2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 #include "skeleton.dtsi"
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/pinctrl/sun4i-a10.h>
57 interrupt-parent = <&gic>;
69 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
70 allwinner,pipeline = "de_be0-lcd0-hdmi";
76 compatible = "allwinner,simple-framebuffer",
78 allwinner,pipeline = "de_be0-lcd0";
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
90 clock-frequency = <24000000>;
91 arm,cpu-registers-not-fw-configured;
95 enable-method = "allwinner,sun6i-a31";
100 compatible = "arm,cortex-a7";
106 compatible = "arm,cortex-a7";
112 compatible = "arm,cortex-a7";
118 compatible = "arm,cortex-a7";
125 reg = <0x40000000 0x80000000>;
129 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
130 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
137 #address-cells = <1>;
143 compatible = "fixed-clock";
144 clock-frequency = <24000000>;
149 compatible = "fixed-clock";
150 clock-frequency = <32768>;
151 clock-output-names = "osc32k";
156 compatible = "allwinner,sun6i-a31-pll1-clk";
157 reg = <0x01c20000 0x4>;
159 clock-output-names = "pll1";
164 compatible = "allwinner,sun6i-a31-pll6-clk";
165 reg = <0x01c20028 0x4>;
167 clock-output-names = "pll6", "pll6x2";
172 compatible = "allwinner,sun4i-a10-cpu-clk";
173 reg = <0x01c20050 0x4>;
176 * PLL1 is listed twice here.
177 * While it looks suspicious, it's actually documented
178 * that way both in the datasheet and in the code from
181 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
182 clock-output-names = "cpu";
187 compatible = "allwinner,sun4i-a10-axi-clk";
188 reg = <0x01c20050 0x4>;
190 clock-output-names = "axi";
193 ahb1_mux: ahb1_mux@01c20054 {
195 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
196 reg = <0x01c20054 0x4>;
197 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
198 clock-output-names = "ahb1_mux";
201 ahb1: ahb1@01c20054 {
203 compatible = "allwinner,sun4i-a10-ahb-clk";
204 reg = <0x01c20054 0x4>;
205 clocks = <&ahb1_mux>;
206 clock-output-names = "ahb1";
209 ahb1_gates: clk@01c20060 {
211 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
212 reg = <0x01c20060 0x8>;
214 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
215 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
216 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
217 "ahb1_nand0", "ahb1_sdram",
218 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
219 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
220 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
221 "ahb1_ehci1", "ahb1_ohci0",
222 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
223 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
224 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
225 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
226 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
227 "ahb1_drc0", "ahb1_drc1";
230 apb1: apb1@01c20054 {
232 compatible = "allwinner,sun4i-a10-apb0-clk";
233 reg = <0x01c20054 0x4>;
235 clock-output-names = "apb1";
238 apb1_gates: clk@01c20068 {
240 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
241 reg = <0x01c20068 0x4>;
243 clock-output-names = "apb1_codec", "apb1_digital_mic",
244 "apb1_pio", "apb1_daudio0",
250 compatible = "allwinner,sun4i-a10-apb1-clk";
251 reg = <0x01c20058 0x4>;
252 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
253 clock-output-names = "apb2";
256 apb2_gates: clk@01c2006c {
258 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
259 reg = <0x01c2006c 0x4>;
261 clock-output-names = "apb2_i2c0", "apb2_i2c1",
262 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
263 "apb2_uart1", "apb2_uart2", "apb2_uart3",
264 "apb2_uart4", "apb2_uart5";
267 mmc0_clk: clk@01c20088 {
269 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c20088 0x4>;
271 clocks = <&osc24M>, <&pll6 0>;
272 clock-output-names = "mmc0";
275 mmc1_clk: clk@01c2008c {
277 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c2008c 0x4>;
279 clocks = <&osc24M>, <&pll6 0>;
280 clock-output-names = "mmc1";
283 mmc2_clk: clk@01c20090 {
285 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c20090 0x4>;
287 clocks = <&osc24M>, <&pll6 0>;
288 clock-output-names = "mmc2";
291 mmc3_clk: clk@01c20094 {
293 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c20094 0x4>;
295 clocks = <&osc24M>, <&pll6 0>;
296 clock-output-names = "mmc3";
299 spi0_clk: clk@01c200a0 {
301 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c200a0 0x4>;
303 clocks = <&osc24M>, <&pll6 0>;
304 clock-output-names = "spi0";
307 spi1_clk: clk@01c200a4 {
309 compatible = "allwinner,sun4i-a10-mod0-clk";
310 reg = <0x01c200a4 0x4>;
311 clocks = <&osc24M>, <&pll6 0>;
312 clock-output-names = "spi1";
315 spi2_clk: clk@01c200a8 {
317 compatible = "allwinner,sun4i-a10-mod0-clk";
318 reg = <0x01c200a8 0x4>;
319 clocks = <&osc24M>, <&pll6 0>;
320 clock-output-names = "spi2";
323 spi3_clk: clk@01c200ac {
325 compatible = "allwinner,sun4i-a10-mod0-clk";
326 reg = <0x01c200ac 0x4>;
327 clocks = <&osc24M>, <&pll6 0>;
328 clock-output-names = "spi3";
331 usb_clk: clk@01c200cc {
334 compatible = "allwinner,sun6i-a31-usb-clk";
335 reg = <0x01c200cc 0x4>;
337 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
338 "usb_ohci0", "usb_ohci1",
343 * The following two are dummy clocks, placeholders used in the gmac_tx
344 * clock. The gmac driver will choose one parent depending on the PHY
345 * interface mode, using clk_set_rate auto-reparenting.
346 * The actual TX clock rate is not controlled by the gmac_tx clock.
348 mii_phy_tx_clk: clk@1 {
350 compatible = "fixed-clock";
351 clock-frequency = <25000000>;
352 clock-output-names = "mii_phy_tx";
355 gmac_int_tx_clk: clk@2 {
357 compatible = "fixed-clock";
358 clock-frequency = <125000000>;
359 clock-output-names = "gmac_int_tx";
362 gmac_tx_clk: clk@01c200d0 {
364 compatible = "allwinner,sun7i-a20-gmac-clk";
365 reg = <0x01c200d0 0x4>;
366 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
367 clock-output-names = "gmac_tx";
372 compatible = "simple-bus";
373 #address-cells = <1>;
377 dma: dma-controller@01c02000 {
378 compatible = "allwinner,sun6i-a31-dma";
379 reg = <0x01c02000 0x1000>;
380 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&ahb1_gates 6>;
382 resets = <&ahb1_rst 6>;
385 /* DMA controller requires AHB1 clocked from PLL6 */
386 assigned-clocks = <&ahb1_mux>;
387 assigned-clock-parents = <&pll6 0>;
391 compatible = "allwinner,sun5i-a13-mmc";
392 reg = <0x01c0f000 0x1000>;
393 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
394 clock-names = "ahb", "mmc";
395 resets = <&ahb1_rst 8>;
397 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
402 compatible = "allwinner,sun5i-a13-mmc";
403 reg = <0x01c10000 0x1000>;
404 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
405 clock-names = "ahb", "mmc";
406 resets = <&ahb1_rst 9>;
408 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
413 compatible = "allwinner,sun5i-a13-mmc";
414 reg = <0x01c11000 0x1000>;
415 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
416 clock-names = "ahb", "mmc";
417 resets = <&ahb1_rst 10>;
419 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
424 compatible = "allwinner,sun5i-a13-mmc";
425 reg = <0x01c12000 0x1000>;
426 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
427 clock-names = "ahb", "mmc";
428 resets = <&ahb1_rst 11>;
430 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
434 usbphy: phy@01c19400 {
435 compatible = "allwinner,sun6i-a31-usb-phy";
436 reg = <0x01c19400 0x10>,
439 reg-names = "phy_ctrl",
442 clocks = <&usb_clk 8>,
445 clock-names = "usb0_phy",
448 resets = <&usb_clk 0>,
451 reset-names = "usb0_reset",
458 ehci0: usb@01c1a000 {
459 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
460 reg = <0x01c1a000 0x100>;
461 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&ahb1_gates 26>;
463 resets = <&ahb1_rst 26>;
469 ohci0: usb@01c1a400 {
470 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
471 reg = <0x01c1a400 0x100>;
472 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
474 resets = <&ahb1_rst 29>;
480 ehci1: usb@01c1b000 {
481 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
482 reg = <0x01c1b000 0x100>;
483 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&ahb1_gates 27>;
485 resets = <&ahb1_rst 27>;
491 ohci1: usb@01c1b400 {
492 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
493 reg = <0x01c1b400 0x100>;
494 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
496 resets = <&ahb1_rst 30>;
502 ohci2: usb@01c1c400 {
503 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
504 reg = <0x01c1c400 0x100>;
505 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
507 resets = <&ahb1_rst 31>;
511 pio: pinctrl@01c20800 {
512 compatible = "allwinner,sun6i-a31-pinctrl";
513 reg = <0x01c20800 0x400>;
514 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&apb1_gates 5>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
525 uart0_pins_a: uart0@0 {
526 allwinner,pins = "PH20", "PH21";
527 allwinner,function = "uart0";
528 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
529 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
532 i2c0_pins_a: i2c0@0 {
533 allwinner,pins = "PH14", "PH15";
534 allwinner,function = "i2c0";
535 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
536 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
539 i2c1_pins_a: i2c1@0 {
540 allwinner,pins = "PH16", "PH17";
541 allwinner,function = "i2c1";
542 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
543 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
546 i2c2_pins_a: i2c2@0 {
547 allwinner,pins = "PH18", "PH19";
548 allwinner,function = "i2c2";
549 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
550 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
553 mmc0_pins_a: mmc0@0 {
554 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
555 allwinner,function = "mmc0";
556 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
557 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
560 gmac_pins_mii_a: gmac_mii@0 {
561 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
562 "PA8", "PA9", "PA11",
563 "PA12", "PA13", "PA14", "PA19",
564 "PA20", "PA21", "PA22", "PA23",
565 "PA24", "PA26", "PA27";
566 allwinner,function = "gmac";
567 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
568 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
571 gmac_pins_gmii_a: gmac_gmii@0 {
572 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
573 "PA4", "PA5", "PA6", "PA7",
574 "PA8", "PA9", "PA10", "PA11",
575 "PA12", "PA13", "PA14", "PA15",
576 "PA16", "PA17", "PA18", "PA19",
577 "PA20", "PA21", "PA22", "PA23",
578 "PA24", "PA25", "PA26", "PA27";
579 allwinner,function = "gmac";
581 * data lines in GMII mode run at 125MHz and
582 * might need a higher signal drive strength
584 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
585 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
588 gmac_pins_rgmii_a: gmac_rgmii@0 {
589 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
590 "PA9", "PA10", "PA11",
591 "PA12", "PA13", "PA14", "PA19",
592 "PA20", "PA25", "PA26", "PA27";
593 allwinner,function = "gmac";
595 * data lines in RGMII mode use DDR mode
596 * and need a higher signal drive strength
598 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
599 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
603 ahb1_rst: reset@01c202c0 {
605 compatible = "allwinner,sun6i-a31-ahb1-reset";
606 reg = <0x01c202c0 0xc>;
609 apb1_rst: reset@01c202d0 {
611 compatible = "allwinner,sun6i-a31-clock-reset";
612 reg = <0x01c202d0 0x4>;
615 apb2_rst: reset@01c202d8 {
617 compatible = "allwinner,sun6i-a31-clock-reset";
618 reg = <0x01c202d8 0x4>;
622 compatible = "allwinner,sun4i-a10-timer";
623 reg = <0x01c20c00 0xa0>;
624 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
632 wdt1: watchdog@01c20ca0 {
633 compatible = "allwinner,sun6i-a31-wdt";
634 reg = <0x01c20ca0 0x20>;
638 compatible = "allwinner,sun6i-a31-ts";
639 reg = <0x01c25000 0x100>;
640 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
641 #thermal-sensor-cells = <0>;
644 uart0: serial@01c28000 {
645 compatible = "snps,dw-apb-uart";
646 reg = <0x01c28000 0x400>;
647 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&apb2_gates 16>;
651 resets = <&apb2_rst 16>;
652 dmas = <&dma 6>, <&dma 6>;
653 dma-names = "rx", "tx";
657 uart1: serial@01c28400 {
658 compatible = "snps,dw-apb-uart";
659 reg = <0x01c28400 0x400>;
660 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&apb2_gates 17>;
664 resets = <&apb2_rst 17>;
665 dmas = <&dma 7>, <&dma 7>;
666 dma-names = "rx", "tx";
670 uart2: serial@01c28800 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0x01c28800 0x400>;
673 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&apb2_gates 18>;
677 resets = <&apb2_rst 18>;
678 dmas = <&dma 8>, <&dma 8>;
679 dma-names = "rx", "tx";
683 uart3: serial@01c28c00 {
684 compatible = "snps,dw-apb-uart";
685 reg = <0x01c28c00 0x400>;
686 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&apb2_gates 19>;
690 resets = <&apb2_rst 19>;
691 dmas = <&dma 9>, <&dma 9>;
692 dma-names = "rx", "tx";
696 uart4: serial@01c29000 {
697 compatible = "snps,dw-apb-uart";
698 reg = <0x01c29000 0x400>;
699 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&apb2_gates 20>;
703 resets = <&apb2_rst 20>;
704 dmas = <&dma 10>, <&dma 10>;
705 dma-names = "rx", "tx";
709 uart5: serial@01c29400 {
710 compatible = "snps,dw-apb-uart";
711 reg = <0x01c29400 0x400>;
712 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&apb2_gates 21>;
716 resets = <&apb2_rst 21>;
717 dmas = <&dma 22>, <&dma 22>;
718 dma-names = "rx", "tx";
723 compatible = "allwinner,sun6i-a31-i2c";
724 reg = <0x01c2ac00 0x400>;
725 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&apb2_gates 0>;
727 resets = <&apb2_rst 0>;
729 #address-cells = <1>;
734 compatible = "allwinner,sun6i-a31-i2c";
735 reg = <0x01c2b000 0x400>;
736 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&apb2_gates 1>;
738 resets = <&apb2_rst 1>;
740 #address-cells = <1>;
745 compatible = "allwinner,sun6i-a31-i2c";
746 reg = <0x01c2b400 0x400>;
747 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&apb2_gates 2>;
749 resets = <&apb2_rst 2>;
751 #address-cells = <1>;
756 compatible = "allwinner,sun6i-a31-i2c";
757 reg = <0x01c2b800 0x400>;
758 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&apb2_gates 3>;
760 resets = <&apb2_rst 3>;
762 #address-cells = <1>;
766 gmac: ethernet@01c30000 {
767 compatible = "allwinner,sun7i-a20-gmac";
768 reg = <0x01c30000 0x1054>;
769 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
770 interrupt-names = "macirq";
771 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
772 clock-names = "stmmaceth", "allwinner_gmac_tx";
773 resets = <&ahb1_rst 17>;
774 reset-names = "stmmaceth";
777 snps,force_sf_dma_mode;
779 #address-cells = <1>;
784 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
785 reg = <0x01c60000 0x1000>;
786 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&ahb1_gates 19>;
791 resets = <&ahb1_rst 19>;
795 compatible = "allwinner,sun6i-a31-spi";
796 reg = <0x01c68000 0x1000>;
797 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&ahb1_gates 20>, <&spi0_clk>;
799 clock-names = "ahb", "mod";
800 dmas = <&dma 23>, <&dma 23>;
801 dma-names = "rx", "tx";
802 resets = <&ahb1_rst 20>;
807 compatible = "allwinner,sun6i-a31-spi";
808 reg = <0x01c69000 0x1000>;
809 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&ahb1_gates 21>, <&spi1_clk>;
811 clock-names = "ahb", "mod";
812 dmas = <&dma 24>, <&dma 24>;
813 dma-names = "rx", "tx";
814 resets = <&ahb1_rst 21>;
819 compatible = "allwinner,sun6i-a31-spi";
820 reg = <0x01c6a000 0x1000>;
821 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&ahb1_gates 22>, <&spi2_clk>;
823 clock-names = "ahb", "mod";
824 dmas = <&dma 25>, <&dma 25>;
825 dma-names = "rx", "tx";
826 resets = <&ahb1_rst 22>;
831 compatible = "allwinner,sun6i-a31-spi";
832 reg = <0x01c6b000 0x1000>;
833 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&ahb1_gates 23>, <&spi3_clk>;
835 clock-names = "ahb", "mod";
836 dmas = <&dma 26>, <&dma 26>;
837 dma-names = "rx", "tx";
838 resets = <&ahb1_rst 23>;
842 gic: interrupt-controller@01c81000 {
843 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
844 reg = <0x01c81000 0x1000>,
848 interrupt-controller;
849 #interrupt-cells = <3>;
850 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
854 compatible = "allwinner,sun6i-a31-rtc";
855 reg = <0x01f00000 0x54>;
856 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
860 nmi_intc: interrupt-controller@01f00c0c {
861 compatible = "allwinner,sun6i-a31-sc-nmi";
862 interrupt-controller;
863 #interrupt-cells = <2>;
864 reg = <0x01f00c0c 0x38>;
865 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
869 compatible = "allwinner,sun6i-a31-prcm";
870 reg = <0x01f01400 0x200>;
873 compatible = "allwinner,sun6i-a31-ar100-clk";
875 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
876 clock-output-names = "ar100";
880 compatible = "fixed-factor-clock";
885 clock-output-names = "ahb0";
889 compatible = "allwinner,sun6i-a31-apb0-clk";
892 clock-output-names = "apb0";
895 apb0_gates: apb0_gates_clk {
896 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
899 clock-output-names = "apb0_pio", "apb0_ir",
900 "apb0_timer", "apb0_p2wi",
901 "apb0_uart", "apb0_1wire",
907 compatible = "allwinner,sun4i-a10-mod0-clk";
908 clocks = <&osc32k>, <&osc24M>;
909 clock-output-names = "ir";
913 compatible = "allwinner,sun6i-a31-clock-reset";
919 compatible = "allwinner,sun6i-a31-cpuconfig";
920 reg = <0x01f01c00 0x300>;
924 compatible = "allwinner,sun5i-a13-ir";
925 clocks = <&apb0_gates 1>, <&ir_clk>;
926 clock-names = "apb", "ir";
927 resets = <&apb0_rst 1>;
928 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
929 reg = <0x01f02000 0x40>;
933 r_pio: pinctrl@01f02c00 {
934 compatible = "allwinner,sun6i-a31-r-pinctrl";
935 reg = <0x01f02c00 0x400>;
936 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&apb0_gates 0>;
939 resets = <&apb0_rst 0>;
941 interrupt-controller;
942 #interrupt-cells = <2>;
947 allwinner,pins = "PL4";
948 allwinner,function = "s_ir";
949 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
950 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;