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Merge branch 'i2c/for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[deliverable/linux.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50 #include "skeleton.dtsi"
51
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53
54 #include <dt-bindings/pinctrl/sun4i-a10.h>
55
56 / {
57 interrupt-parent = <&gic>;
58
59 aliases {
60 ethernet0 = &gmac;
61 };
62
63 chosen {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67
68 framebuffer@0 {
69 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
70 allwinner,pipeline = "de_be0-lcd0-hdmi";
71 clocks = <&pll6 0>;
72 status = "disabled";
73 };
74
75 framebuffer@1 {
76 compatible = "allwinner,simple-framebuffer",
77 "simple-framebuffer";
78 allwinner,pipeline = "de_be0-lcd0";
79 clocks = <&pll6 0>;
80 status = "disabled";
81 };
82 };
83
84 timer {
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
90 clock-frequency = <24000000>;
91 arm,cpu-registers-not-fw-configured;
92 };
93
94 cpus {
95 enable-method = "allwinner,sun6i-a31";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 cpu@0 {
100 compatible = "arm,cortex-a7";
101 device_type = "cpu";
102 reg = <0>;
103 };
104
105 cpu@1 {
106 compatible = "arm,cortex-a7";
107 device_type = "cpu";
108 reg = <1>;
109 };
110
111 cpu@2 {
112 compatible = "arm,cortex-a7";
113 device_type = "cpu";
114 reg = <2>;
115 };
116
117 cpu@3 {
118 compatible = "arm,cortex-a7";
119 device_type = "cpu";
120 reg = <3>;
121 };
122 };
123
124 memory {
125 reg = <0x40000000 0x80000000>;
126 };
127
128 pmu {
129 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
130 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
134 };
135
136 clocks {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges;
140
141 osc24M: osc24M {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 clock-frequency = <24000000>;
145 };
146
147 osc32k: clk@0 {
148 #clock-cells = <0>;
149 compatible = "fixed-clock";
150 clock-frequency = <32768>;
151 clock-output-names = "osc32k";
152 };
153
154 pll1: clk@01c20000 {
155 #clock-cells = <0>;
156 compatible = "allwinner,sun6i-a31-pll1-clk";
157 reg = <0x01c20000 0x4>;
158 clocks = <&osc24M>;
159 clock-output-names = "pll1";
160 };
161
162 pll6: clk@01c20028 {
163 #clock-cells = <1>;
164 compatible = "allwinner,sun6i-a31-pll6-clk";
165 reg = <0x01c20028 0x4>;
166 clocks = <&osc24M>;
167 clock-output-names = "pll6", "pll6x2";
168 };
169
170 cpu: cpu@01c20050 {
171 #clock-cells = <0>;
172 compatible = "allwinner,sun4i-a10-cpu-clk";
173 reg = <0x01c20050 0x4>;
174
175 /*
176 * PLL1 is listed twice here.
177 * While it looks suspicious, it's actually documented
178 * that way both in the datasheet and in the code from
179 * Allwinner.
180 */
181 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
182 clock-output-names = "cpu";
183 };
184
185 axi: axi@01c20050 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-axi-clk";
188 reg = <0x01c20050 0x4>;
189 clocks = <&cpu>;
190 clock-output-names = "axi";
191 };
192
193 ahb1: ahb1@01c20054 {
194 #clock-cells = <0>;
195 compatible = "allwinner,sun6i-a31-ahb1-clk";
196 reg = <0x01c20054 0x4>;
197 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
198 clock-output-names = "ahb1";
199 };
200
201 ahb1_gates: clk@01c20060 {
202 #clock-cells = <1>;
203 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
204 reg = <0x01c20060 0x8>;
205 clocks = <&ahb1>;
206 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
207 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
208 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
209 "ahb1_nand0", "ahb1_sdram",
210 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
211 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
212 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
213 "ahb1_ehci1", "ahb1_ohci0",
214 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
215 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
216 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
217 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
218 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
219 "ahb1_drc0", "ahb1_drc1";
220 };
221
222 apb1: apb1@01c20054 {
223 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-a10-apb0-clk";
225 reg = <0x01c20054 0x4>;
226 clocks = <&ahb1>;
227 clock-output-names = "apb1";
228 };
229
230 apb1_gates: clk@01c20068 {
231 #clock-cells = <1>;
232 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
233 reg = <0x01c20068 0x4>;
234 clocks = <&apb1>;
235 clock-output-names = "apb1_codec", "apb1_digital_mic",
236 "apb1_pio", "apb1_daudio0",
237 "apb1_daudio1";
238 };
239
240 apb2: clk@01c20058 {
241 #clock-cells = <0>;
242 compatible = "allwinner,sun4i-a10-apb1-clk";
243 reg = <0x01c20058 0x4>;
244 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
245 clock-output-names = "apb2";
246 };
247
248 apb2_gates: clk@01c2006c {
249 #clock-cells = <1>;
250 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
251 reg = <0x01c2006c 0x4>;
252 clocks = <&apb2>;
253 clock-output-names = "apb2_i2c0", "apb2_i2c1",
254 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
255 "apb2_uart1", "apb2_uart2", "apb2_uart3",
256 "apb2_uart4", "apb2_uart5";
257 };
258
259 mmc0_clk: clk@01c20088 {
260 #clock-cells = <1>;
261 compatible = "allwinner,sun4i-a10-mmc-clk";
262 reg = <0x01c20088 0x4>;
263 clocks = <&osc24M>, <&pll6 0>;
264 clock-output-names = "mmc0",
265 "mmc0_output",
266 "mmc0_sample";
267 };
268
269 mmc1_clk: clk@01c2008c {
270 #clock-cells = <1>;
271 compatible = "allwinner,sun4i-a10-mmc-clk";
272 reg = <0x01c2008c 0x4>;
273 clocks = <&osc24M>, <&pll6 0>;
274 clock-output-names = "mmc1",
275 "mmc1_output",
276 "mmc1_sample";
277 };
278
279 mmc2_clk: clk@01c20090 {
280 #clock-cells = <1>;
281 compatible = "allwinner,sun4i-a10-mmc-clk";
282 reg = <0x01c20090 0x4>;
283 clocks = <&osc24M>, <&pll6 0>;
284 clock-output-names = "mmc2",
285 "mmc2_output",
286 "mmc2_sample";
287 };
288
289 mmc3_clk: clk@01c20094 {
290 #clock-cells = <1>;
291 compatible = "allwinner,sun4i-a10-mmc-clk";
292 reg = <0x01c20094 0x4>;
293 clocks = <&osc24M>, <&pll6 0>;
294 clock-output-names = "mmc3",
295 "mmc3_output",
296 "mmc3_sample";
297 };
298
299 spi0_clk: clk@01c200a0 {
300 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c200a0 0x4>;
303 clocks = <&osc24M>, <&pll6 0>;
304 clock-output-names = "spi0";
305 };
306
307 spi1_clk: clk@01c200a4 {
308 #clock-cells = <0>;
309 compatible = "allwinner,sun4i-a10-mod0-clk";
310 reg = <0x01c200a4 0x4>;
311 clocks = <&osc24M>, <&pll6 0>;
312 clock-output-names = "spi1";
313 };
314
315 spi2_clk: clk@01c200a8 {
316 #clock-cells = <0>;
317 compatible = "allwinner,sun4i-a10-mod0-clk";
318 reg = <0x01c200a8 0x4>;
319 clocks = <&osc24M>, <&pll6 0>;
320 clock-output-names = "spi2";
321 };
322
323 spi3_clk: clk@01c200ac {
324 #clock-cells = <0>;
325 compatible = "allwinner,sun4i-a10-mod0-clk";
326 reg = <0x01c200ac 0x4>;
327 clocks = <&osc24M>, <&pll6 0>;
328 clock-output-names = "spi3";
329 };
330
331 usb_clk: clk@01c200cc {
332 #clock-cells = <1>;
333 #reset-cells = <1>;
334 compatible = "allwinner,sun6i-a31-usb-clk";
335 reg = <0x01c200cc 0x4>;
336 clocks = <&osc24M>;
337 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
338 "usb_ohci0", "usb_ohci1",
339 "usb_ohci2";
340 };
341
342 /*
343 * The following two are dummy clocks, placeholders used in the gmac_tx
344 * clock. The gmac driver will choose one parent depending on the PHY
345 * interface mode, using clk_set_rate auto-reparenting.
346 * The actual TX clock rate is not controlled by the gmac_tx clock.
347 */
348 mii_phy_tx_clk: clk@1 {
349 #clock-cells = <0>;
350 compatible = "fixed-clock";
351 clock-frequency = <25000000>;
352 clock-output-names = "mii_phy_tx";
353 };
354
355 gmac_int_tx_clk: clk@2 {
356 #clock-cells = <0>;
357 compatible = "fixed-clock";
358 clock-frequency = <125000000>;
359 clock-output-names = "gmac_int_tx";
360 };
361
362 gmac_tx_clk: clk@01c200d0 {
363 #clock-cells = <0>;
364 compatible = "allwinner,sun7i-a20-gmac-clk";
365 reg = <0x01c200d0 0x4>;
366 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
367 clock-output-names = "gmac_tx";
368 };
369 };
370
371 soc@01c00000 {
372 compatible = "simple-bus";
373 #address-cells = <1>;
374 #size-cells = <1>;
375 ranges;
376
377 dma: dma-controller@01c02000 {
378 compatible = "allwinner,sun6i-a31-dma";
379 reg = <0x01c02000 0x1000>;
380 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&ahb1_gates 6>;
382 resets = <&ahb1_rst 6>;
383 #dma-cells = <1>;
384
385 /* DMA controller requires AHB1 clocked from PLL6 */
386 assigned-clocks = <&ahb1>;
387 assigned-clock-parents = <&pll6 0>;
388 };
389
390 mmc0: mmc@01c0f000 {
391 compatible = "allwinner,sun5i-a13-mmc";
392 reg = <0x01c0f000 0x1000>;
393 clocks = <&ahb1_gates 8>,
394 <&mmc0_clk 0>,
395 <&mmc0_clk 1>,
396 <&mmc0_clk 2>;
397 clock-names = "ahb",
398 "mmc",
399 "output",
400 "sample";
401 resets = <&ahb1_rst 8>;
402 reset-names = "ahb";
403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
404 status = "disabled";
405 };
406
407 mmc1: mmc@01c10000 {
408 compatible = "allwinner,sun5i-a13-mmc";
409 reg = <0x01c10000 0x1000>;
410 clocks = <&ahb1_gates 9>,
411 <&mmc1_clk 0>,
412 <&mmc1_clk 1>,
413 <&mmc1_clk 2>;
414 clock-names = "ahb",
415 "mmc",
416 "output",
417 "sample";
418 resets = <&ahb1_rst 9>;
419 reset-names = "ahb";
420 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
421 status = "disabled";
422 };
423
424 mmc2: mmc@01c11000 {
425 compatible = "allwinner,sun5i-a13-mmc";
426 reg = <0x01c11000 0x1000>;
427 clocks = <&ahb1_gates 10>,
428 <&mmc2_clk 0>,
429 <&mmc2_clk 1>,
430 <&mmc2_clk 2>;
431 clock-names = "ahb",
432 "mmc",
433 "output",
434 "sample";
435 resets = <&ahb1_rst 10>;
436 reset-names = "ahb";
437 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
438 status = "disabled";
439 };
440
441 mmc3: mmc@01c12000 {
442 compatible = "allwinner,sun5i-a13-mmc";
443 reg = <0x01c12000 0x1000>;
444 clocks = <&ahb1_gates 11>,
445 <&mmc3_clk 0>,
446 <&mmc3_clk 1>,
447 <&mmc3_clk 2>;
448 clock-names = "ahb",
449 "mmc",
450 "output",
451 "sample";
452 resets = <&ahb1_rst 11>;
453 reset-names = "ahb";
454 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
455 status = "disabled";
456 };
457
458 usbphy: phy@01c19400 {
459 compatible = "allwinner,sun6i-a31-usb-phy";
460 reg = <0x01c19400 0x10>,
461 <0x01c1a800 0x4>,
462 <0x01c1b800 0x4>;
463 reg-names = "phy_ctrl",
464 "pmu1",
465 "pmu2";
466 clocks = <&usb_clk 8>,
467 <&usb_clk 9>,
468 <&usb_clk 10>;
469 clock-names = "usb0_phy",
470 "usb1_phy",
471 "usb2_phy";
472 resets = <&usb_clk 0>,
473 <&usb_clk 1>,
474 <&usb_clk 2>;
475 reset-names = "usb0_reset",
476 "usb1_reset",
477 "usb2_reset";
478 status = "disabled";
479 #phy-cells = <1>;
480 };
481
482 ehci0: usb@01c1a000 {
483 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
484 reg = <0x01c1a000 0x100>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&ahb1_gates 26>;
487 resets = <&ahb1_rst 26>;
488 phys = <&usbphy 1>;
489 phy-names = "usb";
490 status = "disabled";
491 };
492
493 ohci0: usb@01c1a400 {
494 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
495 reg = <0x01c1a400 0x100>;
496 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
498 resets = <&ahb1_rst 29>;
499 phys = <&usbphy 1>;
500 phy-names = "usb";
501 status = "disabled";
502 };
503
504 ehci1: usb@01c1b000 {
505 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
506 reg = <0x01c1b000 0x100>;
507 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&ahb1_gates 27>;
509 resets = <&ahb1_rst 27>;
510 phys = <&usbphy 2>;
511 phy-names = "usb";
512 status = "disabled";
513 };
514
515 ohci1: usb@01c1b400 {
516 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
517 reg = <0x01c1b400 0x100>;
518 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
520 resets = <&ahb1_rst 30>;
521 phys = <&usbphy 2>;
522 phy-names = "usb";
523 status = "disabled";
524 };
525
526 ohci2: usb@01c1c400 {
527 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
528 reg = <0x01c1c400 0x100>;
529 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
531 resets = <&ahb1_rst 31>;
532 status = "disabled";
533 };
534
535 pio: pinctrl@01c20800 {
536 compatible = "allwinner,sun6i-a31-pinctrl";
537 reg = <0x01c20800 0x400>;
538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&apb1_gates 5>;
543 gpio-controller;
544 interrupt-controller;
545 #interrupt-cells = <2>;
546 #size-cells = <0>;
547 #gpio-cells = <3>;
548
549 uart0_pins_a: uart0@0 {
550 allwinner,pins = "PH20", "PH21";
551 allwinner,function = "uart0";
552 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
553 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
554 };
555
556 i2c0_pins_a: i2c0@0 {
557 allwinner,pins = "PH14", "PH15";
558 allwinner,function = "i2c0";
559 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
560 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
561 };
562
563 i2c1_pins_a: i2c1@0 {
564 allwinner,pins = "PH16", "PH17";
565 allwinner,function = "i2c1";
566 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
567 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
568 };
569
570 i2c2_pins_a: i2c2@0 {
571 allwinner,pins = "PH18", "PH19";
572 allwinner,function = "i2c2";
573 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
574 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
575 };
576
577 mmc0_pins_a: mmc0@0 {
578 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
579 allwinner,function = "mmc0";
580 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
581 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
582 };
583
584 gmac_pins_mii_a: gmac_mii@0 {
585 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
586 "PA8", "PA9", "PA11",
587 "PA12", "PA13", "PA14", "PA19",
588 "PA20", "PA21", "PA22", "PA23",
589 "PA24", "PA26", "PA27";
590 allwinner,function = "gmac";
591 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
592 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
593 };
594
595 gmac_pins_gmii_a: gmac_gmii@0 {
596 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
597 "PA4", "PA5", "PA6", "PA7",
598 "PA8", "PA9", "PA10", "PA11",
599 "PA12", "PA13", "PA14", "PA15",
600 "PA16", "PA17", "PA18", "PA19",
601 "PA20", "PA21", "PA22", "PA23",
602 "PA24", "PA25", "PA26", "PA27";
603 allwinner,function = "gmac";
604 /*
605 * data lines in GMII mode run at 125MHz and
606 * might need a higher signal drive strength
607 */
608 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
609 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
610 };
611
612 gmac_pins_rgmii_a: gmac_rgmii@0 {
613 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
614 "PA9", "PA10", "PA11",
615 "PA12", "PA13", "PA14", "PA19",
616 "PA20", "PA25", "PA26", "PA27";
617 allwinner,function = "gmac";
618 /*
619 * data lines in RGMII mode use DDR mode
620 * and need a higher signal drive strength
621 */
622 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
623 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
624 };
625 };
626
627 ahb1_rst: reset@01c202c0 {
628 #reset-cells = <1>;
629 compatible = "allwinner,sun6i-a31-ahb1-reset";
630 reg = <0x01c202c0 0xc>;
631 };
632
633 apb1_rst: reset@01c202d0 {
634 #reset-cells = <1>;
635 compatible = "allwinner,sun6i-a31-clock-reset";
636 reg = <0x01c202d0 0x4>;
637 };
638
639 apb2_rst: reset@01c202d8 {
640 #reset-cells = <1>;
641 compatible = "allwinner,sun6i-a31-clock-reset";
642 reg = <0x01c202d8 0x4>;
643 };
644
645 timer@01c20c00 {
646 compatible = "allwinner,sun4i-a10-timer";
647 reg = <0x01c20c00 0xa0>;
648 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&osc24M>;
654 };
655
656 wdt1: watchdog@01c20ca0 {
657 compatible = "allwinner,sun6i-a31-wdt";
658 reg = <0x01c20ca0 0x20>;
659 };
660
661 rtp: rtp@01c25000 {
662 compatible = "allwinner,sun6i-a31-ts";
663 reg = <0x01c25000 0x100>;
664 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
665 #thermal-sensor-cells = <0>;
666 };
667
668 uart0: serial@01c28000 {
669 compatible = "snps,dw-apb-uart";
670 reg = <0x01c28000 0x400>;
671 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
672 reg-shift = <2>;
673 reg-io-width = <4>;
674 clocks = <&apb2_gates 16>;
675 resets = <&apb2_rst 16>;
676 dmas = <&dma 6>, <&dma 6>;
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 uart1: serial@01c28400 {
682 compatible = "snps,dw-apb-uart";
683 reg = <0x01c28400 0x400>;
684 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
685 reg-shift = <2>;
686 reg-io-width = <4>;
687 clocks = <&apb2_gates 17>;
688 resets = <&apb2_rst 17>;
689 dmas = <&dma 7>, <&dma 7>;
690 dma-names = "rx", "tx";
691 status = "disabled";
692 };
693
694 uart2: serial@01c28800 {
695 compatible = "snps,dw-apb-uart";
696 reg = <0x01c28800 0x400>;
697 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
698 reg-shift = <2>;
699 reg-io-width = <4>;
700 clocks = <&apb2_gates 18>;
701 resets = <&apb2_rst 18>;
702 dmas = <&dma 8>, <&dma 8>;
703 dma-names = "rx", "tx";
704 status = "disabled";
705 };
706
707 uart3: serial@01c28c00 {
708 compatible = "snps,dw-apb-uart";
709 reg = <0x01c28c00 0x400>;
710 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
711 reg-shift = <2>;
712 reg-io-width = <4>;
713 clocks = <&apb2_gates 19>;
714 resets = <&apb2_rst 19>;
715 dmas = <&dma 9>, <&dma 9>;
716 dma-names = "rx", "tx";
717 status = "disabled";
718 };
719
720 uart4: serial@01c29000 {
721 compatible = "snps,dw-apb-uart";
722 reg = <0x01c29000 0x400>;
723 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
724 reg-shift = <2>;
725 reg-io-width = <4>;
726 clocks = <&apb2_gates 20>;
727 resets = <&apb2_rst 20>;
728 dmas = <&dma 10>, <&dma 10>;
729 dma-names = "rx", "tx";
730 status = "disabled";
731 };
732
733 uart5: serial@01c29400 {
734 compatible = "snps,dw-apb-uart";
735 reg = <0x01c29400 0x400>;
736 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
737 reg-shift = <2>;
738 reg-io-width = <4>;
739 clocks = <&apb2_gates 21>;
740 resets = <&apb2_rst 21>;
741 dmas = <&dma 22>, <&dma 22>;
742 dma-names = "rx", "tx";
743 status = "disabled";
744 };
745
746 i2c0: i2c@01c2ac00 {
747 compatible = "allwinner,sun6i-a31-i2c";
748 reg = <0x01c2ac00 0x400>;
749 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&apb2_gates 0>;
751 resets = <&apb2_rst 0>;
752 status = "disabled";
753 #address-cells = <1>;
754 #size-cells = <0>;
755 };
756
757 i2c1: i2c@01c2b000 {
758 compatible = "allwinner,sun6i-a31-i2c";
759 reg = <0x01c2b000 0x400>;
760 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&apb2_gates 1>;
762 resets = <&apb2_rst 1>;
763 status = "disabled";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 };
767
768 i2c2: i2c@01c2b400 {
769 compatible = "allwinner,sun6i-a31-i2c";
770 reg = <0x01c2b400 0x400>;
771 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&apb2_gates 2>;
773 resets = <&apb2_rst 2>;
774 status = "disabled";
775 #address-cells = <1>;
776 #size-cells = <0>;
777 };
778
779 i2c3: i2c@01c2b800 {
780 compatible = "allwinner,sun6i-a31-i2c";
781 reg = <0x01c2b800 0x400>;
782 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&apb2_gates 3>;
784 resets = <&apb2_rst 3>;
785 status = "disabled";
786 #address-cells = <1>;
787 #size-cells = <0>;
788 };
789
790 gmac: ethernet@01c30000 {
791 compatible = "allwinner,sun7i-a20-gmac";
792 reg = <0x01c30000 0x1054>;
793 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "macirq";
795 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
796 clock-names = "stmmaceth", "allwinner_gmac_tx";
797 resets = <&ahb1_rst 17>;
798 reset-names = "stmmaceth";
799 snps,pbl = <2>;
800 snps,fixed-burst;
801 snps,force_sf_dma_mode;
802 status = "disabled";
803 #address-cells = <1>;
804 #size-cells = <0>;
805 };
806
807 timer@01c60000 {
808 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
809 reg = <0x01c60000 0x1000>;
810 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&ahb1_gates 19>;
815 resets = <&ahb1_rst 19>;
816 };
817
818 spi0: spi@01c68000 {
819 compatible = "allwinner,sun6i-a31-spi";
820 reg = <0x01c68000 0x1000>;
821 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&ahb1_gates 20>, <&spi0_clk>;
823 clock-names = "ahb", "mod";
824 dmas = <&dma 23>, <&dma 23>;
825 dma-names = "rx", "tx";
826 resets = <&ahb1_rst 20>;
827 status = "disabled";
828 };
829
830 spi1: spi@01c69000 {
831 compatible = "allwinner,sun6i-a31-spi";
832 reg = <0x01c69000 0x1000>;
833 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&ahb1_gates 21>, <&spi1_clk>;
835 clock-names = "ahb", "mod";
836 dmas = <&dma 24>, <&dma 24>;
837 dma-names = "rx", "tx";
838 resets = <&ahb1_rst 21>;
839 status = "disabled";
840 };
841
842 spi2: spi@01c6a000 {
843 compatible = "allwinner,sun6i-a31-spi";
844 reg = <0x01c6a000 0x1000>;
845 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&ahb1_gates 22>, <&spi2_clk>;
847 clock-names = "ahb", "mod";
848 dmas = <&dma 25>, <&dma 25>;
849 dma-names = "rx", "tx";
850 resets = <&ahb1_rst 22>;
851 status = "disabled";
852 };
853
854 spi3: spi@01c6b000 {
855 compatible = "allwinner,sun6i-a31-spi";
856 reg = <0x01c6b000 0x1000>;
857 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&ahb1_gates 23>, <&spi3_clk>;
859 clock-names = "ahb", "mod";
860 dmas = <&dma 26>, <&dma 26>;
861 dma-names = "rx", "tx";
862 resets = <&ahb1_rst 23>;
863 status = "disabled";
864 };
865
866 gic: interrupt-controller@01c81000 {
867 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
868 reg = <0x01c81000 0x1000>,
869 <0x01c82000 0x1000>,
870 <0x01c84000 0x2000>,
871 <0x01c86000 0x2000>;
872 interrupt-controller;
873 #interrupt-cells = <3>;
874 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
875 };
876
877 rtc: rtc@01f00000 {
878 compatible = "allwinner,sun6i-a31-rtc";
879 reg = <0x01f00000 0x54>;
880 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
882 };
883
884 nmi_intc: interrupt-controller@01f00c0c {
885 compatible = "allwinner,sun6i-a31-sc-nmi";
886 interrupt-controller;
887 #interrupt-cells = <2>;
888 reg = <0x01f00c0c 0x38>;
889 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
890 };
891
892 prcm@01f01400 {
893 compatible = "allwinner,sun6i-a31-prcm";
894 reg = <0x01f01400 0x200>;
895
896 ar100: ar100_clk {
897 compatible = "allwinner,sun6i-a31-ar100-clk";
898 #clock-cells = <0>;
899 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
900 clock-output-names = "ar100";
901 };
902
903 ahb0: ahb0_clk {
904 compatible = "fixed-factor-clock";
905 #clock-cells = <0>;
906 clock-div = <1>;
907 clock-mult = <1>;
908 clocks = <&ar100>;
909 clock-output-names = "ahb0";
910 };
911
912 apb0: apb0_clk {
913 compatible = "allwinner,sun6i-a31-apb0-clk";
914 #clock-cells = <0>;
915 clocks = <&ahb0>;
916 clock-output-names = "apb0";
917 };
918
919 apb0_gates: apb0_gates_clk {
920 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
921 #clock-cells = <1>;
922 clocks = <&apb0>;
923 clock-output-names = "apb0_pio", "apb0_ir",
924 "apb0_timer", "apb0_p2wi",
925 "apb0_uart", "apb0_1wire",
926 "apb0_i2c";
927 };
928
929 ir_clk: ir_clk {
930 #clock-cells = <0>;
931 compatible = "allwinner,sun4i-a10-mod0-clk";
932 clocks = <&osc32k>, <&osc24M>;
933 clock-output-names = "ir";
934 };
935
936 apb0_rst: apb0_rst {
937 compatible = "allwinner,sun6i-a31-clock-reset";
938 #reset-cells = <1>;
939 };
940 };
941
942 cpucfg@01f01c00 {
943 compatible = "allwinner,sun6i-a31-cpuconfig";
944 reg = <0x01f01c00 0x300>;
945 };
946
947 ir: ir@01f02000 {
948 compatible = "allwinner,sun5i-a13-ir";
949 clocks = <&apb0_gates 1>, <&ir_clk>;
950 clock-names = "apb", "ir";
951 resets = <&apb0_rst 1>;
952 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
953 reg = <0x01f02000 0x40>;
954 status = "disabled";
955 };
956
957 r_pio: pinctrl@01f02c00 {
958 compatible = "allwinner,sun6i-a31-r-pinctrl";
959 reg = <0x01f02c00 0x400>;
960 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&apb0_gates 0>;
963 resets = <&apb0_rst 0>;
964 gpio-controller;
965 interrupt-controller;
966 #interrupt-cells = <2>;
967 #size-cells = <0>;
968 #gpio-cells = <3>;
969
970 ir_pins_a: ir@0 {
971 allwinner,pins = "PL4";
972 allwinner,function = "s_ir";
973 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
974 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
975 };
976 };
977 };
978 };
Linux kernel - Deliverables
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