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Merge tag 'drm-intel-next-2016-01-24' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / arch / arm / boot / dts / sun8i-h3.dtsi
1 /*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include "skeleton.dtsi"
44
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
47
48 / {
49 interrupt-parent = <&gic>;
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu@0 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0>;
59 };
60
61 cpu@1 {
62 compatible = "arm,cortex-a7";
63 device_type = "cpu";
64 reg = <1>;
65 };
66
67 cpu@2 {
68 compatible = "arm,cortex-a7";
69 device_type = "cpu";
70 reg = <2>;
71 };
72
73 cpu@3 {
74 compatible = "arm,cortex-a7";
75 device_type = "cpu";
76 reg = <3>;
77 };
78 };
79
80 timer {
81 compatible = "arm,armv7-timer";
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
86 };
87
88 clocks {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 osc24M: osc24M_clk {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <24000000>;
97 clock-output-names = "osc24M";
98 };
99
100 osc32k: osc32k_clk {
101 #clock-cells = <0>;
102 compatible = "fixed-clock";
103 clock-frequency = <32768>;
104 clock-output-names = "osc32k";
105 };
106
107 pll1: clk@01c20000 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun8i-a23-pll1-clk";
110 reg = <0x01c20000 0x4>;
111 clocks = <&osc24M>;
112 clock-output-names = "pll1";
113 };
114
115 /* dummy clock until actually implemented */
116 pll5: pll5_clk {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "pll5";
121 };
122
123 pll6: clk@01c20028 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-pll6-clk";
126 reg = <0x01c20028 0x4>;
127 clocks = <&osc24M>;
128 clock-output-names = "pll6", "pll6x2";
129 };
130
131 pll6d2: pll6d2_clk {
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clock-div = <2>;
135 clock-mult = <1>;
136 clocks = <&pll6 0>;
137 clock-output-names = "pll6d2";
138 };
139
140 /* dummy clock until pll6 can be reused */
141 pll8: pll8_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 clock-frequency = <1>;
145 clock-output-names = "pll8";
146 };
147
148 cpu: cpu_clk@01c20050 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-cpu-clk";
151 reg = <0x01c20050 0x4>;
152 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
153 clock-output-names = "cpu";
154 };
155
156 axi: axi_clk@01c20050 {
157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-a10-axi-clk";
159 reg = <0x01c20050 0x4>;
160 clocks = <&cpu>;
161 clock-output-names = "axi";
162 };
163
164 ahb1: ahb1_clk@01c20054 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun6i-a31-ahb1-clk";
167 reg = <0x01c20054 0x4>;
168 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
169 clock-output-names = "ahb1";
170 };
171
172 ahb2: ahb2_clk@01c2005c {
173 #clock-cells = <0>;
174 compatible = "allwinner,sun8i-h3-ahb2-clk";
175 reg = <0x01c2005c 0x4>;
176 clocks = <&ahb1>, <&pll6d2>;
177 clock-output-names = "ahb2";
178 };
179
180 apb1: apb1_clk@01c20054 {
181 #clock-cells = <0>;
182 compatible = "allwinner,sun4i-a10-apb0-clk";
183 reg = <0x01c20054 0x4>;
184 clocks = <&ahb1>;
185 clock-output-names = "apb1";
186 };
187
188 apb2: apb2_clk@01c20058 {
189 #clock-cells = <0>;
190 compatible = "allwinner,sun4i-a10-apb1-clk";
191 reg = <0x01c20058 0x4>;
192 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
193 clock-output-names = "apb2";
194 };
195
196 bus_gates: clk@01c20060 {
197 #clock-cells = <1>;
198 compatible = "allwinner,sun8i-h3-bus-gates-clk";
199 reg = <0x01c20060 0x14>;
200 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
201 clock-names = "ahb1", "ahb2", "apb1", "apb2";
202 clock-indices = <5>, <6>, <8>,
203 <9>, <10>, <13>,
204 <14>, <17>, <18>,
205 <19>, <20>,
206 <21>, <23>,
207 <24>, <25>,
208 <26>, <27>,
209 <28>, <29>,
210 <30>, <31>, <32>,
211 <35>, <36>, <37>,
212 <40>, <41>, <43>,
213 <44>, <52>, <53>,
214 <54>, <64>,
215 <65>, <69>, <72>,
216 <76>, <77>, <78>,
217 <96>, <97>, <98>,
218 <112>, <113>,
219 <114>, <115>,
220 <116>, <128>, <135>;
221 clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
222 "bus_mmc1", "bus_mmc2", "bus_nand",
223 "bus_sdram", "bus_gmac", "bus_ts",
224 "bus_hstimer", "bus_spi0",
225 "bus_spi1", "bus_otg",
226 "bus_otg_ehci0", "bus_ehci1",
227 "bus_ehci2", "bus_ehci3",
228 "bus_otg_ohci0", "bus_ohci1",
229 "bus_ohci2", "bus_ohci3", "bus_ve",
230 "bus_lcd0", "bus_lcd1", "bus_deint",
231 "bus_csi", "bus_tve", "bus_hdmi",
232 "bus_de", "bus_gpu", "bus_msgbox",
233 "bus_spinlock", "bus_codec",
234 "bus_spdif", "bus_pio", "bus_ths",
235 "bus_i2s0", "bus_i2s1", "bus_i2s2",
236 "bus_i2c0", "bus_i2c1", "bus_i2c2",
237 "bus_uart0", "bus_uart1",
238 "bus_uart2", "bus_uart3",
239 "bus_scr", "bus_ephy", "bus_dbg";
240 };
241
242 mmc0_clk: clk@01c20088 {
243 #clock-cells = <1>;
244 compatible = "allwinner,sun4i-a10-mmc-clk";
245 reg = <0x01c20088 0x4>;
246 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
247 clock-output-names = "mmc0",
248 "mmc0_output",
249 "mmc0_sample";
250 };
251
252 mmc1_clk: clk@01c2008c {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun4i-a10-mmc-clk";
255 reg = <0x01c2008c 0x4>;
256 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
257 clock-output-names = "mmc1",
258 "mmc1_output",
259 "mmc1_sample";
260 };
261
262 mmc2_clk: clk@01c20090 {
263 #clock-cells = <1>;
264 compatible = "allwinner,sun4i-a10-mmc-clk";
265 reg = <0x01c20090 0x4>;
266 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
267 clock-output-names = "mmc2",
268 "mmc2_output",
269 "mmc2_sample";
270 };
271
272 mbus_clk: clk@01c2015c {
273 #clock-cells = <0>;
274 compatible = "allwinner,sun8i-a23-mbus-clk";
275 reg = <0x01c2015c 0x4>;
276 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
277 clock-output-names = "mbus";
278 };
279 };
280
281 soc {
282 compatible = "simple-bus";
283 #address-cells = <1>;
284 #size-cells = <1>;
285 ranges;
286
287 dma: dma-controller@01c02000 {
288 compatible = "allwinner,sun8i-h3-dma";
289 reg = <0x01c02000 0x1000>;
290 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&bus_gates 6>;
292 resets = <&ahb_rst 6>;
293 #dma-cells = <1>;
294 };
295
296 mmc0: mmc@01c0f000 {
297 compatible = "allwinner,sun5i-a13-mmc";
298 reg = <0x01c0f000 0x1000>;
299 clocks = <&bus_gates 8>,
300 <&mmc0_clk 0>,
301 <&mmc0_clk 1>,
302 <&mmc0_clk 2>;
303 clock-names = "ahb",
304 "mmc",
305 "output",
306 "sample";
307 resets = <&ahb_rst 8>;
308 reset-names = "ahb";
309 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
310 status = "disabled";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 };
314
315 mmc1: mmc@01c10000 {
316 compatible = "allwinner,sun5i-a13-mmc";
317 reg = <0x01c10000 0x1000>;
318 clocks = <&bus_gates 9>,
319 <&mmc1_clk 0>,
320 <&mmc1_clk 1>,
321 <&mmc1_clk 2>;
322 clock-names = "ahb",
323 "mmc",
324 "output",
325 "sample";
326 resets = <&ahb_rst 9>;
327 reset-names = "ahb";
328 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
329 status = "disabled";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 };
333
334 mmc2: mmc@01c11000 {
335 compatible = "allwinner,sun5i-a13-mmc";
336 reg = <0x01c11000 0x1000>;
337 clocks = <&bus_gates 10>,
338 <&mmc2_clk 0>,
339 <&mmc2_clk 1>,
340 <&mmc2_clk 2>;
341 clock-names = "ahb",
342 "mmc",
343 "output",
344 "sample";
345 resets = <&ahb_rst 10>;
346 reset-names = "ahb";
347 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
348 status = "disabled";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 };
352
353 pio: pinctrl@01c20800 {
354 compatible = "allwinner,sun8i-h3-pinctrl";
355 reg = <0x01c20800 0x400>;
356 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&bus_gates 69>;
359 gpio-controller;
360 #gpio-cells = <3>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363
364 uart0_pins_a: uart0@0 {
365 allwinner,pins = "PA4", "PA5";
366 allwinner,function = "uart0";
367 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
368 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
369 };
370
371 mmc0_pins_a: mmc0@0 {
372 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
373 "PF4", "PF5";
374 allwinner,function = "mmc0";
375 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
376 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
377 };
378
379 mmc0_cd_pin: mmc0_cd_pin@0 {
380 allwinner,pins = "PF6";
381 allwinner,function = "gpio_in";
382 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
383 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
384 };
385
386 mmc1_pins_a: mmc1@0 {
387 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
388 "PG4", "PG5";
389 allwinner,function = "mmc1";
390 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
391 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
392 };
393 };
394
395 ahb_rst: reset@01c202c0 {
396 #reset-cells = <1>;
397 compatible = "allwinner,sun6i-a31-ahb1-reset";
398 reg = <0x01c202c0 0xc>;
399 };
400
401 apb1_rst: reset@01c202d0 {
402 #reset-cells = <1>;
403 compatible = "allwinner,sun6i-a31-clock-reset";
404 reg = <0x01c202d0 0x4>;
405 };
406
407 apb2_rst: reset@01c202d8 {
408 #reset-cells = <1>;
409 compatible = "allwinner,sun6i-a31-clock-reset";
410 reg = <0x01c202d8 0x4>;
411 };
412
413 timer@01c20c00 {
414 compatible = "allwinner,sun4i-a10-timer";
415 reg = <0x01c20c00 0xa0>;
416 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&osc24M>;
419 };
420
421 wdt0: watchdog@01c20ca0 {
422 compatible = "allwinner,sun6i-a31-wdt";
423 reg = <0x01c20ca0 0x20>;
424 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
425 };
426
427 uart0: serial@01c28000 {
428 compatible = "snps,dw-apb-uart";
429 reg = <0x01c28000 0x400>;
430 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
431 reg-shift = <2>;
432 reg-io-width = <4>;
433 clocks = <&bus_gates 112>;
434 resets = <&apb2_rst 16>;
435 dmas = <&dma 6>, <&dma 6>;
436 dma-names = "rx", "tx";
437 status = "disabled";
438 };
439
440 uart1: serial@01c28400 {
441 compatible = "snps,dw-apb-uart";
442 reg = <0x01c28400 0x400>;
443 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
444 reg-shift = <2>;
445 reg-io-width = <4>;
446 clocks = <&bus_gates 113>;
447 resets = <&apb2_rst 17>;
448 dmas = <&dma 7>, <&dma 7>;
449 dma-names = "rx", "tx";
450 status = "disabled";
451 };
452
453 uart2: serial@01c28800 {
454 compatible = "snps,dw-apb-uart";
455 reg = <0x01c28800 0x400>;
456 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
457 reg-shift = <2>;
458 reg-io-width = <4>;
459 clocks = <&bus_gates 114>;
460 resets = <&apb2_rst 18>;
461 dmas = <&dma 8>, <&dma 8>;
462 dma-names = "rx", "tx";
463 status = "disabled";
464 };
465
466 uart3: serial@01c28c00 {
467 compatible = "snps,dw-apb-uart";
468 reg = <0x01c28c00 0x400>;
469 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
470 reg-shift = <2>;
471 reg-io-width = <4>;
472 clocks = <&bus_gates 115>;
473 resets = <&apb2_rst 19>;
474 dmas = <&dma 9>, <&dma 9>;
475 dma-names = "rx", "tx";
476 status = "disabled";
477 };
478
479 gic: interrupt-controller@01c81000 {
480 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
481 reg = <0x01c81000 0x1000>,
482 <0x01c82000 0x1000>,
483 <0x01c84000 0x2000>,
484 <0x01c86000 0x2000>;
485 interrupt-controller;
486 #interrupt-cells = <3>;
487 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
488 };
489
490 rtc: rtc@01f00000 {
491 compatible = "allwinner,sun6i-a31-rtc";
492 reg = <0x01f00000 0x54>;
493 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
495 };
496 };
497 };
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