arch/arm/boot/dts/tegra114.dtsi

   1 #include <dt-bindings/clock/tegra114-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra114-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         compatible = "nvidia,tegra114";
  11         interrupt-parent = <&gic>;
  12
  13         host1x@50000000 {
  14                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  15                 reg = <0x50000000 0x00028000>;
  16                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  17                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  18                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  19                 resets = <&tegra_car 28>;
  20                 reset-names = "host1x";
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x01000000>;
  26
  27                 gr2d@54140000 {
  28                         compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
  29                         reg = <0x54140000 0x00040000>;
  30                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  31                         clocks = <&tegra_car TEGRA114_CLK_GR2D>;
  32                         resets = <&tegra_car 21>;
  33                         reset-names = "2d";
  34                 };
  35
  36                 gr3d@54180000 {
  37                         compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
  38                         reg = <0x54180000 0x00040000>;
  39                         clocks = <&tegra_car TEGRA114_CLK_GR3D>;
  40                         resets = <&tegra_car 24>;
  41                         reset-names = "3d";
  42                 };
  43
  44                 dc@54200000 {
  45                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  46                         reg = <0x54200000 0x00040000>;
  47                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  49                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  50                         clock-names = "dc", "parent";
  51                         resets = <&tegra_car 27>;
  52                         reset-names = "dc";
  53
  54                         iommus = <&mc TEGRA_SWGROUP_DC>;
  55
  56                         nvidia,head = <0>;
  57
  58                         rgb {
  59                                 status = "disabled";
  60                         };
  61                 };
  62
  63                 dc@54240000 {
  64                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  65                         reg = <0x54240000 0x00040000>;
  66                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  67                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  68                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  69                         clock-names = "dc", "parent";
  70                         resets = <&tegra_car 26>;
  71                         reset-names = "dc";
  72
  73                         iommus = <&mc TEGRA_SWGROUP_DCB>;
  74
  75                         nvidia,head = <1>;
  76
  77                         rgb {
  78                                 status = "disabled";
  79                         };
  80                 };
  81
  82                 hdmi@54280000 {
  83                         compatible = "nvidia,tegra114-hdmi";
  84                         reg = <0x54280000 0x00040000>;
  85                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  86                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  87                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  88                         clock-names = "hdmi", "parent";
  89                         resets = <&tegra_car 51>;
  90                         reset-names = "hdmi";
  91                         status = "disabled";
  92                 };
  93
  94                 dsi@54300000 {
  95                         compatible = "nvidia,tegra114-dsi";
  96                         reg = <0x54300000 0x00040000>;
  97                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
  98                                  <&tegra_car TEGRA114_CLK_DSIALP>,
  99                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
 100                         clock-names = "dsi", "lp", "parent";
 101                         resets = <&tegra_car 48>;
 102                         reset-names = "dsi";
 103                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
 104                         status = "disabled";
 105
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                 };
 109
 110                 dsi@54400000 {
 111                         compatible = "nvidia,tegra114-dsi";
 112                         reg = <0x54400000 0x00040000>;
 113                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
 114                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
 115                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 116                         clock-names = "dsi", "lp", "parent";
 117                         resets = <&tegra_car 82>;
 118                         reset-names = "dsi";
 119                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 120                         status = "disabled";
 121
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                 };
 125         };
 126
 127         gic: interrupt-controller@50041000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 interrupt-controller;
 131                 reg = <0x50041000 0x1000>,
 132                       <0x50042000 0x1000>,
 133                       <0x50044000 0x2000>,
 134                       <0x50046000 0x2000>;
 135                 interrupts = <GIC_PPI 9
 136                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 137         };
 138
 139         timer@60005000 {
 140                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 141                 reg = <0x60005000 0x400>;
 142                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 148                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 149         };
 150
 151         tegra_car: clock@60006000 {
 152                 compatible = "nvidia,tegra114-car";
 153                 reg = <0x60006000 0x1000>;
 154                 #clock-cells = <1>;
 155                 #reset-cells = <1>;
 156         };
 157
 158         flow-controller@60007000 {
 159                 compatible = "nvidia,tegra114-flowctrl";
 160                 reg = <0x60007000 0x1000>;
 161         };
 162
 163         apbdma: dma@6000a000 {
 164                 compatible = "nvidia,tegra114-apbdma";
 165                 reg = <0x6000a000 0x1400>;
 166                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 199                 resets = <&tegra_car 34>;
 200                 reset-names = "dma";
 201                 #dma-cells = <1>;
 202         };
 203
 204         ahb: ahb@6000c004 {
 205                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 206                 reg = <0x6000c004 0x14c>;
 207         };
 208
 209         gpio: gpio@6000d000 {
 210                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 211                 reg = <0x6000d000 0x1000>;
 212                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 220                 #gpio-cells = <2>;
 221                 gpio-controller;
 222                 #interrupt-cells = <2>;
 223                 interrupt-controller;
 224         };
 225
 226         apbmisc@70000800 {
 227                 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
 228                 reg = <0x70000800 0x64   /* Chip revision */
 229                        0x70000008 0x04>; /* Strapping options */
 230         };
 231
 232         pinmux: pinmux@70000868 {
 233                 compatible = "nvidia,tegra114-pinmux";
 234                 reg = <0x70000868 0x148         /* Pad control registers */
 235                        0x70003000 0x40c>;       /* Mux registers */
 236         };
 237
 238         /*
 239          * There are two serial driver i.e. 8250 based simple serial
 240          * driver and APB DMA based serial driver for higher baudrate
 241          * and performace. To enable the 8250 based driver, the compatible
 242          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 243          * the APB DMA based serial driver, the comptible is
 244          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 245          */
 246         uarta: serial@70006000 {
 247                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 248                 reg = <0x70006000 0x40>;
 249                 reg-shift = <2>;
 250                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 252                 resets = <&tegra_car 6>;
 253                 reset-names = "serial";
 254                 dmas = <&apbdma 8>, <&apbdma 8>;
 255                 dma-names = "rx", "tx";
 256                 status = "disabled";
 257         };
 258
 259         uartb: serial@70006040 {
 260                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 261                 reg = <0x70006040 0x40>;
 262                 reg-shift = <2>;
 263                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 265                 resets = <&tegra_car 7>;
 266                 reset-names = "serial";
 267                 dmas = <&apbdma 9>, <&apbdma 9>;
 268                 dma-names = "rx", "tx";
 269                 status = "disabled";
 270         };
 271
 272         uartc: serial@70006200 {
 273                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 274                 reg = <0x70006200 0x100>;
 275                 reg-shift = <2>;
 276                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 277                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 278                 resets = <&tegra_car 55>;
 279                 reset-names = "serial";
 280                 dmas = <&apbdma 10>, <&apbdma 10>;
 281                 dma-names = "rx", "tx";
 282                 status = "disabled";
 283         };
 284
 285         uartd: serial@70006300 {
 286                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 287                 reg = <0x70006300 0x100>;
 288                 reg-shift = <2>;
 289                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 290                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 291                 resets = <&tegra_car 65>;
 292                 reset-names = "serial";
 293                 dmas = <&apbdma 19>, <&apbdma 19>;
 294                 dma-names = "rx", "tx";
 295                 status = "disabled";
 296         };
 297
 298         pwm: pwm@7000a000 {
 299                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 300                 reg = <0x7000a000 0x100>;
 301                 #pwm-cells = <2>;
 302                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 303                 resets = <&tegra_car 17>;
 304                 reset-names = "pwm";
 305                 status = "disabled";
 306         };
 307
 308         i2c@7000c000 {
 309                 compatible = "nvidia,tegra114-i2c";
 310                 reg = <0x7000c000 0x100>;
 311                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 315                 clock-names = "div-clk";
 316                 resets = <&tegra_car 12>;
 317                 reset-names = "i2c";
 318                 dmas = <&apbdma 21>, <&apbdma 21>;
 319                 dma-names = "rx", "tx";
 320                 status = "disabled";
 321         };
 322
 323         i2c@7000c400 {
 324                 compatible = "nvidia,tegra114-i2c";
 325                 reg = <0x7000c400 0x100>;
 326                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 330                 clock-names = "div-clk";
 331                 resets = <&tegra_car 54>;
 332                 reset-names = "i2c";
 333                 dmas = <&apbdma 22>, <&apbdma 22>;
 334                 dma-names = "rx", "tx";
 335                 status = "disabled";
 336         };
 337
 338         i2c@7000c500 {
 339                 compatible = "nvidia,tegra114-i2c";
 340                 reg = <0x7000c500 0x100>;
 341                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 345                 clock-names = "div-clk";
 346                 resets = <&tegra_car 67>;
 347                 reset-names = "i2c";
 348                 dmas = <&apbdma 23>, <&apbdma 23>;
 349                 dma-names = "rx", "tx";
 350                 status = "disabled";
 351         };
 352
 353         i2c@7000c700 {
 354                 compatible = "nvidia,tegra114-i2c";
 355                 reg = <0x7000c700 0x100>;
 356                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 360                 clock-names = "div-clk";
 361                 resets = <&tegra_car 103>;
 362                 reset-names = "i2c";
 363                 dmas = <&apbdma 26>, <&apbdma 26>;
 364                 dma-names = "rx", "tx";
 365                 status = "disabled";
 366         };
 367
 368         i2c@7000d000 {
 369                 compatible = "nvidia,tegra114-i2c";
 370                 reg = <0x7000d000 0x100>;
 371                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 375                 clock-names = "div-clk";
 376                 resets = <&tegra_car 47>;
 377                 reset-names = "i2c";
 378                 dmas = <&apbdma 24>, <&apbdma 24>;
 379                 dma-names = "rx", "tx";
 380                 status = "disabled";
 381         };
 382
 383         spi@7000d400 {
 384                 compatible = "nvidia,tegra114-spi";
 385                 reg = <0x7000d400 0x200>;
 386                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 390                 clock-names = "spi";
 391                 resets = <&tegra_car 41>;
 392                 reset-names = "spi";
 393                 dmas = <&apbdma 15>, <&apbdma 15>;
 394                 dma-names = "rx", "tx";
 395                 status = "disabled";
 396         };
 397
 398         spi@7000d600 {
 399                 compatible = "nvidia,tegra114-spi";
 400                 reg = <0x7000d600 0x200>;
 401                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 405                 clock-names = "spi";
 406                 resets = <&tegra_car 44>;
 407                 reset-names = "spi";
 408                 dmas = <&apbdma 16>, <&apbdma 16>;
 409                 dma-names = "rx", "tx";
 410                 status = "disabled";
 411         };
 412
 413         spi@7000d800 {
 414                 compatible = "nvidia,tegra114-spi";
 415                 reg = <0x7000d800 0x200>;
 416                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 420                 clock-names = "spi";
 421                 resets = <&tegra_car 46>;
 422                 reset-names = "spi";
 423                 dmas = <&apbdma 17>, <&apbdma 17>;
 424                 dma-names = "rx", "tx";
 425                 status = "disabled";
 426         };
 427
 428         spi@7000da00 {
 429                 compatible = "nvidia,tegra114-spi";
 430                 reg = <0x7000da00 0x200>;
 431                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 435                 clock-names = "spi";
 436                 resets = <&tegra_car 68>;
 437                 reset-names = "spi";
 438                 dmas = <&apbdma 18>, <&apbdma 18>;
 439                 dma-names = "rx", "tx";
 440                 status = "disabled";
 441         };
 442
 443         spi@7000dc00 {
 444                 compatible = "nvidia,tegra114-spi";
 445                 reg = <0x7000dc00 0x200>;
 446                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 450                 clock-names = "spi";
 451                 resets = <&tegra_car 104>;
 452                 reset-names = "spi";
 453                 dmas = <&apbdma 27>, <&apbdma 27>;
 454                 dma-names = "rx", "tx";
 455                 status = "disabled";
 456         };
 457
 458         spi@7000de00 {
 459                 compatible = "nvidia,tegra114-spi";
 460                 reg = <0x7000de00 0x200>;
 461                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 465                 clock-names = "spi";
 466                 resets = <&tegra_car 105>;
 467                 reset-names = "spi";
 468                 dmas = <&apbdma 28>, <&apbdma 28>;
 469                 dma-names = "rx", "tx";
 470                 status = "disabled";
 471         };
 472
 473         rtc@7000e000 {
 474                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 475                 reg = <0x7000e000 0x100>;
 476                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 477                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 478         };
 479
 480         kbc@7000e200 {
 481                 compatible = "nvidia,tegra114-kbc";
 482                 reg = <0x7000e200 0x100>;
 483                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 484                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 485                 resets = <&tegra_car 36>;
 486                 reset-names = "kbc";
 487                 status = "disabled";
 488         };
 489
 490         pmc@7000e400 {
 491                 compatible = "nvidia,tegra114-pmc";
 492                 reg = <0x7000e400 0x400>;
 493                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 494                 clock-names = "pclk", "clk32k_in";
 495         };
 496
 497         fuse@7000f800 {
 498                 compatible = "nvidia,tegra114-efuse";
 499                 reg = <0x7000f800 0x400>;
 500                 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
 501                 clock-names = "fuse";
 502                 resets = <&tegra_car 39>;
 503                 reset-names = "fuse";
 504         };
 505
 506         mc: memory-controller@70019000 {
 507                 compatible = "nvidia,tegra114-mc";
 508                 reg = <0x70019000 0x1000>;
 509                 clocks = <&tegra_car TEGRA114_CLK_MC>;
 510                 clock-names = "mc";
 511
 512                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 513
 514                 #iommu-cells = <1>;
 515         };
 516
 517         ahub@70080000 {
 518                 compatible = "nvidia,tegra114-ahub";
 519                 reg = <0x70080000 0x200>,
 520                       <0x70080200 0x100>,
 521                       <0x70081000 0x200>;
 522                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 523                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 524                          <&tegra_car TEGRA114_CLK_APBIF>;
 525                 clock-names = "d_audio", "apbif";
 526                 resets = <&tegra_car 106>, /* d_audio */
 527                          <&tegra_car 107>, /* apbif */
 528                          <&tegra_car 30>,  /* i2s0 */
 529                          <&tegra_car 11>,  /* i2s1 */
 530                          <&tegra_car 18>,  /* i2s2 */
 531                          <&tegra_car 101>, /* i2s3 */
 532                          <&tegra_car 102>, /* i2s4 */
 533                          <&tegra_car 108>, /* dam0 */
 534                          <&tegra_car 109>, /* dam1 */
 535                          <&tegra_car 110>, /* dam2 */
 536                          <&tegra_car 10>,  /* spdif */
 537                          <&tegra_car 153>, /* amx */
 538                          <&tegra_car 154>; /* adx */
 539                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 540                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 541                               "spdif", "amx", "adx";
 542                 dmas = <&apbdma 1>, <&apbdma 1>,
 543                        <&apbdma 2>, <&apbdma 2>,
 544                        <&apbdma 3>, <&apbdma 3>,
 545                        <&apbdma 4>, <&apbdma 4>,
 546                        <&apbdma 6>, <&apbdma 6>,
 547                        <&apbdma 7>, <&apbdma 7>,
 548                        <&apbdma 12>, <&apbdma 12>,
 549                        <&apbdma 13>, <&apbdma 13>,
 550                        <&apbdma 14>, <&apbdma 14>,
 551                        <&apbdma 29>, <&apbdma 29>;
 552                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 553                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 554                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 555                             "rx9", "tx9";
 556                 ranges;
 557                 #address-cells = <1>;
 558                 #size-cells = <1>;
 559
 560                 tegra_i2s0: i2s@70080300 {
 561                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 562                         reg = <0x70080300 0x100>;
 563                         nvidia,ahub-cif-ids = <4 4>;
 564                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 565                         resets = <&tegra_car 30>;
 566                         reset-names = "i2s";
 567                         status = "disabled";
 568                 };
 569
 570                 tegra_i2s1: i2s@70080400 {
 571                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 572                         reg = <0x70080400 0x100>;
 573                         nvidia,ahub-cif-ids = <5 5>;
 574                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 575                         resets = <&tegra_car 11>;
 576                         reset-names = "i2s";
 577                         status = "disabled";
 578                 };
 579
 580                 tegra_i2s2: i2s@70080500 {
 581                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 582                         reg = <0x70080500 0x100>;
 583                         nvidia,ahub-cif-ids = <6 6>;
 584                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 585                         resets = <&tegra_car 18>;
 586                         reset-names = "i2s";
 587                         status = "disabled";
 588                 };
 589
 590                 tegra_i2s3: i2s@70080600 {
 591                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 592                         reg = <0x70080600 0x100>;
 593                         nvidia,ahub-cif-ids = <7 7>;
 594                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 595                         resets = <&tegra_car 101>;
 596                         reset-names = "i2s";
 597                         status = "disabled";
 598                 };
 599
 600                 tegra_i2s4: i2s@70080700 {
 601                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 602                         reg = <0x70080700 0x100>;
 603                         nvidia,ahub-cif-ids = <8 8>;
 604                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 605                         resets = <&tegra_car 102>;
 606                         reset-names = "i2s";
 607                         status = "disabled";
 608                 };
 609         };
 610
 611         mipi: mipi@700e3000 {
 612                 compatible = "nvidia,tegra114-mipi";
 613                 reg = <0x700e3000 0x100>;
 614                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 615                 #nvidia,mipi-calibrate-cells = <1>;
 616         };
 617
 618         sdhci@78000000 {
 619                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 620                 reg = <0x78000000 0x200>;
 621                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 623                 resets = <&tegra_car 14>;
 624                 reset-names = "sdhci";
 625                 status = "disabled";
 626         };
 627
 628         sdhci@78000200 {
 629                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 630                 reg = <0x78000200 0x200>;
 631                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 633                 resets = <&tegra_car 9>;
 634                 reset-names = "sdhci";
 635                 status = "disabled";
 636         };
 637
 638         sdhci@78000400 {
 639                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 640                 reg = <0x78000400 0x200>;
 641                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 643                 resets = <&tegra_car 69>;
 644                 reset-names = "sdhci";
 645                 status = "disabled";
 646         };
 647
 648         sdhci@78000600 {
 649                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 650                 reg = <0x78000600 0x200>;
 651                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 653                 resets = <&tegra_car 15>;
 654                 reset-names = "sdhci";
 655                 status = "disabled";
 656         };
 657
 658         usb@7d000000 {
 659                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 660                 reg = <0x7d000000 0x4000>;
 661                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 662                 phy_type = "utmi";
 663                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 664                 resets = <&tegra_car 22>;
 665                 reset-names = "usb";
 666                 nvidia,phy = <&phy1>;
 667                 status = "disabled";
 668         };
 669
 670         phy1: usb-phy@7d000000 {
 671                 compatible = "nvidia,tegra30-usb-phy";
 672                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 673                 phy_type = "utmi";
 674                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 675                          <&tegra_car TEGRA114_CLK_PLL_U>,
 676                          <&tegra_car TEGRA114_CLK_USBD>;
 677                 clock-names = "reg", "pll_u", "utmi-pads";
 678                 resets = <&tegra_car 22>, <&tegra_car 22>;
 679                 reset-names = "usb", "utmi-pads";
 680                 nvidia,hssync-start-delay = <0>;
 681                 nvidia,idle-wait-delay = <17>;
 682                 nvidia,elastic-limit = <16>;
 683                 nvidia,term-range-adj = <6>;
 684                 nvidia,xcvr-setup = <9>;
 685                 nvidia,xcvr-lsfslew = <0>;
 686                 nvidia,xcvr-lsrslew = <3>;
 687                 nvidia,hssquelch-level = <2>;
 688                 nvidia,hsdiscon-level = <5>;
 689                 nvidia,xcvr-hsslew = <12>;
 690                 nvidia,has-utmi-pad-registers;
 691                 status = "disabled";
 692         };
 693
 694         usb@7d008000 {
 695                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 696                 reg = <0x7d008000 0x4000>;
 697                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 698                 phy_type = "utmi";
 699                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 700                 resets = <&tegra_car 59>;
 701                 reset-names = "usb";
 702                 nvidia,phy = <&phy3>;
 703                 status = "disabled";
 704         };
 705
 706         phy3: usb-phy@7d008000 {
 707                 compatible = "nvidia,tegra30-usb-phy";
 708                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 709                 phy_type = "utmi";
 710                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 711                          <&tegra_car TEGRA114_CLK_PLL_U>,
 712                          <&tegra_car TEGRA114_CLK_USBD>;
 713                 clock-names = "reg", "pll_u", "utmi-pads";
 714                 resets = <&tegra_car 59>, <&tegra_car 22>;
 715                 reset-names = "usb", "utmi-pads";
 716                 nvidia,hssync-start-delay = <0>;
 717                 nvidia,idle-wait-delay = <17>;
 718                 nvidia,elastic-limit = <16>;
 719                 nvidia,term-range-adj = <6>;
 720                 nvidia,xcvr-setup = <9>;
 721                 nvidia,xcvr-lsfslew = <0>;
 722                 nvidia,xcvr-lsrslew = <3>;
 723                 nvidia,hssquelch-level = <2>;
 724                 nvidia,hsdiscon-level = <5>;
 725                 nvidia,xcvr-hsslew = <12>;
 726                 status = "disabled";
 727         };
 728
 729         cpus {
 730                 #address-cells = <1>;
 731                 #size-cells = <0>;
 732
 733                 cpu@0 {
 734                         device_type = "cpu";
 735                         compatible = "arm,cortex-a15";
 736                         reg = <0>;
 737                 };
 738
 739                 cpu@1 {
 740                         device_type = "cpu";
 741                         compatible = "arm,cortex-a15";
 742                         reg = <1>;
 743                 };
 744
 745                 cpu@2 {
 746                         device_type = "cpu";
 747                         compatible = "arm,cortex-a15";
 748                         reg = <2>;
 749                 };
 750
 751                 cpu@3 {
 752                         device_type = "cpu";
 753                         compatible = "arm,cortex-a15";
 754                         reg = <3>;
 755                 };
 756         };
 757
 758         timer {
 759                 compatible = "arm,armv7-timer";
 760                 interrupts =
 761                         <GIC_PPI 13
 762                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 763                         <GIC_PPI 14
 764                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 765                         <GIC_PPI 11
 766                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 767                         <GIC_PPI 10
 768                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 769         };
 770 };