arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "nvidia,tegra124";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         pcie-controller@0,01003000 {
  17                 compatible = "nvidia,tegra124-pcie";
  18                 device_type = "pci";
  19                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  20                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  21                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  22                 reg-names = "pads", "afi", "cs";
  23                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  24                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  25                 interrupt-names = "intr", "msi";
  26
  27                 #interrupt-cells = <1>;
  28                 interrupt-map-mask = <0 0 0 0>;
  29                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  30
  31                 bus-range = <0x00 0xff>;
  32                 #address-cells = <3>;
  33                 #size-cells = <2>;
  34
  35                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  36                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  37                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  38                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  39                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  40
  41                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  42                          <&tegra_car TEGRA124_CLK_AFI>,
  43                          <&tegra_car TEGRA124_CLK_PLL_E>,
  44                          <&tegra_car TEGRA124_CLK_CML0>;
  45                 clock-names = "pex", "afi", "pll_e", "cml";
  46                 resets = <&tegra_car 70>,
  47                          <&tegra_car 72>,
  48                          <&tegra_car 74>;
  49                 reset-names = "pex", "afi", "pcie_x";
  50                 status = "disabled";
  51
  52                 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  53                 phy-names = "pcie";
  54
  55                 pci@1,0 {
  56                         device_type = "pci";
  57                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  58                         reg = <0x000800 0 0 0 0>;
  59                         status = "disabled";
  60
  61                         #address-cells = <3>;
  62                         #size-cells = <2>;
  63                         ranges;
  64
  65                         nvidia,num-lanes = <2>;
  66                 };
  67
  68                 pci@2,0 {
  69                         device_type = "pci";
  70                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  71                         reg = <0x001000 0 0 0 0>;
  72                         status = "disabled";
  73
  74                         #address-cells = <3>;
  75                         #size-cells = <2>;
  76                         ranges;
  77
  78                         nvidia,num-lanes = <1>;
  79                 };
  80         };
  81
  82         host1x@0,50000000 {
  83                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  84                 reg = <0x0 0x50000000 0x0 0x00034000>;
  85                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  86                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  87                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  88                 resets = <&tegra_car 28>;
  89                 reset-names = "host1x";
  90
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93
  94                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  95
  96                 dc@0,54200000 {
  97                         compatible = "nvidia,tegra124-dc";
  98                         reg = <0x0 0x54200000 0x0 0x00040000>;
  99                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 100                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 101                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 102                         clock-names = "dc", "parent";
 103                         resets = <&tegra_car 27>;
 104                         reset-names = "dc";
 105
 106                         iommus = <&mc TEGRA_SWGROUP_DC>;
 107
 108                         nvidia,head = <0>;
 109                 };
 110
 111                 dc@0,54240000 {
 112                         compatible = "nvidia,tegra124-dc";
 113                         reg = <0x0 0x54240000 0x0 0x00040000>;
 114                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 115                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 116                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 117                         clock-names = "dc", "parent";
 118                         resets = <&tegra_car 26>;
 119                         reset-names = "dc";
 120
 121                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 122
 123                         nvidia,head = <1>;
 124                 };
 125
 126                 hdmi@0,54280000 {
 127                         compatible = "nvidia,tegra124-hdmi";
 128                         reg = <0x0 0x54280000 0x0 0x00040000>;
 129                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 130                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 131                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 132                         clock-names = "hdmi", "parent";
 133                         resets = <&tegra_car 51>;
 134                         reset-names = "hdmi";
 135                         status = "disabled";
 136                 };
 137
 138                 sor@0,54540000 {
 139                         compatible = "nvidia,tegra124-sor";
 140                         reg = <0x0 0x54540000 0x0 0x00040000>;
 141                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 142                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 143                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 144                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 145                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 146                         clock-names = "sor", "parent", "dp", "safe";
 147                         resets = <&tegra_car 182>;
 148                         reset-names = "sor";
 149                         status = "disabled";
 150                 };
 151
 152                 dpaux: dpaux@0,545c0000 {
 153                         compatible = "nvidia,tegra124-dpaux";
 154                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 155                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 156                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 157                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 158                         clock-names = "dpaux", "parent";
 159                         resets = <&tegra_car 181>;
 160                         reset-names = "dpaux";
 161                         status = "disabled";
 162                 };
 163         };
 164
 165         gic: interrupt-controller@0,50041000 {
 166                 compatible = "arm,cortex-a15-gic";
 167                 #interrupt-cells = <3>;
 168                 interrupt-controller;
 169                 reg = <0x0 0x50041000 0x0 0x1000>,
 170                       <0x0 0x50042000 0x0 0x1000>,
 171                       <0x0 0x50044000 0x0 0x2000>,
 172                       <0x0 0x50046000 0x0 0x2000>;
 173                 interrupts = <GIC_PPI 9
 174                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 175         };
 176
 177         gpu@0,57000000 {
 178                 compatible = "nvidia,gk20a";
 179                 reg = <0x0 0x57000000 0x0 0x01000000>,
 180                       <0x0 0x58000000 0x0 0x01000000>;
 181                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 183                 interrupt-names = "stall", "nonstall";
 184                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 185                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 186                 clock-names = "gpu", "pwr";
 187                 resets = <&tegra_car 184>;
 188                 reset-names = "gpu";
 189                 status = "disabled";
 190         };
 191
 192         timer@0,60005000 {
 193                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 194                 reg = <0x0 0x60005000 0x0 0x400>;
 195                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 202         };
 203
 204         tegra_car: clock@0,60006000 {
 205                 compatible = "nvidia,tegra124-car";
 206                 reg = <0x0 0x60006000 0x0 0x1000>;
 207                 #clock-cells = <1>;
 208                 #reset-cells = <1>;
 209         };
 210
 211         flow-controller@0,60007000 {
 212                 compatible = "nvidia,tegra124-flowctrl";
 213                 reg = <0x0 0x60007000 0x0 0x1000>;
 214         };
 215
 216         gpio: gpio@0,6000d000 {
 217                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 218                 reg = <0x0 0x6000d000 0x0 0x1000>;
 219                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 227                 #gpio-cells = <2>;
 228                 gpio-controller;
 229                 #interrupt-cells = <2>;
 230                 interrupt-controller;
 231         };
 232
 233         apbdma: dma@0,60020000 {
 234                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 235                 reg = <0x0 0x60020000 0x0 0x1400>;
 236                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 269                 resets = <&tegra_car 34>;
 270                 reset-names = "dma";
 271                 #dma-cells = <1>;
 272         };
 273
 274         apbmisc@0,70000800 {
 275                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 276                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 277                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 278         };
 279
 280         pinmux: pinmux@0,70000868 {
 281                 compatible = "nvidia,tegra124-pinmux";
 282                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 283                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 284                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 285         };
 286
 287         /*
 288          * There are two serial driver i.e. 8250 based simple serial
 289          * driver and APB DMA based serial driver for higher baudrate
 290          * and performace. To enable the 8250 based driver, the compatible
 291          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 292          * the APB DMA based serial driver, the comptible is
 293          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 294          */
 295         uarta: serial@0,70006000 {
 296                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 297                 reg = <0x0 0x70006000 0x0 0x40>;
 298                 reg-shift = <2>;
 299                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 301                 resets = <&tegra_car 6>;
 302                 reset-names = "serial";
 303                 dmas = <&apbdma 8>, <&apbdma 8>;
 304                 dma-names = "rx", "tx";
 305                 status = "disabled";
 306         };
 307
 308         uartb: serial@0,70006040 {
 309                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 310                 reg = <0x0 0x70006040 0x0 0x40>;
 311                 reg-shift = <2>;
 312                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 314                 resets = <&tegra_car 7>;
 315                 reset-names = "serial";
 316                 dmas = <&apbdma 9>, <&apbdma 9>;
 317                 dma-names = "rx", "tx";
 318                 status = "disabled";
 319         };
 320
 321         uartc: serial@0,70006200 {
 322                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 323                 reg = <0x0 0x70006200 0x0 0x40>;
 324                 reg-shift = <2>;
 325                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 327                 resets = <&tegra_car 55>;
 328                 reset-names = "serial";
 329                 dmas = <&apbdma 10>, <&apbdma 10>;
 330                 dma-names = "rx", "tx";
 331                 status = "disabled";
 332         };
 333
 334         uartd: serial@0,70006300 {
 335                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 336                 reg = <0x0 0x70006300 0x0 0x40>;
 337                 reg-shift = <2>;
 338                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 340                 resets = <&tegra_car 65>;
 341                 reset-names = "serial";
 342                 dmas = <&apbdma 19>, <&apbdma 19>;
 343                 dma-names = "rx", "tx";
 344                 status = "disabled";
 345         };
 346
 347         pwm: pwm@0,7000a000 {
 348                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 349                 reg = <0x0 0x7000a000 0x0 0x100>;
 350                 #pwm-cells = <2>;
 351                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 352                 resets = <&tegra_car 17>;
 353                 reset-names = "pwm";
 354                 status = "disabled";
 355         };
 356
 357         i2c@0,7000c000 {
 358                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 359                 reg = <0x0 0x7000c000 0x0 0x100>;
 360                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 364                 clock-names = "div-clk";
 365                 resets = <&tegra_car 12>;
 366                 reset-names = "i2c";
 367                 dmas = <&apbdma 21>, <&apbdma 21>;
 368                 dma-names = "rx", "tx";
 369                 status = "disabled";
 370         };
 371
 372         i2c@0,7000c400 {
 373                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 374                 reg = <0x0 0x7000c400 0x0 0x100>;
 375                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 379                 clock-names = "div-clk";
 380                 resets = <&tegra_car 54>;
 381                 reset-names = "i2c";
 382                 dmas = <&apbdma 22>, <&apbdma 22>;
 383                 dma-names = "rx", "tx";
 384                 status = "disabled";
 385         };
 386
 387         i2c@0,7000c500 {
 388                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 389                 reg = <0x0 0x7000c500 0x0 0x100>;
 390                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 394                 clock-names = "div-clk";
 395                 resets = <&tegra_car 67>;
 396                 reset-names = "i2c";
 397                 dmas = <&apbdma 23>, <&apbdma 23>;
 398                 dma-names = "rx", "tx";
 399                 status = "disabled";
 400         };
 401
 402         i2c@0,7000c700 {
 403                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 404                 reg = <0x0 0x7000c700 0x0 0x100>;
 405                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 409                 clock-names = "div-clk";
 410                 resets = <&tegra_car 103>;
 411                 reset-names = "i2c";
 412                 dmas = <&apbdma 26>, <&apbdma 26>;
 413                 dma-names = "rx", "tx";
 414                 status = "disabled";
 415         };
 416
 417         i2c@0,7000d000 {
 418                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 419                 reg = <0x0 0x7000d000 0x0 0x100>;
 420                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 424                 clock-names = "div-clk";
 425                 resets = <&tegra_car 47>;
 426                 reset-names = "i2c";
 427                 dmas = <&apbdma 24>, <&apbdma 24>;
 428                 dma-names = "rx", "tx";
 429                 status = "disabled";
 430         };
 431
 432         i2c@0,7000d100 {
 433                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 434                 reg = <0x0 0x7000d100 0x0 0x100>;
 435                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 439                 clock-names = "div-clk";
 440                 resets = <&tegra_car 166>;
 441                 reset-names = "i2c";
 442                 dmas = <&apbdma 30>, <&apbdma 30>;
 443                 dma-names = "rx", "tx";
 444                 status = "disabled";
 445         };
 446
 447         spi@0,7000d400 {
 448                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 449                 reg = <0x0 0x7000d400 0x0 0x200>;
 450                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 454                 clock-names = "spi";
 455                 resets = <&tegra_car 41>;
 456                 reset-names = "spi";
 457                 dmas = <&apbdma 15>, <&apbdma 15>;
 458                 dma-names = "rx", "tx";
 459                 status = "disabled";
 460         };
 461
 462         spi@0,7000d600 {
 463                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 464                 reg = <0x0 0x7000d600 0x0 0x200>;
 465                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 469                 clock-names = "spi";
 470                 resets = <&tegra_car 44>;
 471                 reset-names = "spi";
 472                 dmas = <&apbdma 16>, <&apbdma 16>;
 473                 dma-names = "rx", "tx";
 474                 status = "disabled";
 475         };
 476
 477         spi@0,7000d800 {
 478                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 479                 reg = <0x0 0x7000d800 0x0 0x200>;
 480                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 484                 clock-names = "spi";
 485                 resets = <&tegra_car 46>;
 486                 reset-names = "spi";
 487                 dmas = <&apbdma 17>, <&apbdma 17>;
 488                 dma-names = "rx", "tx";
 489                 status = "disabled";
 490         };
 491
 492         spi@0,7000da00 {
 493                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 494                 reg = <0x0 0x7000da00 0x0 0x200>;
 495                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 499                 clock-names = "spi";
 500                 resets = <&tegra_car 68>;
 501                 reset-names = "spi";
 502                 dmas = <&apbdma 18>, <&apbdma 18>;
 503                 dma-names = "rx", "tx";
 504                 status = "disabled";
 505         };
 506
 507         spi@0,7000dc00 {
 508                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 509                 reg = <0x0 0x7000dc00 0x0 0x200>;
 510                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 514                 clock-names = "spi";
 515                 resets = <&tegra_car 104>;
 516                 reset-names = "spi";
 517                 dmas = <&apbdma 27>, <&apbdma 27>;
 518                 dma-names = "rx", "tx";
 519                 status = "disabled";
 520         };
 521
 522         spi@0,7000de00 {
 523                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 524                 reg = <0x0 0x7000de00 0x0 0x200>;
 525                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 529                 clock-names = "spi";
 530                 resets = <&tegra_car 105>;
 531                 reset-names = "spi";
 532                 dmas = <&apbdma 28>, <&apbdma 28>;
 533                 dma-names = "rx", "tx";
 534                 status = "disabled";
 535         };
 536
 537         rtc@0,7000e000 {
 538                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 539                 reg = <0x0 0x7000e000 0x0 0x100>;
 540                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 542         };
 543
 544         pmc@0,7000e400 {
 545                 compatible = "nvidia,tegra124-pmc";
 546                 reg = <0x0 0x7000e400 0x0 0x400>;
 547                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 548                 clock-names = "pclk", "clk32k_in";
 549         };
 550
 551         fuse@0,7000f800 {
 552                 compatible = "nvidia,tegra124-efuse";
 553                 reg = <0x0 0x7000f800 0x0 0x400>;
 554                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 555                 clock-names = "fuse";
 556                 resets = <&tegra_car 39>;
 557                 reset-names = "fuse";
 558         };
 559
 560         mc: memory-controller@0,70019000 {
 561                 compatible = "nvidia,tegra124-mc";
 562                 reg = <0x0 0x70019000 0x0 0x1000>;
 563                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 564                 clock-names = "mc";
 565
 566                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 567
 568                 #iommu-cells = <1>;
 569         };
 570
 571         sata@0,70020000 {
 572                 compatible = "nvidia,tegra124-ahci";
 573
 574                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 575                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 576
 577                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 578
 579                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 580                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 581                         <&tegra_car TEGRA124_CLK_CML1>,
 582                         <&tegra_car TEGRA124_CLK_PLL_E>;
 583                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 584
 585                 resets = <&tegra_car 124>,
 586                         <&tegra_car 123>,
 587                         <&tegra_car 129>;
 588                 reset-names = "sata", "sata-oob", "sata-cold";
 589
 590                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 591                 phy-names = "sata-phy";
 592
 593                 status = "disabled";
 594         };
 595
 596         hda@0,70030000 {
 597                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 598                 reg = <0x0 0x70030000 0x0 0x10000>;
 599                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 601                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 602                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 603                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 604                 resets = <&tegra_car 125>, /* hda */
 605                          <&tegra_car 128>, /* hda2hdmi */
 606                          <&tegra_car 111>; /* hda2codec_2x */
 607                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 608                 status = "disabled";
 609         };
 610
 611         padctl: padctl@0,7009f000 {
 612                 compatible = "nvidia,tegra124-xusb-padctl";
 613                 reg = <0x0 0x7009f000 0x0 0x1000>;
 614                 resets = <&tegra_car 142>;
 615                 reset-names = "padctl";
 616
 617                 #phy-cells = <1>;
 618         };
 619
 620         sdhci@0,700b0000 {
 621                 compatible = "nvidia,tegra124-sdhci";
 622                 reg = <0x0 0x700b0000 0x0 0x200>;
 623                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 625                 resets = <&tegra_car 14>;
 626                 reset-names = "sdhci";
 627                 status = "disabled";
 628         };
 629
 630         sdhci@0,700b0200 {
 631                 compatible = "nvidia,tegra124-sdhci";
 632                 reg = <0x0 0x700b0200 0x0 0x200>;
 633                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 635                 resets = <&tegra_car 9>;
 636                 reset-names = "sdhci";
 637                 status = "disabled";
 638         };
 639
 640         sdhci@0,700b0400 {
 641                 compatible = "nvidia,tegra124-sdhci";
 642                 reg = <0x0 0x700b0400 0x0 0x200>;
 643                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 645                 resets = <&tegra_car 69>;
 646                 reset-names = "sdhci";
 647                 status = "disabled";
 648         };
 649
 650         sdhci@0,700b0600 {
 651                 compatible = "nvidia,tegra124-sdhci";
 652                 reg = <0x0 0x700b0600 0x0 0x200>;
 653                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 654                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 655                 resets = <&tegra_car 15>;
 656                 reset-names = "sdhci";
 657                 status = "disabled";
 658         };
 659
 660         ahub@0,70300000 {
 661                 compatible = "nvidia,tegra124-ahub";
 662                 reg = <0x0 0x70300000 0x0 0x200>,
 663                       <0x0 0x70300800 0x0 0x800>,
 664                       <0x0 0x70300200 0x0 0x600>;
 665                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 667                          <&tegra_car TEGRA124_CLK_APBIF>;
 668                 clock-names = "d_audio", "apbif";
 669                 resets = <&tegra_car 106>, /* d_audio */
 670                          <&tegra_car 107>, /* apbif */
 671                          <&tegra_car 30>,  /* i2s0 */
 672                          <&tegra_car 11>,  /* i2s1 */
 673                          <&tegra_car 18>,  /* i2s2 */
 674                          <&tegra_car 101>, /* i2s3 */
 675                          <&tegra_car 102>, /* i2s4 */
 676                          <&tegra_car 108>, /* dam0 */
 677                          <&tegra_car 109>, /* dam1 */
 678                          <&tegra_car 110>, /* dam2 */
 679                          <&tegra_car 10>,  /* spdif */
 680                          <&tegra_car 153>, /* amx */
 681                          <&tegra_car 185>, /* amx1 */
 682                          <&tegra_car 154>, /* adx */
 683                          <&tegra_car 180>, /* adx1 */
 684                          <&tegra_car 186>, /* afc0 */
 685                          <&tegra_car 187>, /* afc1 */
 686                          <&tegra_car 188>, /* afc2 */
 687                          <&tegra_car 189>, /* afc3 */
 688                          <&tegra_car 190>, /* afc4 */
 689                          <&tegra_car 191>; /* afc5 */
 690                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 691                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 692                               "spdif", "amx", "amx1", "adx", "adx1",
 693                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 694                 dmas = <&apbdma 1>, <&apbdma 1>,
 695                        <&apbdma 2>, <&apbdma 2>,
 696                        <&apbdma 3>, <&apbdma 3>,
 697                        <&apbdma 4>, <&apbdma 4>,
 698                        <&apbdma 6>, <&apbdma 6>,
 699                        <&apbdma 7>, <&apbdma 7>,
 700                        <&apbdma 12>, <&apbdma 12>,
 701                        <&apbdma 13>, <&apbdma 13>,
 702                        <&apbdma 14>, <&apbdma 14>,
 703                        <&apbdma 29>, <&apbdma 29>;
 704                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 705                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 706                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 707                             "rx9", "tx9";
 708                 ranges;
 709                 #address-cells = <2>;
 710                 #size-cells = <2>;
 711
 712                 tegra_i2s0: i2s@0,70301000 {
 713                         compatible = "nvidia,tegra124-i2s";
 714                         reg = <0x0 0x70301000 0x0 0x100>;
 715                         nvidia,ahub-cif-ids = <4 4>;
 716                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 717                         resets = <&tegra_car 30>;
 718                         reset-names = "i2s";
 719                         status = "disabled";
 720                 };
 721
 722                 tegra_i2s1: i2s@0,70301100 {
 723                         compatible = "nvidia,tegra124-i2s";
 724                         reg = <0x0 0x70301100 0x0 0x100>;
 725                         nvidia,ahub-cif-ids = <5 5>;
 726                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 727                         resets = <&tegra_car 11>;
 728                         reset-names = "i2s";
 729                         status = "disabled";
 730                 };
 731
 732                 tegra_i2s2: i2s@0,70301200 {
 733                         compatible = "nvidia,tegra124-i2s";
 734                         reg = <0x0 0x70301200 0x0 0x100>;
 735                         nvidia,ahub-cif-ids = <6 6>;
 736                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 737                         resets = <&tegra_car 18>;
 738                         reset-names = "i2s";
 739                         status = "disabled";
 740                 };
 741
 742                 tegra_i2s3: i2s@0,70301300 {
 743                         compatible = "nvidia,tegra124-i2s";
 744                         reg = <0x0 0x70301300 0x0 0x100>;
 745                         nvidia,ahub-cif-ids = <7 7>;
 746                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 747                         resets = <&tegra_car 101>;
 748                         reset-names = "i2s";
 749                         status = "disabled";
 750                 };
 751
 752                 tegra_i2s4: i2s@0,70301400 {
 753                         compatible = "nvidia,tegra124-i2s";
 754                         reg = <0x0 0x70301400 0x0 0x100>;
 755                         nvidia,ahub-cif-ids = <8 8>;
 756                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 757                         resets = <&tegra_car 102>;
 758                         reset-names = "i2s";
 759                         status = "disabled";
 760                 };
 761         };
 762
 763         usb@0,7d000000 {
 764                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 765                 reg = <0x0 0x7d000000 0x0 0x4000>;
 766                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 767                 phy_type = "utmi";
 768                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 769                 resets = <&tegra_car 22>;
 770                 reset-names = "usb";
 771                 nvidia,phy = <&phy1>;
 772                 status = "disabled";
 773         };
 774
 775         phy1: usb-phy@0,7d000000 {
 776                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 777                 reg = <0x0 0x7d000000 0x0 0x4000>,
 778                       <0x0 0x7d000000 0x0 0x4000>;
 779                 phy_type = "utmi";
 780                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 781                          <&tegra_car TEGRA124_CLK_PLL_U>,
 782                          <&tegra_car TEGRA124_CLK_USBD>;
 783                 clock-names = "reg", "pll_u", "utmi-pads";
 784                 resets = <&tegra_car 59>, <&tegra_car 22>;
 785                 reset-names = "usb", "utmi-pads";
 786                 nvidia,hssync-start-delay = <0>;
 787                 nvidia,idle-wait-delay = <17>;
 788                 nvidia,elastic-limit = <16>;
 789                 nvidia,term-range-adj = <6>;
 790                 nvidia,xcvr-setup = <9>;
 791                 nvidia,xcvr-lsfslew = <0>;
 792                 nvidia,xcvr-lsrslew = <3>;
 793                 nvidia,hssquelch-level = <2>;
 794                 nvidia,hsdiscon-level = <5>;
 795                 nvidia,xcvr-hsslew = <12>;
 796                 status = "disabled";
 797         };
 798
 799         usb@0,7d004000 {
 800                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 801                 reg = <0x0 0x7d004000 0x0 0x4000>;
 802                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 803                 phy_type = "utmi";
 804                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 805                 resets = <&tegra_car 58>;
 806                 reset-names = "usb";
 807                 nvidia,phy = <&phy2>;
 808                 status = "disabled";
 809         };
 810
 811         phy2: usb-phy@0,7d004000 {
 812                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 813                 reg = <0x0 0x7d004000 0x0 0x4000>,
 814                       <0x0 0x7d000000 0x0 0x4000>;
 815                 phy_type = "utmi";
 816                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 817                          <&tegra_car TEGRA124_CLK_PLL_U>,
 818                          <&tegra_car TEGRA124_CLK_USBD>;
 819                 clock-names = "reg", "pll_u", "utmi-pads";
 820                 resets = <&tegra_car 22>, <&tegra_car 22>;
 821                 reset-names = "usb", "utmi-pads";
 822                 nvidia,hssync-start-delay = <0>;
 823                 nvidia,idle-wait-delay = <17>;
 824                 nvidia,elastic-limit = <16>;
 825                 nvidia,term-range-adj = <6>;
 826                 nvidia,xcvr-setup = <9>;
 827                 nvidia,xcvr-lsfslew = <0>;
 828                 nvidia,xcvr-lsrslew = <3>;
 829                 nvidia,hssquelch-level = <2>;
 830                 nvidia,hsdiscon-level = <5>;
 831                 nvidia,xcvr-hsslew = <12>;
 832                 nvidia,has-utmi-pad-registers;
 833                 status = "disabled";
 834         };
 835
 836         usb@0,7d008000 {
 837                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 838                 reg = <0x0 0x7d008000 0x0 0x4000>;
 839                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 840                 phy_type = "utmi";
 841                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 842                 resets = <&tegra_car 59>;
 843                 reset-names = "usb";
 844                 nvidia,phy = <&phy3>;
 845                 status = "disabled";
 846         };
 847
 848         phy3: usb-phy@0,7d008000 {
 849                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 850                 reg = <0x0 0x7d008000 0x0 0x4000>,
 851                       <0x0 0x7d000000 0x0 0x4000>;
 852                 phy_type = "utmi";
 853                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 854                          <&tegra_car TEGRA124_CLK_PLL_U>,
 855                          <&tegra_car TEGRA124_CLK_USBD>;
 856                 clock-names = "reg", "pll_u", "utmi-pads";
 857                 resets = <&tegra_car 58>, <&tegra_car 22>;
 858                 reset-names = "usb", "utmi-pads";
 859                 nvidia,hssync-start-delay = <0>;
 860                 nvidia,idle-wait-delay = <17>;
 861                 nvidia,elastic-limit = <16>;
 862                 nvidia,term-range-adj = <6>;
 863                 nvidia,xcvr-setup = <9>;
 864                 nvidia,xcvr-lsfslew = <0>;
 865                 nvidia,xcvr-lsrslew = <3>;
 866                 nvidia,hssquelch-level = <2>;
 867                 nvidia,hsdiscon-level = <5>;
 868                 nvidia,xcvr-hsslew = <12>;
 869                 status = "disabled";
 870         };
 871
 872         cpus {
 873                 #address-cells = <1>;
 874                 #size-cells = <0>;
 875
 876                 cpu@0 {
 877                         device_type = "cpu";
 878                         compatible = "arm,cortex-a15";
 879                         reg = <0>;
 880                 };
 881
 882                 cpu@1 {
 883                         device_type = "cpu";
 884                         compatible = "arm,cortex-a15";
 885                         reg = <1>;
 886                 };
 887
 888                 cpu@2 {
 889                         device_type = "cpu";
 890                         compatible = "arm,cortex-a15";
 891                         reg = <2>;
 892                 };
 893
 894                 cpu@3 {
 895                         device_type = "cpu";
 896                         compatible = "arm,cortex-a15";
 897                         reg = <3>;
 898                 };
 899         };
 900
 901         timer {
 902                 compatible = "arm,armv7-timer";
 903                 interrupts = <GIC_PPI 13
 904                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 905                              <GIC_PPI 14
 906                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 907                              <GIC_PPI 11
 908                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 909                              <GIC_PPI 10
 910                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 911         };
 912 };