arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/clock/tegra20-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         compatible = "nvidia,tegra20";
   9         interrupt-parent = <&intc>;
  10
  11         aliases {
  12                 serial0 = &uarta;
  13                 serial1 = &uartb;
  14                 serial2 = &uartc;
  15                 serial3 = &uartd;
  16                 serial4 = &uarte;
  17         };
  18
  19         host1x {
  20                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  21                 reg = <0x50000000 0x00024000>;
  22                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  23                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  24                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  25
  26                 #address-cells = <1>;
  27                 #size-cells = <1>;
  28
  29                 ranges = <0x54000000 0x54000000 0x04000000>;
  30
  31                 mpe {
  32                         compatible = "nvidia,tegra20-mpe";
  33                         reg = <0x54040000 0x00040000>;
  34                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  35                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  36                 };
  37
  38                 vi {
  39                         compatible = "nvidia,tegra20-vi";
  40                         reg = <0x54080000 0x00040000>;
  41                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  42                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  43                 };
  44
  45                 epp {
  46                         compatible = "nvidia,tegra20-epp";
  47                         reg = <0x540c0000 0x00040000>;
  48                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  49                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  50                 };
  51
  52                 isp {
  53                         compatible = "nvidia,tegra20-isp";
  54                         reg = <0x54100000 0x00040000>;
  55                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  56                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  57                 };
  58
  59                 gr2d {
  60                         compatible = "nvidia,tegra20-gr2d";
  61                         reg = <0x54140000 0x00040000>;
  62                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  63                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  64                 };
  65
  66                 gr3d {
  67                         compatible = "nvidia,tegra20-gr3d";
  68                         reg = <0x54180000 0x00040000>;
  69                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  70                 };
  71
  72                 dc@54200000 {
  73                         compatible = "nvidia,tegra20-dc";
  74                         reg = <0x54200000 0x00040000>;
  75                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  76                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  77                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  78                         clock-names = "disp1", "parent";
  79
  80                         rgb {
  81                                 status = "disabled";
  82                         };
  83                 };
  84
  85                 dc@54240000 {
  86                         compatible = "nvidia,tegra20-dc";
  87                         reg = <0x54240000 0x00040000>;
  88                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  89                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
  90                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  91                         clock-names = "disp2", "parent";
  92
  93                         rgb {
  94                                 status = "disabled";
  95                         };
  96                 };
  97
  98                 hdmi {
  99                         compatible = "nvidia,tegra20-hdmi";
 100                         reg = <0x54280000 0x00040000>;
 101                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 103                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 104                         clock-names = "hdmi", "parent";
 105                         status = "disabled";
 106                 };
 107
 108                 tvo {
 109                         compatible = "nvidia,tegra20-tvo";
 110                         reg = <0x542c0000 0x00040000>;
 111                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 113                         status = "disabled";
 114                 };
 115
 116                 dsi {
 117                         compatible = "nvidia,tegra20-dsi";
 118                         reg = <0x54300000 0x00040000>;
 119                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 120                         status = "disabled";
 121                 };
 122         };
 123
 124         timer@50004600 {
 125                 compatible = "arm,cortex-a9-twd-timer";
 126                 reg = <0x50040600 0x20>;
 127                 interrupts = <GIC_PPI 13
 128                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 129                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 130         };
 131
 132         intc: interrupt-controller {
 133                 compatible = "arm,cortex-a9-gic";
 134                 reg = <0x50041000 0x1000
 135                        0x50040100 0x0100>;
 136                 interrupt-controller;
 137                 #interrupt-cells = <3>;
 138         };
 139
 140         cache-controller {
 141                 compatible = "arm,pl310-cache";
 142                 reg = <0x50043000 0x1000>;
 143                 arm,data-latency = <5 5 2>;
 144                 arm,tag-latency = <4 4 2>;
 145                 cache-unified;
 146                 cache-level = <2>;
 147         };
 148
 149         timer@60005000 {
 150                 compatible = "nvidia,tegra20-timer";
 151                 reg = <0x60005000 0x60>;
 152                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 157         };
 158
 159         tegra_car: clock {
 160                 compatible = "nvidia,tegra20-car";
 161                 reg = <0x60006000 0x1000>;
 162                 #clock-cells = <1>;
 163         };
 164
 165         apbdma: dma {
 166                 compatible = "nvidia,tegra20-apbdma";
 167                 reg = <0x6000a000 0x1200>;
 168                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 185         };
 186
 187         ahb {
 188                 compatible = "nvidia,tegra20-ahb";
 189                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 190         };
 191
 192         gpio: gpio {
 193                 compatible = "nvidia,tegra20-gpio";
 194                 reg = <0x6000d000 0x1000>;
 195                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 202                 #gpio-cells = <2>;
 203                 gpio-controller;
 204                 #interrupt-cells = <2>;
 205                 interrupt-controller;
 206         };
 207
 208         pinmux: pinmux {
 209                 compatible = "nvidia,tegra20-pinmux";
 210                 reg = <0x70000014 0x10   /* Tri-state registers */
 211                        0x70000080 0x20   /* Mux registers */
 212                        0x700000a0 0x14   /* Pull-up/down registers */
 213                        0x70000868 0xa8>; /* Pad control registers */
 214         };
 215
 216         das {
 217                 compatible = "nvidia,tegra20-das";
 218                 reg = <0x70000c00 0x80>;
 219         };
 220
 221         tegra_ac97: ac97 {
 222                 compatible = "nvidia,tegra20-ac97";
 223                 reg = <0x70002000 0x200>;
 224                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 225                 nvidia,dma-request-selector = <&apbdma 12>;
 226                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 227                 status = "disabled";
 228         };
 229
 230         tegra_i2s1: i2s@70002800 {
 231                 compatible = "nvidia,tegra20-i2s";
 232                 reg = <0x70002800 0x200>;
 233                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 234                 nvidia,dma-request-selector = <&apbdma 2>;
 235                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 236                 status = "disabled";
 237         };
 238
 239         tegra_i2s2: i2s@70002a00 {
 240                 compatible = "nvidia,tegra20-i2s";
 241                 reg = <0x70002a00 0x200>;
 242                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 243                 nvidia,dma-request-selector = <&apbdma 1>;
 244                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 245                 status = "disabled";
 246         };
 247
 248         /*
 249          * There are two serial driver i.e. 8250 based simple serial
 250          * driver and APB DMA based serial driver for higher baudrate
 251          * and performace. To enable the 8250 based driver, the compatible
 252          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 253          * driver, the comptible is "nvidia,tegra20-hsuart".
 254          */
 255         uarta: serial@70006000 {
 256                 compatible = "nvidia,tegra20-uart";
 257                 reg = <0x70006000 0x40>;
 258                 reg-shift = <2>;
 259                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 260                 nvidia,dma-request-selector = <&apbdma 8>;
 261                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 262                 status = "disabled";
 263         };
 264
 265         uartb: serial@70006040 {
 266                 compatible = "nvidia,tegra20-uart";
 267                 reg = <0x70006040 0x40>;
 268                 reg-shift = <2>;
 269                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 270                 nvidia,dma-request-selector = <&apbdma 9>;
 271                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 272                 status = "disabled";
 273         };
 274
 275         uartc: serial@70006200 {
 276                 compatible = "nvidia,tegra20-uart";
 277                 reg = <0x70006200 0x100>;
 278                 reg-shift = <2>;
 279                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 280                 nvidia,dma-request-selector = <&apbdma 10>;
 281                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 282                 status = "disabled";
 283         };
 284
 285         uartd: serial@70006300 {
 286                 compatible = "nvidia,tegra20-uart";
 287                 reg = <0x70006300 0x100>;
 288                 reg-shift = <2>;
 289                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 290                 nvidia,dma-request-selector = <&apbdma 19>;
 291                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 292                 status = "disabled";
 293         };
 294
 295         uarte: serial@70006400 {
 296                 compatible = "nvidia,tegra20-uart";
 297                 reg = <0x70006400 0x100>;
 298                 reg-shift = <2>;
 299                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 300                 nvidia,dma-request-selector = <&apbdma 20>;
 301                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 302                 status = "disabled";
 303         };
 304
 305         pwm: pwm {
 306                 compatible = "nvidia,tegra20-pwm";
 307                 reg = <0x7000a000 0x100>;
 308                 #pwm-cells = <2>;
 309                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 310                 status = "disabled";
 311         };
 312
 313         rtc {
 314                 compatible = "nvidia,tegra20-rtc";
 315                 reg = <0x7000e000 0x100>;
 316                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 318         };
 319
 320         i2c@7000c000 {
 321                 compatible = "nvidia,tegra20-i2c";
 322                 reg = <0x7000c000 0x100>;
 323                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 327                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 328                 clock-names = "div-clk", "fast-clk";
 329                 status = "disabled";
 330         };
 331
 332         spi@7000c380 {
 333                 compatible = "nvidia,tegra20-sflash";
 334                 reg = <0x7000c380 0x80>;
 335                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 336                 nvidia,dma-request-selector = <&apbdma 11>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 340                 status = "disabled";
 341         };
 342
 343         i2c@7000c400 {
 344                 compatible = "nvidia,tegra20-i2c";
 345                 reg = <0x7000c400 0x100>;
 346                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 350                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 351                 clock-names = "div-clk", "fast-clk";
 352                 status = "disabled";
 353         };
 354
 355         i2c@7000c500 {
 356                 compatible = "nvidia,tegra20-i2c";
 357                 reg = <0x7000c500 0x100>;
 358                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 362                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 363                 clock-names = "div-clk", "fast-clk";
 364                 status = "disabled";
 365         };
 366
 367         i2c@7000d000 {
 368                 compatible = "nvidia,tegra20-i2c-dvc";
 369                 reg = <0x7000d000 0x200>;
 370                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 374                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 375                 clock-names = "div-clk", "fast-clk";
 376                 status = "disabled";
 377         };
 378
 379         spi@7000d400 {
 380                 compatible = "nvidia,tegra20-slink";
 381                 reg = <0x7000d400 0x200>;
 382                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 383                 nvidia,dma-request-selector = <&apbdma 15>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 387                 status = "disabled";
 388         };
 389
 390         spi@7000d600 {
 391                 compatible = "nvidia,tegra20-slink";
 392                 reg = <0x7000d600 0x200>;
 393                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 394                 nvidia,dma-request-selector = <&apbdma 16>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 398                 status = "disabled";
 399         };
 400
 401         spi@7000d800 {
 402                 compatible = "nvidia,tegra20-slink";
 403                 reg = <0x7000d800 0x200>;
 404                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 405                 nvidia,dma-request-selector = <&apbdma 17>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 409                 status = "disabled";
 410         };
 411
 412         spi@7000da00 {
 413                 compatible = "nvidia,tegra20-slink";
 414                 reg = <0x7000da00 0x200>;
 415                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 416                 nvidia,dma-request-selector = <&apbdma 18>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 420                 status = "disabled";
 421         };
 422
 423         kbc {
 424                 compatible = "nvidia,tegra20-kbc";
 425                 reg = <0x7000e200 0x100>;
 426                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 428                 status = "disabled";
 429         };
 430
 431         pmc {
 432                 compatible = "nvidia,tegra20-pmc";
 433                 reg = <0x7000e400 0x400>;
 434                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 435                 clock-names = "pclk", "clk32k_in";
 436         };
 437
 438         memory-controller@7000f000 {
 439                 compatible = "nvidia,tegra20-mc";
 440                 reg = <0x7000f000 0x024
 441                        0x7000f03c 0x3c4>;
 442                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 443         };
 444
 445         iommu {
 446                 compatible = "nvidia,tegra20-gart";
 447                 reg = <0x7000f024 0x00000018    /* controller registers */
 448                        0x58000000 0x02000000>;  /* GART aperture */
 449         };
 450
 451         memory-controller@7000f400 {
 452                 compatible = "nvidia,tegra20-emc";
 453                 reg = <0x7000f400 0x200>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456         };
 457
 458         pcie-controller {
 459                 compatible = "nvidia,tegra20-pcie";
 460                 device_type = "pci";
 461                 reg = <0x80003000 0x00000800   /* PADS registers */
 462                        0x80003800 0x00000200   /* AFI registers */
 463                        0x90000000 0x10000000>; /* configuration space */
 464                 reg-names = "pads", "afi", "cs";
 465                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 466                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 467                 interrupt-names = "intr", "msi";
 468
 469                 bus-range = <0x00 0xff>;
 470                 #address-cells = <3>;
 471                 #size-cells = <2>;
 472
 473                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 474                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 475                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 476                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 477                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 478
 479                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 480                          <&tegra_car TEGRA20_CLK_AFI>,
 481                          <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 482                          <&tegra_car TEGRA20_CLK_PLL_E>;
 483                 clock-names = "pex", "afi", "pcie_xclk", "pll_e";
 484                 status = "disabled";
 485
 486                 pci@1,0 {
 487                         device_type = "pci";
 488                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 489                         reg = <0x000800 0 0 0 0>;
 490                         status = "disabled";
 491
 492                         #address-cells = <3>;
 493                         #size-cells = <2>;
 494                         ranges;
 495
 496                         nvidia,num-lanes = <2>;
 497                 };
 498
 499                 pci@2,0 {
 500                         device_type = "pci";
 501                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 502                         reg = <0x001000 0 0 0 0>;
 503                         status = "disabled";
 504
 505                         #address-cells = <3>;
 506                         #size-cells = <2>;
 507                         ranges;
 508
 509                         nvidia,num-lanes = <2>;
 510                 };
 511         };
 512
 513         usb@c5000000 {
 514                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 515                 reg = <0xc5000000 0x4000>;
 516                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 517                 phy_type = "utmi";
 518                 nvidia,has-legacy-mode;
 519                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 520                 nvidia,needs-double-reset;
 521                 nvidia,phy = <&phy1>;
 522                 status = "disabled";
 523         };
 524
 525         phy1: usb-phy@c5000000 {
 526                 compatible = "nvidia,tegra20-usb-phy";
 527                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 528                 phy_type = "utmi";
 529                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 530                          <&tegra_car TEGRA20_CLK_PLL_U>,
 531                          <&tegra_car TEGRA20_CLK_CLK_M>,
 532                          <&tegra_car TEGRA20_CLK_USBD>;
 533                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 534                 nvidia,has-legacy-mode;
 535                 nvidia,hssync-start-delay = <9>;
 536                 nvidia,idle-wait-delay = <17>;
 537                 nvidia,elastic-limit = <16>;
 538                 nvidia,term-range-adj = <6>;
 539                 nvidia,xcvr-setup = <9>;
 540                 nvidia,xcvr-lsfslew = <1>;
 541                 nvidia,xcvr-lsrslew = <1>;
 542                 status = "disabled";
 543         };
 544
 545         usb@c5004000 {
 546                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 547                 reg = <0xc5004000 0x4000>;
 548                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 549                 phy_type = "ulpi";
 550                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 551                 nvidia,phy = <&phy2>;
 552                 status = "disabled";
 553         };
 554
 555         phy2: usb-phy@c5004000 {
 556                 compatible = "nvidia,tegra20-usb-phy";
 557                 reg = <0xc5004000 0x4000>;
 558                 phy_type = "ulpi";
 559                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 560                          <&tegra_car TEGRA20_CLK_PLL_U>,
 561                          <&tegra_car TEGRA20_CLK_CDEV2>;
 562                 clock-names = "reg", "pll_u", "ulpi-link";
 563                 status = "disabled";
 564         };
 565
 566         usb@c5008000 {
 567                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 568                 reg = <0xc5008000 0x4000>;
 569                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 570                 phy_type = "utmi";
 571                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 572                 nvidia,phy = <&phy3>;
 573                 status = "disabled";
 574         };
 575
 576         phy3: usb-phy@c5008000 {
 577                 compatible = "nvidia,tegra20-usb-phy";
 578                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 579                 phy_type = "utmi";
 580                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 581                          <&tegra_car TEGRA20_CLK_PLL_U>,
 582                          <&tegra_car TEGRA20_CLK_CLK_M>,
 583                          <&tegra_car TEGRA20_CLK_USBD>;
 584                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 585                 nvidia,hssync-start-delay = <9>;
 586                 nvidia,idle-wait-delay = <17>;
 587                 nvidia,elastic-limit = <16>;
 588                 nvidia,term-range-adj = <6>;
 589                 nvidia,xcvr-setup = <9>;
 590                 nvidia,xcvr-lsfslew = <2>;
 591                 nvidia,xcvr-lsrslew = <2>;
 592                 status = "disabled";
 593         };
 594
 595         sdhci@c8000000 {
 596                 compatible = "nvidia,tegra20-sdhci";
 597                 reg = <0xc8000000 0x200>;
 598                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 599                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 600                 status = "disabled";
 601         };
 602
 603         sdhci@c8000200 {
 604                 compatible = "nvidia,tegra20-sdhci";
 605                 reg = <0xc8000200 0x200>;
 606                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 607                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 608                 status = "disabled";
 609         };
 610
 611         sdhci@c8000400 {
 612                 compatible = "nvidia,tegra20-sdhci";
 613                 reg = <0xc8000400 0x200>;
 614                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 615                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 616                 status = "disabled";
 617         };
 618
 619         sdhci@c8000600 {
 620                 compatible = "nvidia,tegra20-sdhci";
 621                 reg = <0xc8000600 0x200>;
 622                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 624                 status = "disabled";
 625         };
 626
 627         cpus {
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630
 631                 cpu@0 {
 632                         device_type = "cpu";
 633                         compatible = "arm,cortex-a9";
 634                         reg = <0>;
 635                 };
 636
 637                 cpu@1 {
 638                         device_type = "cpu";
 639                         compatible = "arm,cortex-a9";
 640                         reg = <1>;
 641                 };
 642         };
 643
 644         pmu {
 645                 compatible = "arm,cortex-a9-pmu";
 646                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 647                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 648         };
 649 };