arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/clock/tegra20-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra20";
  10         interrupt-parent = <&intc>;
  11
  12         host1x@50000000 {
  13                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  14                 reg = <0x50000000 0x00024000>;
  15                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  16                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  17                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  18                 resets = <&tegra_car 28>;
  19                 reset-names = "host1x";
  20
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23
  24                 ranges = <0x54000000 0x54000000 0x04000000>;
  25
  26                 mpe@54040000 {
  27                         compatible = "nvidia,tegra20-mpe";
  28                         reg = <0x54040000 0x00040000>;
  29                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  30                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  31                         resets = <&tegra_car 60>;
  32                         reset-names = "mpe";
  33                 };
  34
  35                 vi@54080000 {
  36                         compatible = "nvidia,tegra20-vi";
  37                         reg = <0x54080000 0x00040000>;
  38                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  39                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  40                         resets = <&tegra_car 20>;
  41                         reset-names = "vi";
  42                 };
  43
  44                 epp@540c0000 {
  45                         compatible = "nvidia,tegra20-epp";
  46                         reg = <0x540c0000 0x00040000>;
  47                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  49                         resets = <&tegra_car 19>;
  50                         reset-names = "epp";
  51                 };
  52
  53                 isp@54100000 {
  54                         compatible = "nvidia,tegra20-isp";
  55                         reg = <0x54100000 0x00040000>;
  56                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  57                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  58                         resets = <&tegra_car 23>;
  59                         reset-names = "isp";
  60                 };
  61
  62                 gr2d@54140000 {
  63                         compatible = "nvidia,tegra20-gr2d";
  64                         reg = <0x54140000 0x00040000>;
  65                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  67                         resets = <&tegra_car 21>;
  68                         reset-names = "2d";
  69                 };
  70
  71                 gr3d@54180000 {
  72                         compatible = "nvidia,tegra20-gr3d";
  73                         reg = <0x54180000 0x00040000>;
  74                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  75                         resets = <&tegra_car 24>;
  76                         reset-names = "3d";
  77                 };
  78
  79                 dc@54200000 {
  80                         compatible = "nvidia,tegra20-dc";
  81                         reg = <0x54200000 0x00040000>;
  82                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  83                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  84                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  85                         clock-names = "dc", "parent";
  86                         resets = <&tegra_car 27>;
  87                         reset-names = "dc";
  88
  89                         nvidia,head = <0>;
  90
  91                         rgb {
  92                                 status = "disabled";
  93                         };
  94                 };
  95
  96                 dc@54240000 {
  97                         compatible = "nvidia,tegra20-dc";
  98                         reg = <0x54240000 0x00040000>;
  99                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 100                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 101                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 102                         clock-names = "dc", "parent";
 103                         resets = <&tegra_car 26>;
 104                         reset-names = "dc";
 105
 106                         nvidia,head = <1>;
 107
 108                         rgb {
 109                                 status = "disabled";
 110                         };
 111                 };
 112
 113                 hdmi@54280000 {
 114                         compatible = "nvidia,tegra20-hdmi";
 115                         reg = <0x54280000 0x00040000>;
 116                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 118                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 119                         clock-names = "hdmi", "parent";
 120                         resets = <&tegra_car 51>;
 121                         reset-names = "hdmi";
 122                         status = "disabled";
 123                 };
 124
 125                 tvo@542c0000 {
 126                         compatible = "nvidia,tegra20-tvo";
 127                         reg = <0x542c0000 0x00040000>;
 128                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 130                         status = "disabled";
 131                 };
 132
 133                 dsi@54300000 {
 134                         compatible = "nvidia,tegra20-dsi";
 135                         reg = <0x54300000 0x00040000>;
 136                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 137                         resets = <&tegra_car 48>;
 138                         reset-names = "dsi";
 139                         status = "disabled";
 140                 };
 141         };
 142
 143         timer@50040600 {
 144                 compatible = "arm,cortex-a9-twd-timer";
 145                 reg = <0x50040600 0x20>;
 146                 interrupts = <GIC_PPI 13
 147                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 148                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 149         };
 150
 151         intc: interrupt-controller@50041000 {
 152                 compatible = "arm,cortex-a9-gic";
 153                 reg = <0x50041000 0x1000
 154                        0x50040100 0x0100>;
 155                 interrupt-controller;
 156                 #interrupt-cells = <3>;
 157         };
 158
 159         cache-controller@50043000 {
 160                 compatible = "arm,pl310-cache";
 161                 reg = <0x50043000 0x1000>;
 162                 arm,data-latency = <5 5 2>;
 163                 arm,tag-latency = <4 4 2>;
 164                 cache-unified;
 165                 cache-level = <2>;
 166         };
 167
 168         timer@60005000 {
 169                 compatible = "nvidia,tegra20-timer";
 170                 reg = <0x60005000 0x60>;
 171                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 176         };
 177
 178         tegra_car: clock@60006000 {
 179                 compatible = "nvidia,tegra20-car";
 180                 reg = <0x60006000 0x1000>;
 181                 #clock-cells = <1>;
 182                 #reset-cells = <1>;
 183         };
 184
 185         flow-controller@60007000 {
 186                 compatible = "nvidia,tegra20-flowctrl";
 187                 reg = <0x60007000 0x1000>;
 188         };
 189
 190         apbdma: dma@6000a000 {
 191                 compatible = "nvidia,tegra20-apbdma";
 192                 reg = <0x6000a000 0x1200>;
 193                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 210                 resets = <&tegra_car 34>;
 211                 reset-names = "dma";
 212                 #dma-cells = <1>;
 213         };
 214
 215         ahb@6000c004 {
 216                 compatible = "nvidia,tegra20-ahb";
 217                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 218         };
 219
 220         gpio: gpio@6000d000 {
 221                 compatible = "nvidia,tegra20-gpio";
 222                 reg = <0x6000d000 0x1000>;
 223                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 230                 #gpio-cells = <2>;
 231                 gpio-controller;
 232                 #interrupt-cells = <2>;
 233                 interrupt-controller;
 234         };
 235
 236         apbmisc@70000800 {
 237                 compatible = "nvidia,tegra20-apbmisc";
 238                 reg = <0x70000800 0x64   /* Chip revision */
 239                        0x70000008 0x04>; /* Strapping options */
 240         };
 241
 242         pinmux: pinmux@70000014 {
 243                 compatible = "nvidia,tegra20-pinmux";
 244                 reg = <0x70000014 0x10   /* Tri-state registers */
 245                        0x70000080 0x20   /* Mux registers */
 246                        0x700000a0 0x14   /* Pull-up/down registers */
 247                        0x70000868 0xa8>; /* Pad control registers */
 248         };
 249
 250         das@70000c00 {
 251                 compatible = "nvidia,tegra20-das";
 252                 reg = <0x70000c00 0x80>;
 253         };
 254
 255         tegra_ac97: ac97@70002000 {
 256                 compatible = "nvidia,tegra20-ac97";
 257                 reg = <0x70002000 0x200>;
 258                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 260                 resets = <&tegra_car 3>;
 261                 reset-names = "ac97";
 262                 dmas = <&apbdma 12>, <&apbdma 12>;
 263                 dma-names = "rx", "tx";
 264                 status = "disabled";
 265         };
 266
 267         tegra_i2s1: i2s@70002800 {
 268                 compatible = "nvidia,tegra20-i2s";
 269                 reg = <0x70002800 0x200>;
 270                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 272                 resets = <&tegra_car 11>;
 273                 reset-names = "i2s";
 274                 dmas = <&apbdma 2>, <&apbdma 2>;
 275                 dma-names = "rx", "tx";
 276                 status = "disabled";
 277         };
 278
 279         tegra_i2s2: i2s@70002a00 {
 280                 compatible = "nvidia,tegra20-i2s";
 281                 reg = <0x70002a00 0x200>;
 282                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 284                 resets = <&tegra_car 18>;
 285                 reset-names = "i2s";
 286                 dmas = <&apbdma 1>, <&apbdma 1>;
 287                 dma-names = "rx", "tx";
 288                 status = "disabled";
 289         };
 290
 291         /*
 292          * There are two serial driver i.e. 8250 based simple serial
 293          * driver and APB DMA based serial driver for higher baudrate
 294          * and performace. To enable the 8250 based driver, the compatible
 295          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 296          * driver, the comptible is "nvidia,tegra20-hsuart".
 297          */
 298         uarta: serial@70006000 {
 299                 compatible = "nvidia,tegra20-uart";
 300                 reg = <0x70006000 0x40>;
 301                 reg-shift = <2>;
 302                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 304                 resets = <&tegra_car 6>;
 305                 reset-names = "serial";
 306                 dmas = <&apbdma 8>, <&apbdma 8>;
 307                 dma-names = "rx", "tx";
 308                 status = "disabled";
 309         };
 310
 311         uartb: serial@70006040 {
 312                 compatible = "nvidia,tegra20-uart";
 313                 reg = <0x70006040 0x40>;
 314                 reg-shift = <2>;
 315                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 317                 resets = <&tegra_car 7>;
 318                 reset-names = "serial";
 319                 dmas = <&apbdma 9>, <&apbdma 9>;
 320                 dma-names = "rx", "tx";
 321                 status = "disabled";
 322         };
 323
 324         uartc: serial@70006200 {
 325                 compatible = "nvidia,tegra20-uart";
 326                 reg = <0x70006200 0x100>;
 327                 reg-shift = <2>;
 328                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 330                 resets = <&tegra_car 55>;
 331                 reset-names = "serial";
 332                 dmas = <&apbdma 10>, <&apbdma 10>;
 333                 dma-names = "rx", "tx";
 334                 status = "disabled";
 335         };
 336
 337         uartd: serial@70006300 {
 338                 compatible = "nvidia,tegra20-uart";
 339                 reg = <0x70006300 0x100>;
 340                 reg-shift = <2>;
 341                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 343                 resets = <&tegra_car 65>;
 344                 reset-names = "serial";
 345                 dmas = <&apbdma 19>, <&apbdma 19>;
 346                 dma-names = "rx", "tx";
 347                 status = "disabled";
 348         };
 349
 350         uarte: serial@70006400 {
 351                 compatible = "nvidia,tegra20-uart";
 352                 reg = <0x70006400 0x100>;
 353                 reg-shift = <2>;
 354                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 356                 resets = <&tegra_car 66>;
 357                 reset-names = "serial";
 358                 dmas = <&apbdma 20>, <&apbdma 20>;
 359                 dma-names = "rx", "tx";
 360                 status = "disabled";
 361         };
 362
 363         pwm: pwm@7000a000 {
 364                 compatible = "nvidia,tegra20-pwm";
 365                 reg = <0x7000a000 0x100>;
 366                 #pwm-cells = <2>;
 367                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 368                 resets = <&tegra_car 17>;
 369                 reset-names = "pwm";
 370                 status = "disabled";
 371         };
 372
 373         rtc@7000e000 {
 374                 compatible = "nvidia,tegra20-rtc";
 375                 reg = <0x7000e000 0x100>;
 376                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 378         };
 379
 380         i2c@7000c000 {
 381                 compatible = "nvidia,tegra20-i2c";
 382                 reg = <0x7000c000 0x100>;
 383                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 387                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 388                 clock-names = "div-clk", "fast-clk";
 389                 resets = <&tegra_car 12>;
 390                 reset-names = "i2c";
 391                 dmas = <&apbdma 21>, <&apbdma 21>;
 392                 dma-names = "rx", "tx";
 393                 status = "disabled";
 394         };
 395
 396         spi@7000c380 {
 397                 compatible = "nvidia,tegra20-sflash";
 398                 reg = <0x7000c380 0x80>;
 399                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 403                 resets = <&tegra_car 43>;
 404                 reset-names = "spi";
 405                 dmas = <&apbdma 11>, <&apbdma 11>;
 406                 dma-names = "rx", "tx";
 407                 status = "disabled";
 408         };
 409
 410         i2c@7000c400 {
 411                 compatible = "nvidia,tegra20-i2c";
 412                 reg = <0x7000c400 0x100>;
 413                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 417                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 418                 clock-names = "div-clk", "fast-clk";
 419                 resets = <&tegra_car 54>;
 420                 reset-names = "i2c";
 421                 dmas = <&apbdma 22>, <&apbdma 22>;
 422                 dma-names = "rx", "tx";
 423                 status = "disabled";
 424         };
 425
 426         i2c@7000c500 {
 427                 compatible = "nvidia,tegra20-i2c";
 428                 reg = <0x7000c500 0x100>;
 429                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 433                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 434                 clock-names = "div-clk", "fast-clk";
 435                 resets = <&tegra_car 67>;
 436                 reset-names = "i2c";
 437                 dmas = <&apbdma 23>, <&apbdma 23>;
 438                 dma-names = "rx", "tx";
 439                 status = "disabled";
 440         };
 441
 442         i2c@7000d000 {
 443                 compatible = "nvidia,tegra20-i2c-dvc";
 444                 reg = <0x7000d000 0x200>;
 445                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 449                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 450                 clock-names = "div-clk", "fast-clk";
 451                 resets = <&tegra_car 47>;
 452                 reset-names = "i2c";
 453                 dmas = <&apbdma 24>, <&apbdma 24>;
 454                 dma-names = "rx", "tx";
 455                 status = "disabled";
 456         };
 457
 458         spi@7000d400 {
 459                 compatible = "nvidia,tegra20-slink";
 460                 reg = <0x7000d400 0x200>;
 461                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 465                 resets = <&tegra_car 41>;
 466                 reset-names = "spi";
 467                 dmas = <&apbdma 15>, <&apbdma 15>;
 468                 dma-names = "rx", "tx";
 469                 status = "disabled";
 470         };
 471
 472         spi@7000d600 {
 473                 compatible = "nvidia,tegra20-slink";
 474                 reg = <0x7000d600 0x200>;
 475                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 479                 resets = <&tegra_car 44>;
 480                 reset-names = "spi";
 481                 dmas = <&apbdma 16>, <&apbdma 16>;
 482                 dma-names = "rx", "tx";
 483                 status = "disabled";
 484         };
 485
 486         spi@7000d800 {
 487                 compatible = "nvidia,tegra20-slink";
 488                 reg = <0x7000d800 0x200>;
 489                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 493                 resets = <&tegra_car 46>;
 494                 reset-names = "spi";
 495                 dmas = <&apbdma 17>, <&apbdma 17>;
 496                 dma-names = "rx", "tx";
 497                 status = "disabled";
 498         };
 499
 500         spi@7000da00 {
 501                 compatible = "nvidia,tegra20-slink";
 502                 reg = <0x7000da00 0x200>;
 503                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 507                 resets = <&tegra_car 68>;
 508                 reset-names = "spi";
 509                 dmas = <&apbdma 18>, <&apbdma 18>;
 510                 dma-names = "rx", "tx";
 511                 status = "disabled";
 512         };
 513
 514         kbc@7000e200 {
 515                 compatible = "nvidia,tegra20-kbc";
 516                 reg = <0x7000e200 0x100>;
 517                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 519                 resets = <&tegra_car 36>;
 520                 reset-names = "kbc";
 521                 status = "disabled";
 522         };
 523
 524         pmc@7000e400 {
 525                 compatible = "nvidia,tegra20-pmc";
 526                 reg = <0x7000e400 0x400>;
 527                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 528                 clock-names = "pclk", "clk32k_in";
 529         };
 530
 531         memory-controller@7000f000 {
 532                 compatible = "nvidia,tegra20-mc";
 533                 reg = <0x7000f000 0x024
 534                        0x7000f03c 0x3c4>;
 535                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 536         };
 537
 538         iommu@7000f024 {
 539                 compatible = "nvidia,tegra20-gart";
 540                 reg = <0x7000f024 0x00000018    /* controller registers */
 541                        0x58000000 0x02000000>;  /* GART aperture */
 542         };
 543
 544         memory-controller@7000f400 {
 545                 compatible = "nvidia,tegra20-emc";
 546                 reg = <0x7000f400 0x200>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549         };
 550
 551         fuse@7000f800 {
 552                 compatible = "nvidia,tegra20-efuse";
 553                 reg = <0x7000F800 0x400>;
 554                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 555                 clock-names = "fuse";
 556                 resets = <&tegra_car 39>;
 557                 reset-names = "fuse";
 558         };
 559
 560         pcie-controller@80003000 {
 561                 compatible = "nvidia,tegra20-pcie";
 562                 device_type = "pci";
 563                 reg = <0x80003000 0x00000800   /* PADS registers */
 564                        0x80003800 0x00000200   /* AFI registers */
 565                        0x90000000 0x10000000>; /* configuration space */
 566                 reg-names = "pads", "afi", "cs";
 567                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 568                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 569                 interrupt-names = "intr", "msi";
 570
 571                 #interrupt-cells = <1>;
 572                 interrupt-map-mask = <0 0 0 0>;
 573                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 574
 575                 bus-range = <0x00 0xff>;
 576                 #address-cells = <3>;
 577                 #size-cells = <2>;
 578
 579                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 580                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 581                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 582                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 583                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 584
 585                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 586                          <&tegra_car TEGRA20_CLK_AFI>,
 587                          <&tegra_car TEGRA20_CLK_PLL_E>;
 588                 clock-names = "pex", "afi", "pll_e";
 589                 resets = <&tegra_car 70>,
 590                          <&tegra_car 72>,
 591                          <&tegra_car 74>;
 592                 reset-names = "pex", "afi", "pcie_x";
 593                 status = "disabled";
 594
 595                 pci@1,0 {
 596                         device_type = "pci";
 597                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 598                         reg = <0x000800 0 0 0 0>;
 599                         status = "disabled";
 600
 601                         #address-cells = <3>;
 602                         #size-cells = <2>;
 603                         ranges;
 604
 605                         nvidia,num-lanes = <2>;
 606                 };
 607
 608                 pci@2,0 {
 609                         device_type = "pci";
 610                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 611                         reg = <0x001000 0 0 0 0>;
 612                         status = "disabled";
 613
 614                         #address-cells = <3>;
 615                         #size-cells = <2>;
 616                         ranges;
 617
 618                         nvidia,num-lanes = <2>;
 619                 };
 620         };
 621
 622         usb@c5000000 {
 623                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 624                 reg = <0xc5000000 0x4000>;
 625                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 626                 phy_type = "utmi";
 627                 nvidia,has-legacy-mode;
 628                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 629                 resets = <&tegra_car 22>;
 630                 reset-names = "usb";
 631                 nvidia,needs-double-reset;
 632                 nvidia,phy = <&phy1>;
 633                 status = "disabled";
 634         };
 635
 636         phy1: usb-phy@c5000000 {
 637                 compatible = "nvidia,tegra20-usb-phy";
 638                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 639                 phy_type = "utmi";
 640                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 641                          <&tegra_car TEGRA20_CLK_PLL_U>,
 642                          <&tegra_car TEGRA20_CLK_CLK_M>,
 643                          <&tegra_car TEGRA20_CLK_USBD>;
 644                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 645                 resets = <&tegra_car 22>, <&tegra_car 22>;
 646                 reset-names = "usb", "utmi-pads";
 647                 nvidia,has-legacy-mode;
 648                 nvidia,hssync-start-delay = <9>;
 649                 nvidia,idle-wait-delay = <17>;
 650                 nvidia,elastic-limit = <16>;
 651                 nvidia,term-range-adj = <6>;
 652                 nvidia,xcvr-setup = <9>;
 653                 nvidia,xcvr-lsfslew = <1>;
 654                 nvidia,xcvr-lsrslew = <1>;
 655                 nvidia,has-utmi-pad-registers;
 656                 status = "disabled";
 657         };
 658
 659         usb@c5004000 {
 660                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 661                 reg = <0xc5004000 0x4000>;
 662                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 663                 phy_type = "ulpi";
 664                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 665                 resets = <&tegra_car 58>;
 666                 reset-names = "usb";
 667                 nvidia,phy = <&phy2>;
 668                 status = "disabled";
 669         };
 670
 671         phy2: usb-phy@c5004000 {
 672                 compatible = "nvidia,tegra20-usb-phy";
 673                 reg = <0xc5004000 0x4000>;
 674                 phy_type = "ulpi";
 675                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 676                          <&tegra_car TEGRA20_CLK_PLL_U>,
 677                          <&tegra_car TEGRA20_CLK_CDEV2>;
 678                 clock-names = "reg", "pll_u", "ulpi-link";
 679                 resets = <&tegra_car 58>, <&tegra_car 22>;
 680                 reset-names = "usb", "utmi-pads";
 681                 status = "disabled";
 682         };
 683
 684         usb@c5008000 {
 685                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 686                 reg = <0xc5008000 0x4000>;
 687                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 688                 phy_type = "utmi";
 689                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 690                 resets = <&tegra_car 59>;
 691                 reset-names = "usb";
 692                 nvidia,phy = <&phy3>;
 693                 status = "disabled";
 694         };
 695
 696         phy3: usb-phy@c5008000 {
 697                 compatible = "nvidia,tegra20-usb-phy";
 698                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 699                 phy_type = "utmi";
 700                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 701                          <&tegra_car TEGRA20_CLK_PLL_U>,
 702                          <&tegra_car TEGRA20_CLK_CLK_M>,
 703                          <&tegra_car TEGRA20_CLK_USBD>;
 704                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 705                 resets = <&tegra_car 59>, <&tegra_car 22>;
 706                 reset-names = "usb", "utmi-pads";
 707                 nvidia,hssync-start-delay = <9>;
 708                 nvidia,idle-wait-delay = <17>;
 709                 nvidia,elastic-limit = <16>;
 710                 nvidia,term-range-adj = <6>;
 711                 nvidia,xcvr-setup = <9>;
 712                 nvidia,xcvr-lsfslew = <2>;
 713                 nvidia,xcvr-lsrslew = <2>;
 714                 status = "disabled";
 715         };
 716
 717         sdhci@c8000000 {
 718                 compatible = "nvidia,tegra20-sdhci";
 719                 reg = <0xc8000000 0x200>;
 720                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 722                 resets = <&tegra_car 14>;
 723                 reset-names = "sdhci";
 724                 status = "disabled";
 725         };
 726
 727         sdhci@c8000200 {
 728                 compatible = "nvidia,tegra20-sdhci";
 729                 reg = <0xc8000200 0x200>;
 730                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 731                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 732                 resets = <&tegra_car 9>;
 733                 reset-names = "sdhci";
 734                 status = "disabled";
 735         };
 736
 737         sdhci@c8000400 {
 738                 compatible = "nvidia,tegra20-sdhci";
 739                 reg = <0xc8000400 0x200>;
 740                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 742                 resets = <&tegra_car 69>;
 743                 reset-names = "sdhci";
 744                 status = "disabled";
 745         };
 746
 747         sdhci@c8000600 {
 748                 compatible = "nvidia,tegra20-sdhci";
 749                 reg = <0xc8000600 0x200>;
 750                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 751                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 752                 resets = <&tegra_car 15>;
 753                 reset-names = "sdhci";
 754                 status = "disabled";
 755         };
 756
 757         cpus {
 758                 #address-cells = <1>;
 759                 #size-cells = <0>;
 760
 761                 cpu@0 {
 762                         device_type = "cpu";
 763                         compatible = "arm,cortex-a9";
 764                         reg = <0>;
 765                 };
 766
 767                 cpu@1 {
 768                         device_type = "cpu";
 769                         compatible = "arm,cortex-a9";
 770                         reg = <1>;
 771                 };
 772         };
 773
 774         pmu {
 775                 compatible = "arm,cortex-a9-pmu";
 776                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 777                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 778         };
 779 };