arch/arm/boot/dts/versatile-ab.dts

   1 /dts-v1/;
   2 /include/ "skeleton.dtsi"
   3
   4 / {
   5         model = "ARM Versatile AB";
   6         compatible = "arm,versatile-ab";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart0;
  20         };
  21
  22         memory {
  23                 reg = <0x0 0x08000000>;
  24         };
  25
  26         xtal24mhz: xtal24mhz@24M {
  27                 #clock-cells = <0>;
  28                 compatible = "fixed-clock";
  29                 clock-frequency = <24000000>;
  30         };
  31
  32         core-module@10000000 {
  33                 compatible = "arm,core-module-versatile", "syscon";
  34                 reg = <0x10000000 0x200>;
  35
  36                 /* OSC1 on AB, OSC4 on PB */
  37                 osc1: cm_aux_osc@24M {
  38                         #clock-cells = <0>;
  39                         compatible = "arm,versatile-cm-auxosc";
  40                         clocks = <&xtal24mhz>;
  41                 };
  42
  43                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
  44                 timclk: timclk@1M {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-factor-clock";
  47                         clock-div = <24>;
  48                         clock-mult = <1>;
  49                         clocks = <&xtal24mhz>;
  50                 };
  51
  52                 pclk: pclk@24M {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-factor-clock";
  55                         clock-div = <1>;
  56                         clock-mult = <1>;
  57                         clocks = <&xtal24mhz>;
  58                 };
  59         };
  60
  61         flash@34000000 {
  62                 compatible = "arm,versatile-flash";
  63                 reg = <0x34000000 0x4000000>;
  64                 bank-width = <4>;
  65         };
  66
  67         i2c0: i2c@10002000 {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70                 compatible = "arm,versatile-i2c";
  71                 reg = <0x10002000 0x1000>;
  72
  73                 rtc@68 {
  74                         compatible = "dallas,ds1338";
  75                         reg = <0x68>;
  76                 };
  77         };
  78
  79         net@10010000 {
  80                 compatible = "smsc,lan91c111";
  81                 reg = <0x10010000 0x10000>;
  82                 interrupts = <25>;
  83         };
  84
  85         lcd@10008000 {
  86                 compatible = "arm,versatile-lcd";
  87                 reg = <0x10008000 0x1000>;
  88         };
  89
  90         amba {
  91                 compatible = "arm,amba-bus";
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 vic: intc@10140000 {
  97                         compatible = "arm,versatile-vic";
  98                         interrupt-controller;
  99                         #interrupt-cells = <1>;
 100                         reg = <0x10140000 0x1000>;
 101                         clear-mask = <0xffffffff>;
 102                         valid-mask = <0xffffffff>;
 103                 };
 104
 105                 sic: intc@10003000 {
 106                         compatible = "arm,versatile-sic";
 107                         interrupt-controller;
 108                         #interrupt-cells = <1>;
 109                         reg = <0x10003000 0x1000>;
 110                         interrupt-parent = <&vic>;
 111                         interrupts = <31>; /* Cascaded to vic */
 112                         clear-mask = <0xffffffff>;
 113                         valid-mask = <0xffc203f8>;
 114                 };
 115
 116                 dma@10130000 {
 117                         compatible = "arm,pl081", "arm,primecell";
 118                         reg = <0x10130000 0x1000>;
 119                         interrupts = <17>;
 120                         clocks = <&pclk>;
 121                         clock-names = "apb_pclk";
 122                 };
 123
 124                 uart0: uart@101f1000 {
 125                         compatible = "arm,pl011", "arm,primecell";
 126                         reg = <0x101f1000 0x1000>;
 127                         interrupts = <12>;
 128                         clocks = <&xtal24mhz>, <&pclk>;
 129                         clock-names = "uartclk", "apb_pclk";
 130                 };
 131
 132                 uart1: uart@101f2000 {
 133                         compatible = "arm,pl011", "arm,primecell";
 134                         reg = <0x101f2000 0x1000>;
 135                         interrupts = <13>;
 136                         clocks = <&xtal24mhz>, <&pclk>;
 137                         clock-names = "uartclk", "apb_pclk";
 138                 };
 139
 140                 uart2: uart@101f3000 {
 141                         compatible = "arm,pl011", "arm,primecell";
 142                         reg = <0x101f3000 0x1000>;
 143                         interrupts = <14>;
 144                         clocks = <&xtal24mhz>, <&pclk>;
 145                         clock-names = "uartclk", "apb_pclk";
 146                 };
 147
 148                 smc@10100000 {
 149                         compatible = "arm,primecell";
 150                         reg = <0x10100000 0x1000>;
 151                         clocks = <&pclk>;
 152                         clock-names = "apb_pclk";
 153                 };
 154
 155                 mpmc@10110000 {
 156                         compatible = "arm,primecell";
 157                         reg = <0x10110000 0x1000>;
 158                         clocks = <&pclk>;
 159                         clock-names = "apb_pclk";
 160                 };
 161
 162                 display@10120000 {
 163                         compatible = "arm,pl110", "arm,primecell";
 164                         reg = <0x10120000 0x1000>;
 165                         interrupts = <16>;
 166                         clocks = <&osc1>, <&pclk>;
 167                         clock-names = "clcd", "apb_pclk";
 168                 };
 169
 170                 sctl@101e0000 {
 171                         compatible = "arm,primecell";
 172                         reg = <0x101e0000 0x1000>;
 173                         clocks = <&pclk>;
 174                         clock-names = "apb_pclk";
 175                 };
 176
 177                 watchdog@101e1000 {
 178                         compatible = "arm,primecell";
 179                         reg = <0x101e1000 0x1000>;
 180                         interrupts = <0>;
 181                         clocks = <&pclk>;
 182                         clock-names = "apb_pclk";
 183                 };
 184
 185                 timer@101e2000 {
 186                         compatible = "arm,sp804", "arm,primecell";
 187                         reg = <0x101e2000 0x1000>;
 188                         interrupts = <4>;
 189                         clocks = <&timclk>, <&timclk>, <&pclk>;
 190                         clock-names = "timer0", "timer1", "apb_pclk";
 191                 };
 192
 193                 timer@101e3000 {
 194                         compatible = "arm,sp804", "arm,primecell";
 195                         reg = <0x101e3000 0x1000>;
 196                         interrupts = <5>;
 197                         clocks = <&timclk>, <&timclk>, <&pclk>;
 198                         clock-names = "timer0", "timer1", "apb_pclk";
 199                 };
 200
 201                 gpio0: gpio@101e4000 {
 202                         compatible = "arm,pl061", "arm,primecell";
 203                         reg = <0x101e4000 0x1000>;
 204                         gpio-controller;
 205                         interrupts = <6>;
 206                         #gpio-cells = <2>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <2>;
 209                         clocks = <&pclk>;
 210                         clock-names = "apb_pclk";
 211                 };
 212
 213                 gpio1: gpio@101e5000 {
 214                         compatible = "arm,pl061", "arm,primecell";
 215                         reg = <0x101e5000 0x1000>;
 216                         interrupts = <7>;
 217                         gpio-controller;
 218                         #gpio-cells = <2>;
 219                         interrupt-controller;
 220                         #interrupt-cells = <2>;
 221                         clocks = <&pclk>;
 222                         clock-names = "apb_pclk";
 223                 };
 224
 225                 rtc@101e8000 {
 226                         compatible = "arm,pl030", "arm,primecell";
 227                         reg = <0x101e8000 0x1000>;
 228                         interrupts = <10>;
 229                         clocks = <&pclk>;
 230                         clock-names = "apb_pclk";
 231                 };
 232
 233                 sci@101f0000 {
 234                         compatible = "arm,primecell";
 235                         reg = <0x101f0000 0x1000>;
 236                         interrupts = <15>;
 237                         clocks = <&pclk>;
 238                         clock-names = "apb_pclk";
 239                 };
 240
 241                 ssp@101f4000 {
 242                         compatible = "arm,pl022", "arm,primecell";
 243                         reg = <0x101f4000 0x1000>;
 244                         interrupts = <11>;
 245                         clocks = <&xtal24mhz>, <&pclk>;
 246                         clock-names = "SSPCLK", "apb_pclk";
 247                 };
 248
 249                 fpga {
 250                         compatible = "arm,versatile-fpga", "simple-bus";
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         ranges = <0 0x10000000 0x10000>;
 254
 255                         sysreg@0 {
 256                                 compatible = "arm,versatile-sysreg", "syscon";
 257                                 reg = <0x00000 0x1000>;
 258                         };
 259
 260                         aaci@4000 {
 261                                 compatible = "arm,primecell";
 262                                 reg = <0x4000 0x1000>;
 263                                 interrupts = <24>;
 264                                 clocks = <&pclk>;
 265                                 clock-names = "apb_pclk";
 266                         };
 267                         mmc@5000 {
 268                                 compatible = "arm,pl180", "arm,primecell";
 269                                 reg = < 0x5000 0x1000>;
 270                                 interrupts-extended = <&vic 22 &sic 2>;
 271                                 clocks = <&xtal24mhz>, <&pclk>;
 272                                 clock-names = "mclk", "apb_pclk";
 273                         };
 274                         kmi@6000 {
 275                                 compatible = "arm,pl050", "arm,primecell";
 276                                 reg = <0x6000 0x1000>;
 277                                 interrupt-parent = <&sic>;
 278                                 interrupts = <3>;
 279                                 clocks = <&xtal24mhz>, <&pclk>;
 280                                 clock-names = "KMIREFCLK", "apb_pclk";
 281                         };
 282                         kmi@7000 {
 283                                 compatible = "arm,pl050", "arm,primecell";
 284                                 reg = <0x7000 0x1000>;
 285                                 interrupt-parent = <&sic>;
 286                                 interrupts = <4>;
 287                                 clocks = <&xtal24mhz>, <&pclk>;
 288                                 clock-names = "KMIREFCLK", "apb_pclk";
 289                         };
 290                 };
 291         };
 292 };