2 * ARM Ltd. Versatile Express
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
13 model = "V2P-CA15_CA7";
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
38 compatible = "arm,cortex-a15";
40 cci-control-port = <&cci_control1>;
41 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
46 compatible = "arm,cortex-a15";
48 cci-control-port = <&cci_control1>;
49 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
54 compatible = "arm,cortex-a7";
56 cci-control-port = <&cci_control2>;
57 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
62 compatible = "arm,cortex-a7";
64 cci-control-port = <&cci_control2>;
65 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
70 compatible = "arm,cortex-a7";
72 cci-control-port = <&cci_control2>;
73 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
77 CLUSTER_SLEEP_BIG: cluster-sleep-big {
78 compatible = "arm,idle-state";
80 entry-latency-us = <1000>;
81 exit-latency-us = <700>;
82 min-residency-us = <2000>;
85 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
86 compatible = "arm,idle-state";
88 entry-latency-us = <1000>;
89 exit-latency-us = <500>;
90 min-residency-us = <2500>;
96 device_type = "memory";
97 reg = <0 0x80000000 0 0x40000000>;
101 compatible = "arm,sp805", "arm,primecell";
102 reg = <0 0x2a490000 0 0x1000>;
103 interrupts = <0 98 4>;
104 clocks = <&oscclk6a>, <&oscclk6a>;
105 clock-names = "wdogclk", "apb_pclk";
109 compatible = "arm,hdlcd";
110 reg = <0 0x2b000000 0 0x1000>;
111 interrupts = <0 85 4>;
113 clock-names = "pxlclk";
116 memory-controller@2b0a0000 {
117 compatible = "arm,pl341", "arm,primecell";
118 reg = <0 0x2b0a0000 0 0x1000>;
119 clocks = <&oscclk6a>;
120 clock-names = "apb_pclk";
123 gic: interrupt-controller@2c001000 {
124 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 #address-cells = <0>;
127 interrupt-controller;
128 reg = <0 0x2c001000 0 0x1000>,
129 <0 0x2c002000 0 0x1000>,
130 <0 0x2c004000 0 0x2000>,
131 <0 0x2c006000 0 0x2000>;
132 interrupts = <1 9 0xf04>;
136 compatible = "arm,cci-400";
137 #address-cells = <1>;
139 reg = <0 0x2c090000 0 0x1000>;
140 ranges = <0x0 0x0 0x2c090000 0x10000>;
142 cci_control1: slave-if@4000 {
143 compatible = "arm,cci-400-ctrl-if";
144 interface-type = "ace";
145 reg = <0x4000 0x1000>;
148 cci_control2: slave-if@5000 {
149 compatible = "arm,cci-400-ctrl-if";
150 interface-type = "ace";
151 reg = <0x5000 0x1000>;
155 memory-controller@7ffd0000 {
156 compatible = "arm,pl354", "arm,primecell";
157 reg = <0 0x7ffd0000 0 0x1000>;
158 interrupts = <0 86 4>,
160 clocks = <&oscclk6a>;
161 clock-names = "apb_pclk";
165 compatible = "arm,pl330", "arm,primecell";
166 reg = <0 0x7ff00000 0 0x1000>;
167 interrupts = <0 92 4>,
172 clocks = <&oscclk6a>;
173 clock-names = "apb_pclk";
177 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
178 reg = <0 0x7fff0000 0 0x1000>;
179 interrupts = <0 95 4>;
183 compatible = "arm,armv7-timer";
184 interrupts = <1 13 0xf08>,
191 compatible = "arm,cortex-a15-pmu";
192 interrupts = <0 68 4>,
197 /* Reference 24MHz clock */
198 compatible = "fixed-clock";
200 clock-frequency = <24000000>;
201 clock-output-names = "oscclk6a";
205 compatible = "arm,vexpress,config-bus";
206 arm,vexpress,config-bridge = <&v2m_sysreg>;
209 /* A15 PLL 0 reference clock */
210 compatible = "arm,vexpress-osc";
211 arm,vexpress-sysreg,func = <1 0>;
212 freq-range = <17000000 50000000>;
214 clock-output-names = "oscclk0";
218 /* A15 PLL 1 reference clock */
219 compatible = "arm,vexpress-osc";
220 arm,vexpress-sysreg,func = <1 1>;
221 freq-range = <17000000 50000000>;
223 clock-output-names = "oscclk1";
227 /* A7 PLL 0 reference clock */
228 compatible = "arm,vexpress-osc";
229 arm,vexpress-sysreg,func = <1 2>;
230 freq-range = <17000000 50000000>;
232 clock-output-names = "oscclk2";
236 /* A7 PLL 1 reference clock */
237 compatible = "arm,vexpress-osc";
238 arm,vexpress-sysreg,func = <1 3>;
239 freq-range = <17000000 50000000>;
241 clock-output-names = "oscclk3";
245 /* External AXI master clock */
246 compatible = "arm,vexpress-osc";
247 arm,vexpress-sysreg,func = <1 4>;
248 freq-range = <20000000 40000000>;
250 clock-output-names = "oscclk4";
254 /* HDLCD PLL reference clock */
255 compatible = "arm,vexpress-osc";
256 arm,vexpress-sysreg,func = <1 5>;
257 freq-range = <23750000 165000000>;
259 clock-output-names = "oscclk5";
263 /* Static memory controller clock */
264 compatible = "arm,vexpress-osc";
265 arm,vexpress-sysreg,func = <1 6>;
266 freq-range = <20000000 40000000>;
268 clock-output-names = "oscclk6";
272 /* SYS PLL reference clock */
273 compatible = "arm,vexpress-osc";
274 arm,vexpress-sysreg,func = <1 7>;
275 freq-range = <17000000 50000000>;
277 clock-output-names = "oscclk7";
281 /* DDR2 PLL reference clock */
282 compatible = "arm,vexpress-osc";
283 arm,vexpress-sysreg,func = <1 8>;
284 freq-range = <20000000 50000000>;
286 clock-output-names = "oscclk8";
290 /* A15 CPU core voltage */
291 compatible = "arm,vexpress-volt";
292 arm,vexpress-sysreg,func = <2 0>;
293 regulator-name = "A15 Vcore";
294 regulator-min-microvolt = <800000>;
295 regulator-max-microvolt = <1050000>;
301 /* A7 CPU core voltage */
302 compatible = "arm,vexpress-volt";
303 arm,vexpress-sysreg,func = <2 1>;
304 regulator-name = "A7 Vcore";
305 regulator-min-microvolt = <800000>;
306 regulator-max-microvolt = <1050000>;
312 /* Total current for the two A15 cores */
313 compatible = "arm,vexpress-amp";
314 arm,vexpress-sysreg,func = <3 0>;
319 /* Total current for the three A7 cores */
320 compatible = "arm,vexpress-amp";
321 arm,vexpress-sysreg,func = <3 1>;
326 /* DCC internal temperature */
327 compatible = "arm,vexpress-temp";
328 arm,vexpress-sysreg,func = <4 0>;
333 /* Total power for the two A15 cores */
334 compatible = "arm,vexpress-power";
335 arm,vexpress-sysreg,func = <12 0>;
340 /* Total power for the three A7 cores */
341 compatible = "arm,vexpress-power";
342 arm,vexpress-sysreg,func = <12 1>;
347 /* Total energy for the two A15 cores */
348 compatible = "arm,vexpress-energy";
349 arm,vexpress-sysreg,func = <13 0>, <13 1>;
354 /* Total energy for the three A7 cores */
355 compatible = "arm,vexpress-energy";
356 arm,vexpress-sysreg,func = <13 2>, <13 3>;
362 compatible = "simple-bus";
364 #address-cells = <2>;
366 ranges = <0 0 0 0x08000000 0x04000000>,
367 <1 0 0 0x14000000 0x04000000>,
368 <2 0 0 0x18000000 0x04000000>,
369 <3 0 0 0x1c000000 0x04000000>,
370 <4 0 0 0x0c000000 0x04000000>,
371 <5 0 0 0x10000000 0x04000000>;
373 #interrupt-cells = <1>;
374 interrupt-map-mask = <0 0 63>;
375 interrupt-map = <0 0 0 &gic 0 0 4>,
385 <0 0 10 &gic 0 10 4>,
386 <0 0 11 &gic 0 11 4>,
387 <0 0 12 &gic 0 12 4>,
388 <0 0 13 &gic 0 13 4>,
389 <0 0 14 &gic 0 14 4>,
390 <0 0 15 &gic 0 15 4>,
391 <0 0 16 &gic 0 16 4>,
392 <0 0 17 &gic 0 17 4>,
393 <0 0 18 &gic 0 18 4>,
394 <0 0 19 &gic 0 19 4>,
395 <0 0 20 &gic 0 20 4>,
396 <0 0 21 &gic 0 21 4>,
397 <0 0 22 &gic 0 22 4>,
398 <0 0 23 &gic 0 23 4>,
399 <0 0 24 &gic 0 24 4>,
400 <0 0 25 &gic 0 25 4>,
401 <0 0 26 &gic 0 26 4>,
402 <0 0 27 &gic 0 27 4>,
403 <0 0 28 &gic 0 28 4>,
404 <0 0 29 &gic 0 29 4>,
405 <0 0 30 &gic 0 30 4>,
406 <0 0 31 &gic 0 31 4>,
407 <0 0 32 &gic 0 32 4>,
408 <0 0 33 &gic 0 33 4>,
409 <0 0 34 &gic 0 34 4>,
410 <0 0 35 &gic 0 35 4>,
411 <0 0 36 &gic 0 36 4>,
412 <0 0 37 &gic 0 37 4>,
413 <0 0 38 &gic 0 38 4>,
414 <0 0 39 &gic 0 39 4>,
415 <0 0 40 &gic 0 40 4>,
416 <0 0 41 &gic 0 41 4>,
417 <0 0 42 &gic 0 42 4>;
419 /include/ "vexpress-v2m-rs1.dtsi"