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spi/build: Remove SPI_SIRF from compile test
[deliverable/linux.git] / arch / arm / common / edma.c
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/err.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/of_irq.h>
34 #include <linux/pm_runtime.h>
35
36 #include <linux/platform_data/edma.h>
37
38 /* Offsets matching "struct edmacc_param" */
39 #define PARM_OPT 0x00
40 #define PARM_SRC 0x04
41 #define PARM_A_B_CNT 0x08
42 #define PARM_DST 0x0c
43 #define PARM_SRC_DST_BIDX 0x10
44 #define PARM_LINK_BCNTRLD 0x14
45 #define PARM_SRC_DST_CIDX 0x18
46 #define PARM_CCNT 0x1c
47
48 #define PARM_SIZE 0x20
49
50 /* Offsets for EDMA CC global channel registers and their shadows */
51 #define SH_ER 0x00 /* 64 bits */
52 #define SH_ECR 0x08 /* 64 bits */
53 #define SH_ESR 0x10 /* 64 bits */
54 #define SH_CER 0x18 /* 64 bits */
55 #define SH_EER 0x20 /* 64 bits */
56 #define SH_EECR 0x28 /* 64 bits */
57 #define SH_EESR 0x30 /* 64 bits */
58 #define SH_SER 0x38 /* 64 bits */
59 #define SH_SECR 0x40 /* 64 bits */
60 #define SH_IER 0x50 /* 64 bits */
61 #define SH_IECR 0x58 /* 64 bits */
62 #define SH_IESR 0x60 /* 64 bits */
63 #define SH_IPR 0x68 /* 64 bits */
64 #define SH_ICR 0x70 /* 64 bits */
65 #define SH_IEVAL 0x78
66 #define SH_QER 0x80
67 #define SH_QEER 0x84
68 #define SH_QEECR 0x88
69 #define SH_QEESR 0x8c
70 #define SH_QSER 0x90
71 #define SH_QSECR 0x94
72 #define SH_SIZE 0x200
73
74 /* Offsets for EDMA CC global registers */
75 #define EDMA_REV 0x0000
76 #define EDMA_CCCFG 0x0004
77 #define EDMA_QCHMAP 0x0200 /* 8 registers */
78 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
79 #define EDMA_QDMAQNUM 0x0260
80 #define EDMA_QUETCMAP 0x0280
81 #define EDMA_QUEPRI 0x0284
82 #define EDMA_EMR 0x0300 /* 64 bits */
83 #define EDMA_EMCR 0x0308 /* 64 bits */
84 #define EDMA_QEMR 0x0310
85 #define EDMA_QEMCR 0x0314
86 #define EDMA_CCERR 0x0318
87 #define EDMA_CCERRCLR 0x031c
88 #define EDMA_EEVAL 0x0320
89 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
90 #define EDMA_QRAE 0x0380 /* 4 registers */
91 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
92 #define EDMA_QSTAT 0x0600 /* 2 registers */
93 #define EDMA_QWMTHRA 0x0620
94 #define EDMA_QWMTHRB 0x0624
95 #define EDMA_CCSTAT 0x0640
96
97 #define EDMA_M 0x1000 /* global channel registers */
98 #define EDMA_ECR 0x1008
99 #define EDMA_ECRH 0x100C
100 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
101 #define EDMA_PARM 0x4000 /* 128 param entries */
102
103 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
104
105 #define EDMA_DCHMAP 0x0100 /* 64 registers */
106 #define CHMAP_EXIST BIT(24)
107
108 #define EDMA_MAX_DMACH 64
109 #define EDMA_MAX_PARAMENTRY 512
110
111 /*****************************************************************************/
112
113 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
114
115 static inline unsigned int edma_read(unsigned ctlr, int offset)
116 {
117 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
118 }
119
120 static inline void edma_write(unsigned ctlr, int offset, int val)
121 {
122 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
123 }
124 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
125 unsigned or)
126 {
127 unsigned val = edma_read(ctlr, offset);
128 val &= and;
129 val |= or;
130 edma_write(ctlr, offset, val);
131 }
132 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
133 {
134 unsigned val = edma_read(ctlr, offset);
135 val &= and;
136 edma_write(ctlr, offset, val);
137 }
138 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
139 {
140 unsigned val = edma_read(ctlr, offset);
141 val |= or;
142 edma_write(ctlr, offset, val);
143 }
144 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
145 {
146 return edma_read(ctlr, offset + (i << 2));
147 }
148 static inline void edma_write_array(unsigned ctlr, int offset, int i,
149 unsigned val)
150 {
151 edma_write(ctlr, offset + (i << 2), val);
152 }
153 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
154 unsigned and, unsigned or)
155 {
156 edma_modify(ctlr, offset + (i << 2), and, or);
157 }
158 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
159 {
160 edma_or(ctlr, offset + (i << 2), or);
161 }
162 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
163 unsigned or)
164 {
165 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
166 }
167 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
168 unsigned val)
169 {
170 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
171 }
172 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
173 {
174 return edma_read(ctlr, EDMA_SHADOW0 + offset);
175 }
176 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
177 int i)
178 {
179 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
180 }
181 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
182 {
183 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
184 }
185 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
186 unsigned val)
187 {
188 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
189 }
190 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
191 int param_no)
192 {
193 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
194 }
195 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
196 unsigned val)
197 {
198 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
199 }
200 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
201 unsigned and, unsigned or)
202 {
203 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
204 }
205 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
206 unsigned and)
207 {
208 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
209 }
210 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
211 unsigned or)
212 {
213 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
214 }
215
216 static inline void set_bits(int offset, int len, unsigned long *p)
217 {
218 for (; len > 0; len--)
219 set_bit(offset + (len - 1), p);
220 }
221
222 static inline void clear_bits(int offset, int len, unsigned long *p)
223 {
224 for (; len > 0; len--)
225 clear_bit(offset + (len - 1), p);
226 }
227
228 /*****************************************************************************/
229
230 /* actual number of DMA channels and slots on this silicon */
231 struct edma {
232 /* how many dma resources of each type */
233 unsigned num_channels;
234 unsigned num_region;
235 unsigned num_slots;
236 unsigned num_tc;
237 unsigned num_cc;
238 enum dma_event_q default_queue;
239
240 /* list of channels with no even trigger; terminated by "-1" */
241 const s8 *noevent;
242
243 /* The edma_inuse bit for each PaRAM slot is clear unless the
244 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
245 */
246 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
247
248 /* The edma_unused bit for each channel is clear unless
249 * it is not being used on this platform. It uses a bit
250 * of SOC-specific initialization code.
251 */
252 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
253
254 unsigned irq_res_start;
255 unsigned irq_res_end;
256
257 struct dma_interrupt_data {
258 void (*callback)(unsigned channel, unsigned short ch_status,
259 void *data);
260 void *data;
261 } intr_data[EDMA_MAX_DMACH];
262 };
263
264 static struct edma *edma_cc[EDMA_MAX_CC];
265 static int arch_num_cc;
266
267 /* dummy param set used to (re)initialize parameter RAM slots */
268 static const struct edmacc_param dummy_paramset = {
269 .link_bcntrld = 0xffff,
270 .ccnt = 1,
271 };
272
273 /*****************************************************************************/
274
275 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
276 enum dma_event_q queue_no)
277 {
278 int bit = (ch_no & 0x7) * 4;
279
280 /* default to low priority queue */
281 if (queue_no == EVENTQ_DEFAULT)
282 queue_no = edma_cc[ctlr]->default_queue;
283
284 queue_no &= 7;
285 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
286 ~(0x7 << bit), queue_no << bit);
287 }
288
289 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
290 {
291 int bit = queue_no * 4;
292 edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
293 }
294
295 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
296 int priority)
297 {
298 int bit = queue_no * 4;
299 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
300 ((priority & 0x7) << bit));
301 }
302
303 /**
304 * map_dmach_param - Maps channel number to param entry number
305 *
306 * This maps the dma channel number to param entry numberter. In
307 * other words using the DMA channel mapping registers a param entry
308 * can be mapped to any channel
309 *
310 * Callers are responsible for ensuring the channel mapping logic is
311 * included in that particular EDMA variant (Eg : dm646x)
312 *
313 */
314 static void __init map_dmach_param(unsigned ctlr)
315 {
316 int i;
317 for (i = 0; i < EDMA_MAX_DMACH; i++)
318 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
319 }
320
321 static inline void
322 setup_dma_interrupt(unsigned lch,
323 void (*callback)(unsigned channel, u16 ch_status, void *data),
324 void *data)
325 {
326 unsigned ctlr;
327
328 ctlr = EDMA_CTLR(lch);
329 lch = EDMA_CHAN_SLOT(lch);
330
331 if (!callback)
332 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
333 BIT(lch & 0x1f));
334
335 edma_cc[ctlr]->intr_data[lch].callback = callback;
336 edma_cc[ctlr]->intr_data[lch].data = data;
337
338 if (callback) {
339 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
340 BIT(lch & 0x1f));
341 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
342 BIT(lch & 0x1f));
343 }
344 }
345
346 static int irq2ctlr(int irq)
347 {
348 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
349 return 0;
350 else if (irq >= edma_cc[1]->irq_res_start &&
351 irq <= edma_cc[1]->irq_res_end)
352 return 1;
353
354 return -1;
355 }
356
357 /******************************************************************************
358 *
359 * DMA interrupt handler
360 *
361 *****************************************************************************/
362 static irqreturn_t dma_irq_handler(int irq, void *data)
363 {
364 int ctlr;
365 u32 sh_ier;
366 u32 sh_ipr;
367 u32 bank;
368
369 ctlr = irq2ctlr(irq);
370 if (ctlr < 0)
371 return IRQ_NONE;
372
373 dev_dbg(data, "dma_irq_handler\n");
374
375 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
376 if (!sh_ipr) {
377 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
378 if (!sh_ipr)
379 return IRQ_NONE;
380 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
381 bank = 1;
382 } else {
383 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
384 bank = 0;
385 }
386
387 do {
388 u32 slot;
389 u32 channel;
390
391 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
392
393 slot = __ffs(sh_ipr);
394 sh_ipr &= ~(BIT(slot));
395
396 if (sh_ier & BIT(slot)) {
397 channel = (bank << 5) | slot;
398 /* Clear the corresponding IPR bits */
399 edma_shadow0_write_array(ctlr, SH_ICR, bank,
400 BIT(slot));
401 if (edma_cc[ctlr]->intr_data[channel].callback)
402 edma_cc[ctlr]->intr_data[channel].callback(
403 channel, DMA_COMPLETE,
404 edma_cc[ctlr]->intr_data[channel].data);
405 }
406 } while (sh_ipr);
407
408 edma_shadow0_write(ctlr, SH_IEVAL, 1);
409 return IRQ_HANDLED;
410 }
411
412 /******************************************************************************
413 *
414 * DMA error interrupt handler
415 *
416 *****************************************************************************/
417 static irqreturn_t dma_ccerr_handler(int irq, void *data)
418 {
419 int i;
420 int ctlr;
421 unsigned int cnt = 0;
422
423 ctlr = irq2ctlr(irq);
424 if (ctlr < 0)
425 return IRQ_NONE;
426
427 dev_dbg(data, "dma_ccerr_handler\n");
428
429 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
430 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
431 (edma_read(ctlr, EDMA_QEMR) == 0) &&
432 (edma_read(ctlr, EDMA_CCERR) == 0))
433 return IRQ_NONE;
434
435 while (1) {
436 int j = -1;
437 if (edma_read_array(ctlr, EDMA_EMR, 0))
438 j = 0;
439 else if (edma_read_array(ctlr, EDMA_EMR, 1))
440 j = 1;
441 if (j >= 0) {
442 dev_dbg(data, "EMR%d %08x\n", j,
443 edma_read_array(ctlr, EDMA_EMR, j));
444 for (i = 0; i < 32; i++) {
445 int k = (j << 5) + i;
446 if (edma_read_array(ctlr, EDMA_EMR, j) &
447 BIT(i)) {
448 /* Clear the corresponding EMR bits */
449 edma_write_array(ctlr, EDMA_EMCR, j,
450 BIT(i));
451 /* Clear any SER */
452 edma_shadow0_write_array(ctlr, SH_SECR,
453 j, BIT(i));
454 if (edma_cc[ctlr]->intr_data[k].
455 callback) {
456 edma_cc[ctlr]->intr_data[k].
457 callback(k,
458 DMA_CC_ERROR,
459 edma_cc[ctlr]->intr_data
460 [k].data);
461 }
462 }
463 }
464 } else if (edma_read(ctlr, EDMA_QEMR)) {
465 dev_dbg(data, "QEMR %02x\n",
466 edma_read(ctlr, EDMA_QEMR));
467 for (i = 0; i < 8; i++) {
468 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
469 /* Clear the corresponding IPR bits */
470 edma_write(ctlr, EDMA_QEMCR, BIT(i));
471 edma_shadow0_write(ctlr, SH_QSECR,
472 BIT(i));
473
474 /* NOTE: not reported!! */
475 }
476 }
477 } else if (edma_read(ctlr, EDMA_CCERR)) {
478 dev_dbg(data, "CCERR %08x\n",
479 edma_read(ctlr, EDMA_CCERR));
480 /* FIXME: CCERR.BIT(16) ignored! much better
481 * to just write CCERRCLR with CCERR value...
482 */
483 for (i = 0; i < 8; i++) {
484 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
485 /* Clear the corresponding IPR bits */
486 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
487
488 /* NOTE: not reported!! */
489 }
490 }
491 }
492 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
493 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
494 (edma_read(ctlr, EDMA_QEMR) == 0) &&
495 (edma_read(ctlr, EDMA_CCERR) == 0))
496 break;
497 cnt++;
498 if (cnt > 10)
499 break;
500 }
501 edma_write(ctlr, EDMA_EEVAL, 1);
502 return IRQ_HANDLED;
503 }
504
505 static int reserve_contiguous_slots(int ctlr, unsigned int id,
506 unsigned int num_slots,
507 unsigned int start_slot)
508 {
509 int i, j;
510 unsigned int count = num_slots;
511 int stop_slot = start_slot;
512 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
513
514 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
515 j = EDMA_CHAN_SLOT(i);
516 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
517 /* Record our current beginning slot */
518 if (count == num_slots)
519 stop_slot = i;
520
521 count--;
522 set_bit(j, tmp_inuse);
523
524 if (count == 0)
525 break;
526 } else {
527 clear_bit(j, tmp_inuse);
528
529 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
530 stop_slot = i;
531 break;
532 } else {
533 count = num_slots;
534 }
535 }
536 }
537
538 /*
539 * We have to clear any bits that we set
540 * if we run out parameter RAM slots, i.e we do find a set
541 * of contiguous parameter RAM slots but do not find the exact number
542 * requested as we may reach the total number of parameter RAM slots
543 */
544 if (i == edma_cc[ctlr]->num_slots)
545 stop_slot = i;
546
547 j = start_slot;
548 for_each_set_bit_from(j, tmp_inuse, stop_slot)
549 clear_bit(j, edma_cc[ctlr]->edma_inuse);
550
551 if (count)
552 return -EBUSY;
553
554 for (j = i - num_slots + 1; j <= i; ++j)
555 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
556 &dummy_paramset, PARM_SIZE);
557
558 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
559 }
560
561 static int prepare_unused_channel_list(struct device *dev, void *data)
562 {
563 struct platform_device *pdev = to_platform_device(dev);
564 int i, ctlr;
565
566 for (i = 0; i < pdev->num_resources; i++) {
567 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
568 (int)pdev->resource[i].start >= 0) {
569 ctlr = EDMA_CTLR(pdev->resource[i].start);
570 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
571 edma_cc[ctlr]->edma_unused);
572 }
573 }
574
575 return 0;
576 }
577
578 /*-----------------------------------------------------------------------*/
579
580 static bool unused_chan_list_done;
581
582 /* Resource alloc/free: dma channels, parameter RAM slots */
583
584 /**
585 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
586 * @channel: specific channel to allocate; negative for "any unmapped channel"
587 * @callback: optional; to be issued on DMA completion or errors
588 * @data: passed to callback
589 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
590 * Controller (TC) executes requests using this channel. Use
591 * EVENTQ_DEFAULT unless you really need a high priority queue.
592 *
593 * This allocates a DMA channel and its associated parameter RAM slot.
594 * The parameter RAM is initialized to hold a dummy transfer.
595 *
596 * Normal use is to pass a specific channel number as @channel, to make
597 * use of hardware events mapped to that channel. When the channel will
598 * be used only for software triggering or event chaining, channels not
599 * mapped to hardware events (or mapped to unused events) are preferable.
600 *
601 * DMA transfers start from a channel using edma_start(), or by
602 * chaining. When the transfer described in that channel's parameter RAM
603 * slot completes, that slot's data may be reloaded through a link.
604 *
605 * DMA errors are only reported to the @callback associated with the
606 * channel driving that transfer, but transfer completion callbacks can
607 * be sent to another channel under control of the TCC field in
608 * the option word of the transfer's parameter RAM set. Drivers must not
609 * use DMA transfer completion callbacks for channels they did not allocate.
610 * (The same applies to TCC codes used in transfer chaining.)
611 *
612 * Returns the number of the channel, else negative errno.
613 */
614 int edma_alloc_channel(int channel,
615 void (*callback)(unsigned channel, u16 ch_status, void *data),
616 void *data,
617 enum dma_event_q eventq_no)
618 {
619 unsigned i, done = 0, ctlr = 0;
620 int ret = 0;
621
622 if (!unused_chan_list_done) {
623 /*
624 * Scan all the platform devices to find out the EDMA channels
625 * used and clear them in the unused list, making the rest
626 * available for ARM usage.
627 */
628 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
629 prepare_unused_channel_list);
630 if (ret < 0)
631 return ret;
632
633 unused_chan_list_done = true;
634 }
635
636 if (channel >= 0) {
637 ctlr = EDMA_CTLR(channel);
638 channel = EDMA_CHAN_SLOT(channel);
639 }
640
641 if (channel < 0) {
642 for (i = 0; i < arch_num_cc; i++) {
643 channel = 0;
644 for (;;) {
645 channel = find_next_bit(edma_cc[i]->edma_unused,
646 edma_cc[i]->num_channels,
647 channel);
648 if (channel == edma_cc[i]->num_channels)
649 break;
650 if (!test_and_set_bit(channel,
651 edma_cc[i]->edma_inuse)) {
652 done = 1;
653 ctlr = i;
654 break;
655 }
656 channel++;
657 }
658 if (done)
659 break;
660 }
661 if (!done)
662 return -ENOMEM;
663 } else if (channel >= edma_cc[ctlr]->num_channels) {
664 return -EINVAL;
665 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
666 return -EBUSY;
667 }
668
669 /* ensure access through shadow region 0 */
670 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
671
672 /* ensure no events are pending */
673 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
674 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
675 &dummy_paramset, PARM_SIZE);
676
677 if (callback)
678 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
679 callback, data);
680
681 map_dmach_queue(ctlr, channel, eventq_no);
682
683 return EDMA_CTLR_CHAN(ctlr, channel);
684 }
685 EXPORT_SYMBOL(edma_alloc_channel);
686
687
688 /**
689 * edma_free_channel - deallocate DMA channel
690 * @channel: dma channel returned from edma_alloc_channel()
691 *
692 * This deallocates the DMA channel and associated parameter RAM slot
693 * allocated by edma_alloc_channel().
694 *
695 * Callers are responsible for ensuring the channel is inactive, and
696 * will not be reactivated by linking, chaining, or software calls to
697 * edma_start().
698 */
699 void edma_free_channel(unsigned channel)
700 {
701 unsigned ctlr;
702
703 ctlr = EDMA_CTLR(channel);
704 channel = EDMA_CHAN_SLOT(channel);
705
706 if (channel >= edma_cc[ctlr]->num_channels)
707 return;
708
709 setup_dma_interrupt(channel, NULL, NULL);
710 /* REVISIT should probably take out of shadow region 0 */
711
712 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
713 &dummy_paramset, PARM_SIZE);
714 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
715 }
716 EXPORT_SYMBOL(edma_free_channel);
717
718 /**
719 * edma_alloc_slot - allocate DMA parameter RAM
720 * @slot: specific slot to allocate; negative for "any unused slot"
721 *
722 * This allocates a parameter RAM slot, initializing it to hold a
723 * dummy transfer. Slots allocated using this routine have not been
724 * mapped to a hardware DMA channel, and will normally be used by
725 * linking to them from a slot associated with a DMA channel.
726 *
727 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
728 * slots may be allocated on behalf of DSP firmware.
729 *
730 * Returns the number of the slot, else negative errno.
731 */
732 int edma_alloc_slot(unsigned ctlr, int slot)
733 {
734 if (!edma_cc[ctlr])
735 return -EINVAL;
736
737 if (slot >= 0)
738 slot = EDMA_CHAN_SLOT(slot);
739
740 if (slot < 0) {
741 slot = edma_cc[ctlr]->num_channels;
742 for (;;) {
743 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
744 edma_cc[ctlr]->num_slots, slot);
745 if (slot == edma_cc[ctlr]->num_slots)
746 return -ENOMEM;
747 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
748 break;
749 }
750 } else if (slot < edma_cc[ctlr]->num_channels ||
751 slot >= edma_cc[ctlr]->num_slots) {
752 return -EINVAL;
753 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
754 return -EBUSY;
755 }
756
757 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
758 &dummy_paramset, PARM_SIZE);
759
760 return EDMA_CTLR_CHAN(ctlr, slot);
761 }
762 EXPORT_SYMBOL(edma_alloc_slot);
763
764 /**
765 * edma_free_slot - deallocate DMA parameter RAM
766 * @slot: parameter RAM slot returned from edma_alloc_slot()
767 *
768 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
769 * Callers are responsible for ensuring the slot is inactive, and will
770 * not be activated.
771 */
772 void edma_free_slot(unsigned slot)
773 {
774 unsigned ctlr;
775
776 ctlr = EDMA_CTLR(slot);
777 slot = EDMA_CHAN_SLOT(slot);
778
779 if (slot < edma_cc[ctlr]->num_channels ||
780 slot >= edma_cc[ctlr]->num_slots)
781 return;
782
783 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
784 &dummy_paramset, PARM_SIZE);
785 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
786 }
787 EXPORT_SYMBOL(edma_free_slot);
788
789
790 /**
791 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
792 * The API will return the starting point of a set of
793 * contiguous parameter RAM slots that have been requested
794 *
795 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
796 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
797 * @count: number of contiguous Paramter RAM slots
798 * @slot - the start value of Parameter RAM slot that should be passed if id
799 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
800 *
801 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
802 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
803 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
804 *
805 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
806 * set of contiguous parameter RAM slots from the "slot" that is passed as an
807 * argument to the API.
808 *
809 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
810 * starts looking for a set of contiguous parameter RAMs from the "slot"
811 * that is passed as an argument to the API. On failure the API will try to
812 * find a set of contiguous Parameter RAM slots from the remaining Parameter
813 * RAM slots
814 */
815 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
816 {
817 /*
818 * The start slot requested should be greater than
819 * the number of channels and lesser than the total number
820 * of slots
821 */
822 if ((id != EDMA_CONT_PARAMS_ANY) &&
823 (slot < edma_cc[ctlr]->num_channels ||
824 slot >= edma_cc[ctlr]->num_slots))
825 return -EINVAL;
826
827 /*
828 * The number of parameter RAM slots requested cannot be less than 1
829 * and cannot be more than the number of slots minus the number of
830 * channels
831 */
832 if (count < 1 || count >
833 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
834 return -EINVAL;
835
836 switch (id) {
837 case EDMA_CONT_PARAMS_ANY:
838 return reserve_contiguous_slots(ctlr, id, count,
839 edma_cc[ctlr]->num_channels);
840 case EDMA_CONT_PARAMS_FIXED_EXACT:
841 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
842 return reserve_contiguous_slots(ctlr, id, count, slot);
843 default:
844 return -EINVAL;
845 }
846
847 }
848 EXPORT_SYMBOL(edma_alloc_cont_slots);
849
850 /**
851 * edma_free_cont_slots - deallocate DMA parameter RAM slots
852 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
853 * @count: the number of contiguous parameter RAM slots to be freed
854 *
855 * This deallocates the parameter RAM slots allocated by
856 * edma_alloc_cont_slots.
857 * Callers/applications need to keep track of sets of contiguous
858 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
859 * API.
860 * Callers are responsible for ensuring the slots are inactive, and will
861 * not be activated.
862 */
863 int edma_free_cont_slots(unsigned slot, int count)
864 {
865 unsigned ctlr, slot_to_free;
866 int i;
867
868 ctlr = EDMA_CTLR(slot);
869 slot = EDMA_CHAN_SLOT(slot);
870
871 if (slot < edma_cc[ctlr]->num_channels ||
872 slot >= edma_cc[ctlr]->num_slots ||
873 count < 1)
874 return -EINVAL;
875
876 for (i = slot; i < slot + count; ++i) {
877 ctlr = EDMA_CTLR(i);
878 slot_to_free = EDMA_CHAN_SLOT(i);
879
880 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
881 &dummy_paramset, PARM_SIZE);
882 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
883 }
884
885 return 0;
886 }
887 EXPORT_SYMBOL(edma_free_cont_slots);
888
889 /*-----------------------------------------------------------------------*/
890
891 /* Parameter RAM operations (i) -- read/write partial slots */
892
893 /**
894 * edma_set_src - set initial DMA source address in parameter RAM slot
895 * @slot: parameter RAM slot being configured
896 * @src_port: physical address of source (memory, controller FIFO, etc)
897 * @addressMode: INCR, except in very rare cases
898 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
899 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
900 *
901 * Note that the source address is modified during the DMA transfer
902 * according to edma_set_src_index().
903 */
904 void edma_set_src(unsigned slot, dma_addr_t src_port,
905 enum address_mode mode, enum fifo_width width)
906 {
907 unsigned ctlr;
908
909 ctlr = EDMA_CTLR(slot);
910 slot = EDMA_CHAN_SLOT(slot);
911
912 if (slot < edma_cc[ctlr]->num_slots) {
913 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
914
915 if (mode) {
916 /* set SAM and program FWID */
917 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
918 } else {
919 /* clear SAM */
920 i &= ~SAM;
921 }
922 edma_parm_write(ctlr, PARM_OPT, slot, i);
923
924 /* set the source port address
925 in source register of param structure */
926 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
927 }
928 }
929 EXPORT_SYMBOL(edma_set_src);
930
931 /**
932 * edma_set_dest - set initial DMA destination address in parameter RAM slot
933 * @slot: parameter RAM slot being configured
934 * @dest_port: physical address of destination (memory, controller FIFO, etc)
935 * @addressMode: INCR, except in very rare cases
936 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
937 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
938 *
939 * Note that the destination address is modified during the DMA transfer
940 * according to edma_set_dest_index().
941 */
942 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
943 enum address_mode mode, enum fifo_width width)
944 {
945 unsigned ctlr;
946
947 ctlr = EDMA_CTLR(slot);
948 slot = EDMA_CHAN_SLOT(slot);
949
950 if (slot < edma_cc[ctlr]->num_slots) {
951 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
952
953 if (mode) {
954 /* set DAM and program FWID */
955 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
956 } else {
957 /* clear DAM */
958 i &= ~DAM;
959 }
960 edma_parm_write(ctlr, PARM_OPT, slot, i);
961 /* set the destination port address
962 in dest register of param structure */
963 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
964 }
965 }
966 EXPORT_SYMBOL(edma_set_dest);
967
968 /**
969 * edma_get_position - returns the current transfer points
970 * @slot: parameter RAM slot being examined
971 * @src: pointer to source port position
972 * @dst: pointer to destination port position
973 *
974 * Returns current source and destination addresses for a particular
975 * parameter RAM slot. Its channel should not be active when this is called.
976 */
977 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
978 {
979 struct edmacc_param temp;
980 unsigned ctlr;
981
982 ctlr = EDMA_CTLR(slot);
983 slot = EDMA_CHAN_SLOT(slot);
984
985 edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
986 if (src != NULL)
987 *src = temp.src;
988 if (dst != NULL)
989 *dst = temp.dst;
990 }
991 EXPORT_SYMBOL(edma_get_position);
992
993 /**
994 * edma_set_src_index - configure DMA source address indexing
995 * @slot: parameter RAM slot being configured
996 * @src_bidx: byte offset between source arrays in a frame
997 * @src_cidx: byte offset between source frames in a block
998 *
999 * Offsets are specified to support either contiguous or discontiguous
1000 * memory transfers, or repeated access to a hardware register, as needed.
1001 * When accessing hardware registers, both offsets are normally zero.
1002 */
1003 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1004 {
1005 unsigned ctlr;
1006
1007 ctlr = EDMA_CTLR(slot);
1008 slot = EDMA_CHAN_SLOT(slot);
1009
1010 if (slot < edma_cc[ctlr]->num_slots) {
1011 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1012 0xffff0000, src_bidx);
1013 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1014 0xffff0000, src_cidx);
1015 }
1016 }
1017 EXPORT_SYMBOL(edma_set_src_index);
1018
1019 /**
1020 * edma_set_dest_index - configure DMA destination address indexing
1021 * @slot: parameter RAM slot being configured
1022 * @dest_bidx: byte offset between destination arrays in a frame
1023 * @dest_cidx: byte offset between destination frames in a block
1024 *
1025 * Offsets are specified to support either contiguous or discontiguous
1026 * memory transfers, or repeated access to a hardware register, as needed.
1027 * When accessing hardware registers, both offsets are normally zero.
1028 */
1029 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1030 {
1031 unsigned ctlr;
1032
1033 ctlr = EDMA_CTLR(slot);
1034 slot = EDMA_CHAN_SLOT(slot);
1035
1036 if (slot < edma_cc[ctlr]->num_slots) {
1037 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1038 0x0000ffff, dest_bidx << 16);
1039 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1040 0x0000ffff, dest_cidx << 16);
1041 }
1042 }
1043 EXPORT_SYMBOL(edma_set_dest_index);
1044
1045 /**
1046 * edma_set_transfer_params - configure DMA transfer parameters
1047 * @slot: parameter RAM slot being configured
1048 * @acnt: how many bytes per array (at least one)
1049 * @bcnt: how many arrays per frame (at least one)
1050 * @ccnt: how many frames per block (at least one)
1051 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1052 * the value to reload into bcnt when it decrements to zero
1053 * @sync_mode: ASYNC or ABSYNC
1054 *
1055 * See the EDMA3 documentation to understand how to configure and link
1056 * transfers using the fields in PaRAM slots. If you are not doing it
1057 * all at once with edma_write_slot(), you will use this routine
1058 * plus two calls each for source and destination, setting the initial
1059 * address and saying how to index that address.
1060 *
1061 * An example of an A-Synchronized transfer is a serial link using a
1062 * single word shift register. In that case, @acnt would be equal to
1063 * that word size; the serial controller issues a DMA synchronization
1064 * event to transfer each word, and memory access by the DMA transfer
1065 * controller will be word-at-a-time.
1066 *
1067 * An example of an AB-Synchronized transfer is a device using a FIFO.
1068 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1069 * The controller with the FIFO issues DMA synchronization events when
1070 * the FIFO threshold is reached, and the DMA transfer controller will
1071 * transfer one frame to (or from) the FIFO. It will probably use
1072 * efficient burst modes to access memory.
1073 */
1074 void edma_set_transfer_params(unsigned slot,
1075 u16 acnt, u16 bcnt, u16 ccnt,
1076 u16 bcnt_rld, enum sync_dimension sync_mode)
1077 {
1078 unsigned ctlr;
1079
1080 ctlr = EDMA_CTLR(slot);
1081 slot = EDMA_CHAN_SLOT(slot);
1082
1083 if (slot < edma_cc[ctlr]->num_slots) {
1084 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1085 0x0000ffff, bcnt_rld << 16);
1086 if (sync_mode == ASYNC)
1087 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1088 else
1089 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1090 /* Set the acount, bcount, ccount registers */
1091 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1092 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1093 }
1094 }
1095 EXPORT_SYMBOL(edma_set_transfer_params);
1096
1097 /**
1098 * edma_link - link one parameter RAM slot to another
1099 * @from: parameter RAM slot originating the link
1100 * @to: parameter RAM slot which is the link target
1101 *
1102 * The originating slot should not be part of any active DMA transfer.
1103 */
1104 void edma_link(unsigned from, unsigned to)
1105 {
1106 unsigned ctlr_from, ctlr_to;
1107
1108 ctlr_from = EDMA_CTLR(from);
1109 from = EDMA_CHAN_SLOT(from);
1110 ctlr_to = EDMA_CTLR(to);
1111 to = EDMA_CHAN_SLOT(to);
1112
1113 if (from >= edma_cc[ctlr_from]->num_slots)
1114 return;
1115 if (to >= edma_cc[ctlr_to]->num_slots)
1116 return;
1117 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1118 PARM_OFFSET(to));
1119 }
1120 EXPORT_SYMBOL(edma_link);
1121
1122 /**
1123 * edma_unlink - cut link from one parameter RAM slot
1124 * @from: parameter RAM slot originating the link
1125 *
1126 * The originating slot should not be part of any active DMA transfer.
1127 * Its link is set to 0xffff.
1128 */
1129 void edma_unlink(unsigned from)
1130 {
1131 unsigned ctlr;
1132
1133 ctlr = EDMA_CTLR(from);
1134 from = EDMA_CHAN_SLOT(from);
1135
1136 if (from >= edma_cc[ctlr]->num_slots)
1137 return;
1138 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1139 }
1140 EXPORT_SYMBOL(edma_unlink);
1141
1142 /*-----------------------------------------------------------------------*/
1143
1144 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1145
1146 /**
1147 * edma_write_slot - write parameter RAM data for slot
1148 * @slot: number of parameter RAM slot being modified
1149 * @param: data to be written into parameter RAM slot
1150 *
1151 * Use this to assign all parameters of a transfer at once. This
1152 * allows more efficient setup of transfers than issuing multiple
1153 * calls to set up those parameters in small pieces, and provides
1154 * complete control over all transfer options.
1155 */
1156 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1157 {
1158 unsigned ctlr;
1159
1160 ctlr = EDMA_CTLR(slot);
1161 slot = EDMA_CHAN_SLOT(slot);
1162
1163 if (slot >= edma_cc[ctlr]->num_slots)
1164 return;
1165 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1166 PARM_SIZE);
1167 }
1168 EXPORT_SYMBOL(edma_write_slot);
1169
1170 /**
1171 * edma_read_slot - read parameter RAM data from slot
1172 * @slot: number of parameter RAM slot being copied
1173 * @param: where to store copy of parameter RAM data
1174 *
1175 * Use this to read data from a parameter RAM slot, perhaps to
1176 * save them as a template for later reuse.
1177 */
1178 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1179 {
1180 unsigned ctlr;
1181
1182 ctlr = EDMA_CTLR(slot);
1183 slot = EDMA_CHAN_SLOT(slot);
1184
1185 if (slot >= edma_cc[ctlr]->num_slots)
1186 return;
1187 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1188 PARM_SIZE);
1189 }
1190 EXPORT_SYMBOL(edma_read_slot);
1191
1192 /*-----------------------------------------------------------------------*/
1193
1194 /* Various EDMA channel control operations */
1195
1196 /**
1197 * edma_pause - pause dma on a channel
1198 * @channel: on which edma_start() has been called
1199 *
1200 * This temporarily disables EDMA hardware events on the specified channel,
1201 * preventing them from triggering new transfers on its behalf
1202 */
1203 void edma_pause(unsigned channel)
1204 {
1205 unsigned ctlr;
1206
1207 ctlr = EDMA_CTLR(channel);
1208 channel = EDMA_CHAN_SLOT(channel);
1209
1210 if (channel < edma_cc[ctlr]->num_channels) {
1211 unsigned int mask = BIT(channel & 0x1f);
1212
1213 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1214 }
1215 }
1216 EXPORT_SYMBOL(edma_pause);
1217
1218 /**
1219 * edma_resume - resumes dma on a paused channel
1220 * @channel: on which edma_pause() has been called
1221 *
1222 * This re-enables EDMA hardware events on the specified channel.
1223 */
1224 void edma_resume(unsigned channel)
1225 {
1226 unsigned ctlr;
1227
1228 ctlr = EDMA_CTLR(channel);
1229 channel = EDMA_CHAN_SLOT(channel);
1230
1231 if (channel < edma_cc[ctlr]->num_channels) {
1232 unsigned int mask = BIT(channel & 0x1f);
1233
1234 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1235 }
1236 }
1237 EXPORT_SYMBOL(edma_resume);
1238
1239 /**
1240 * edma_start - start dma on a channel
1241 * @channel: channel being activated
1242 *
1243 * Channels with event associations will be triggered by their hardware
1244 * events, and channels without such associations will be triggered by
1245 * software. (At this writing there is no interface for using software
1246 * triggers except with channels that don't support hardware triggers.)
1247 *
1248 * Returns zero on success, else negative errno.
1249 */
1250 int edma_start(unsigned channel)
1251 {
1252 unsigned ctlr;
1253
1254 ctlr = EDMA_CTLR(channel);
1255 channel = EDMA_CHAN_SLOT(channel);
1256
1257 if (channel < edma_cc[ctlr]->num_channels) {
1258 int j = channel >> 5;
1259 unsigned int mask = BIT(channel & 0x1f);
1260
1261 /* EDMA channels without event association */
1262 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1263 pr_debug("EDMA: ESR%d %08x\n", j,
1264 edma_shadow0_read_array(ctlr, SH_ESR, j));
1265 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1266 return 0;
1267 }
1268
1269 /* EDMA channel with event association */
1270 pr_debug("EDMA: ER%d %08x\n", j,
1271 edma_shadow0_read_array(ctlr, SH_ER, j));
1272 /* Clear any pending event or error */
1273 edma_write_array(ctlr, EDMA_ECR, j, mask);
1274 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1275 /* Clear any SER */
1276 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1277 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1278 pr_debug("EDMA: EER%d %08x\n", j,
1279 edma_shadow0_read_array(ctlr, SH_EER, j));
1280 return 0;
1281 }
1282
1283 return -EINVAL;
1284 }
1285 EXPORT_SYMBOL(edma_start);
1286
1287 /**
1288 * edma_stop - stops dma on the channel passed
1289 * @channel: channel being deactivated
1290 *
1291 * When @lch is a channel, any active transfer is paused and
1292 * all pending hardware events are cleared. The current transfer
1293 * may not be resumed, and the channel's Parameter RAM should be
1294 * reinitialized before being reused.
1295 */
1296 void edma_stop(unsigned channel)
1297 {
1298 unsigned ctlr;
1299
1300 ctlr = EDMA_CTLR(channel);
1301 channel = EDMA_CHAN_SLOT(channel);
1302
1303 if (channel < edma_cc[ctlr]->num_channels) {
1304 int j = channel >> 5;
1305 unsigned int mask = BIT(channel & 0x1f);
1306
1307 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1308 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1309 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1310 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1311
1312 pr_debug("EDMA: EER%d %08x\n", j,
1313 edma_shadow0_read_array(ctlr, SH_EER, j));
1314
1315 /* REVISIT: consider guarding against inappropriate event
1316 * chaining by overwriting with dummy_paramset.
1317 */
1318 }
1319 }
1320 EXPORT_SYMBOL(edma_stop);
1321
1322 /******************************************************************************
1323 *
1324 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1325 * been removed before EDMA has finished.It is usedful for removable media.
1326 * Arguments:
1327 * ch_no - channel no
1328 *
1329 * Return: zero on success, or corresponding error no on failure
1330 *
1331 * FIXME this should not be needed ... edma_stop() should suffice.
1332 *
1333 *****************************************************************************/
1334
1335 void edma_clean_channel(unsigned channel)
1336 {
1337 unsigned ctlr;
1338
1339 ctlr = EDMA_CTLR(channel);
1340 channel = EDMA_CHAN_SLOT(channel);
1341
1342 if (channel < edma_cc[ctlr]->num_channels) {
1343 int j = (channel >> 5);
1344 unsigned int mask = BIT(channel & 0x1f);
1345
1346 pr_debug("EDMA: EMR%d %08x\n", j,
1347 edma_read_array(ctlr, EDMA_EMR, j));
1348 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1349 /* Clear the corresponding EMR bits */
1350 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1351 /* Clear any SER */
1352 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1353 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1354 }
1355 }
1356 EXPORT_SYMBOL(edma_clean_channel);
1357
1358 /*
1359 * edma_clear_event - clear an outstanding event on the DMA channel
1360 * Arguments:
1361 * channel - channel number
1362 */
1363 void edma_clear_event(unsigned channel)
1364 {
1365 unsigned ctlr;
1366
1367 ctlr = EDMA_CTLR(channel);
1368 channel = EDMA_CHAN_SLOT(channel);
1369
1370 if (channel >= edma_cc[ctlr]->num_channels)
1371 return;
1372 if (channel < 32)
1373 edma_write(ctlr, EDMA_ECR, BIT(channel));
1374 else
1375 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1376 }
1377 EXPORT_SYMBOL(edma_clear_event);
1378
1379 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1380
1381 static int edma_of_read_u32_to_s16_array(const struct device_node *np,
1382 const char *propname, s16 *out_values,
1383 size_t sz)
1384 {
1385 int ret;
1386
1387 ret = of_property_read_u16_array(np, propname, out_values, sz);
1388 if (ret)
1389 return ret;
1390
1391 /* Terminate it */
1392 *out_values++ = -1;
1393 *out_values++ = -1;
1394
1395 return 0;
1396 }
1397
1398 static int edma_xbar_event_map(struct device *dev,
1399 struct device_node *node,
1400 struct edma_soc_info *pdata, int len)
1401 {
1402 int ret, i;
1403 struct resource res;
1404 void __iomem *xbar;
1405 const s16 (*xbar_chans)[2];
1406 u32 shift, offset, mux;
1407
1408 xbar_chans = devm_kzalloc(dev,
1409 len/sizeof(s16) + 2*sizeof(s16),
1410 GFP_KERNEL);
1411 if (!xbar_chans)
1412 return -ENOMEM;
1413
1414 ret = of_address_to_resource(node, 1, &res);
1415 if (ret)
1416 return -EIO;
1417
1418 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1419 if (!xbar)
1420 return -ENOMEM;
1421
1422 ret = edma_of_read_u32_to_s16_array(node,
1423 "ti,edma-xbar-event-map",
1424 (s16 *)xbar_chans,
1425 len/sizeof(u32));
1426 if (ret)
1427 return -EIO;
1428
1429 for (i = 0; xbar_chans[i][0] != -1; i++) {
1430 shift = (xbar_chans[i][1] & 0x03) << 3;
1431 offset = xbar_chans[i][1] & 0xfffffffc;
1432 mux = readl(xbar + offset);
1433 mux &= ~(0xff << shift);
1434 mux |= xbar_chans[i][0] << shift;
1435 writel(mux, (xbar + offset));
1436 }
1437
1438 pdata->xbar_chans = xbar_chans;
1439
1440 return 0;
1441 }
1442
1443 static int edma_of_parse_dt(struct device *dev,
1444 struct device_node *node,
1445 struct edma_soc_info *pdata)
1446 {
1447 int ret = 0, i;
1448 u32 value;
1449 struct property *prop;
1450 size_t sz;
1451 struct edma_rsv_info *rsv_info;
1452 s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
1453
1454 memset(pdata, 0, sizeof(struct edma_soc_info));
1455
1456 ret = of_property_read_u32(node, "dma-channels", &value);
1457 if (ret < 0)
1458 return ret;
1459 pdata->n_channel = value;
1460
1461 ret = of_property_read_u32(node, "ti,edma-regions", &value);
1462 if (ret < 0)
1463 return ret;
1464 pdata->n_region = value;
1465
1466 ret = of_property_read_u32(node, "ti,edma-slots", &value);
1467 if (ret < 0)
1468 return ret;
1469 pdata->n_slot = value;
1470
1471 pdata->n_cc = 1;
1472
1473 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1474 if (!rsv_info)
1475 return -ENOMEM;
1476 pdata->rsv = rsv_info;
1477
1478 queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1479 if (!queue_tc_map)
1480 return -ENOMEM;
1481
1482 for (i = 0; i < 3; i++) {
1483 queue_tc_map[i][0] = i;
1484 queue_tc_map[i][1] = i;
1485 }
1486 queue_tc_map[i][0] = -1;
1487 queue_tc_map[i][1] = -1;
1488
1489 pdata->queue_tc_mapping = queue_tc_map;
1490
1491 queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1492 if (!queue_priority_map)
1493 return -ENOMEM;
1494
1495 for (i = 0; i < 3; i++) {
1496 queue_priority_map[i][0] = i;
1497 queue_priority_map[i][1] = i;
1498 }
1499 queue_priority_map[i][0] = -1;
1500 queue_priority_map[i][1] = -1;
1501
1502 pdata->queue_priority_mapping = queue_priority_map;
1503
1504 pdata->default_queue = 0;
1505
1506 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1507 if (prop)
1508 ret = edma_xbar_event_map(dev, node, pdata, sz);
1509
1510 return ret;
1511 }
1512
1513 static struct of_dma_filter_info edma_filter_info = {
1514 .filter_fn = edma_filter_fn,
1515 };
1516
1517 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1518 struct device_node *node)
1519 {
1520 struct edma_soc_info *info;
1521 int ret;
1522
1523 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1524 if (!info)
1525 return ERR_PTR(-ENOMEM);
1526
1527 ret = edma_of_parse_dt(dev, node, info);
1528 if (ret)
1529 return ERR_PTR(ret);
1530
1531 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1532 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1533 &edma_filter_info);
1534
1535 return info;
1536 }
1537 #else
1538 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1539 struct device_node *node)
1540 {
1541 return ERR_PTR(-ENOSYS);
1542 }
1543 #endif
1544
1545 static int edma_probe(struct platform_device *pdev)
1546 {
1547 struct edma_soc_info **info = pdev->dev.platform_data;
1548 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1549 s8 (*queue_priority_mapping)[2];
1550 s8 (*queue_tc_mapping)[2];
1551 int i, j, off, ln, found = 0;
1552 int status = -1;
1553 const s16 (*rsv_chans)[2];
1554 const s16 (*rsv_slots)[2];
1555 const s16 (*xbar_chans)[2];
1556 int irq[EDMA_MAX_CC] = {0, 0};
1557 int err_irq[EDMA_MAX_CC] = {0, 0};
1558 struct resource *r[EDMA_MAX_CC] = {NULL};
1559 struct resource res[EDMA_MAX_CC];
1560 char res_name[10];
1561 char irq_name[10];
1562 struct device_node *node = pdev->dev.of_node;
1563 struct device *dev = &pdev->dev;
1564 int ret;
1565
1566 if (node) {
1567 /* Check if this is a second instance registered */
1568 if (arch_num_cc) {
1569 dev_err(dev, "only one EDMA instance is supported via DT\n");
1570 return -ENODEV;
1571 }
1572
1573 ninfo[0] = edma_setup_info_from_dt(dev, node);
1574 if (IS_ERR(ninfo[0])) {
1575 dev_err(dev, "failed to get DT data\n");
1576 return PTR_ERR(ninfo[0]);
1577 }
1578
1579 info = ninfo;
1580 }
1581
1582 if (!info)
1583 return -ENODEV;
1584
1585 pm_runtime_enable(dev);
1586 ret = pm_runtime_get_sync(dev);
1587 if (ret < 0) {
1588 dev_err(dev, "pm_runtime_get_sync() failed\n");
1589 return ret;
1590 }
1591
1592 for (j = 0; j < EDMA_MAX_CC; j++) {
1593 if (!info[j]) {
1594 if (!found)
1595 return -ENODEV;
1596 break;
1597 }
1598 if (node) {
1599 ret = of_address_to_resource(node, j, &res[j]);
1600 if (!ret)
1601 r[j] = &res[j];
1602 } else {
1603 sprintf(res_name, "edma_cc%d", j);
1604 r[j] = platform_get_resource_byname(pdev,
1605 IORESOURCE_MEM,
1606 res_name);
1607 }
1608 if (!r[j]) {
1609 if (found)
1610 break;
1611 else
1612 return -ENODEV;
1613 } else {
1614 found = 1;
1615 }
1616
1617 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1618 if (IS_ERR(edmacc_regs_base[j]))
1619 return PTR_ERR(edmacc_regs_base[j]);
1620
1621 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1622 GFP_KERNEL);
1623 if (!edma_cc[j])
1624 return -ENOMEM;
1625
1626 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1627 EDMA_MAX_DMACH);
1628 edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
1629 EDMA_MAX_PARAMENTRY);
1630 edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
1631 EDMA_MAX_CC);
1632
1633 edma_cc[j]->default_queue = info[j]->default_queue;
1634
1635 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1636 edmacc_regs_base[j]);
1637
1638 for (i = 0; i < edma_cc[j]->num_slots; i++)
1639 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1640 &dummy_paramset, PARM_SIZE);
1641
1642 /* Mark all channels as unused */
1643 memset(edma_cc[j]->edma_unused, 0xff,
1644 sizeof(edma_cc[j]->edma_unused));
1645
1646 if (info[j]->rsv) {
1647
1648 /* Clear the reserved channels in unused list */
1649 rsv_chans = info[j]->rsv->rsv_chans;
1650 if (rsv_chans) {
1651 for (i = 0; rsv_chans[i][0] != -1; i++) {
1652 off = rsv_chans[i][0];
1653 ln = rsv_chans[i][1];
1654 clear_bits(off, ln,
1655 edma_cc[j]->edma_unused);
1656 }
1657 }
1658
1659 /* Set the reserved slots in inuse list */
1660 rsv_slots = info[j]->rsv->rsv_slots;
1661 if (rsv_slots) {
1662 for (i = 0; rsv_slots[i][0] != -1; i++) {
1663 off = rsv_slots[i][0];
1664 ln = rsv_slots[i][1];
1665 set_bits(off, ln,
1666 edma_cc[j]->edma_inuse);
1667 }
1668 }
1669 }
1670
1671 /* Clear the xbar mapped channels in unused list */
1672 xbar_chans = info[j]->xbar_chans;
1673 if (xbar_chans) {
1674 for (i = 0; xbar_chans[i][1] != -1; i++) {
1675 off = xbar_chans[i][1];
1676 clear_bits(off, 1,
1677 edma_cc[j]->edma_unused);
1678 }
1679 }
1680
1681 if (node) {
1682 irq[j] = irq_of_parse_and_map(node, 0);
1683 } else {
1684 sprintf(irq_name, "edma%d", j);
1685 irq[j] = platform_get_irq_byname(pdev, irq_name);
1686 }
1687 edma_cc[j]->irq_res_start = irq[j];
1688 status = devm_request_irq(&pdev->dev, irq[j],
1689 dma_irq_handler, 0, "edma",
1690 &pdev->dev);
1691 if (status < 0) {
1692 dev_dbg(&pdev->dev,
1693 "devm_request_irq %d failed --> %d\n",
1694 irq[j], status);
1695 return status;
1696 }
1697
1698 if (node) {
1699 err_irq[j] = irq_of_parse_and_map(node, 2);
1700 } else {
1701 sprintf(irq_name, "edma%d_err", j);
1702 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1703 }
1704 edma_cc[j]->irq_res_end = err_irq[j];
1705 status = devm_request_irq(&pdev->dev, err_irq[j],
1706 dma_ccerr_handler, 0,
1707 "edma_error", &pdev->dev);
1708 if (status < 0) {
1709 dev_dbg(&pdev->dev,
1710 "devm_request_irq %d failed --> %d\n",
1711 err_irq[j], status);
1712 return status;
1713 }
1714
1715 for (i = 0; i < edma_cc[j]->num_channels; i++)
1716 map_dmach_queue(j, i, info[j]->default_queue);
1717
1718 queue_tc_mapping = info[j]->queue_tc_mapping;
1719 queue_priority_mapping = info[j]->queue_priority_mapping;
1720
1721 /* Event queue to TC mapping */
1722 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1723 map_queue_tc(j, queue_tc_mapping[i][0],
1724 queue_tc_mapping[i][1]);
1725
1726 /* Event queue priority mapping */
1727 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1728 assign_priority_to_queue(j,
1729 queue_priority_mapping[i][0],
1730 queue_priority_mapping[i][1]);
1731
1732 /* Map the channel to param entry if channel mapping logic
1733 * exist
1734 */
1735 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1736 map_dmach_param(j);
1737
1738 for (i = 0; i < info[j]->n_region; i++) {
1739 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1740 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1741 edma_write_array(j, EDMA_QRAE, i, 0x0);
1742 }
1743 arch_num_cc++;
1744 }
1745
1746 return 0;
1747 }
1748
1749 static const struct of_device_id edma_of_ids[] = {
1750 { .compatible = "ti,edma3", },
1751 {}
1752 };
1753
1754 static struct platform_driver edma_driver = {
1755 .driver = {
1756 .name = "edma",
1757 .of_match_table = edma_of_ids,
1758 },
1759 .probe = edma_probe,
1760 };
1761
1762 static int __init edma_init(void)
1763 {
1764 return platform_driver_probe(&edma_driver, edma_probe);
1765 }
1766 arch_initcall(edma_init);
1767
Linux kernel - Deliverables
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