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ARM: common: edma: Remove unused functions
[deliverable/linux.git] / arch / arm / common / edma.c
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/of_irq.h>
34 #include <linux/pm_runtime.h>
35
36 #include <linux/platform_data/edma.h>
37
38 /* Offsets matching "struct edmacc_param" */
39 #define PARM_OPT 0x00
40 #define PARM_SRC 0x04
41 #define PARM_A_B_CNT 0x08
42 #define PARM_DST 0x0c
43 #define PARM_SRC_DST_BIDX 0x10
44 #define PARM_LINK_BCNTRLD 0x14
45 #define PARM_SRC_DST_CIDX 0x18
46 #define PARM_CCNT 0x1c
47
48 #define PARM_SIZE 0x20
49
50 /* Offsets for EDMA CC global channel registers and their shadows */
51 #define SH_ER 0x00 /* 64 bits */
52 #define SH_ECR 0x08 /* 64 bits */
53 #define SH_ESR 0x10 /* 64 bits */
54 #define SH_CER 0x18 /* 64 bits */
55 #define SH_EER 0x20 /* 64 bits */
56 #define SH_EECR 0x28 /* 64 bits */
57 #define SH_EESR 0x30 /* 64 bits */
58 #define SH_SER 0x38 /* 64 bits */
59 #define SH_SECR 0x40 /* 64 bits */
60 #define SH_IER 0x50 /* 64 bits */
61 #define SH_IECR 0x58 /* 64 bits */
62 #define SH_IESR 0x60 /* 64 bits */
63 #define SH_IPR 0x68 /* 64 bits */
64 #define SH_ICR 0x70 /* 64 bits */
65 #define SH_IEVAL 0x78
66 #define SH_QER 0x80
67 #define SH_QEER 0x84
68 #define SH_QEECR 0x88
69 #define SH_QEESR 0x8c
70 #define SH_QSER 0x90
71 #define SH_QSECR 0x94
72 #define SH_SIZE 0x200
73
74 /* Offsets for EDMA CC global registers */
75 #define EDMA_REV 0x0000
76 #define EDMA_CCCFG 0x0004
77 #define EDMA_QCHMAP 0x0200 /* 8 registers */
78 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
79 #define EDMA_QDMAQNUM 0x0260
80 #define EDMA_QUETCMAP 0x0280
81 #define EDMA_QUEPRI 0x0284
82 #define EDMA_EMR 0x0300 /* 64 bits */
83 #define EDMA_EMCR 0x0308 /* 64 bits */
84 #define EDMA_QEMR 0x0310
85 #define EDMA_QEMCR 0x0314
86 #define EDMA_CCERR 0x0318
87 #define EDMA_CCERRCLR 0x031c
88 #define EDMA_EEVAL 0x0320
89 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
90 #define EDMA_QRAE 0x0380 /* 4 registers */
91 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
92 #define EDMA_QSTAT 0x0600 /* 2 registers */
93 #define EDMA_QWMTHRA 0x0620
94 #define EDMA_QWMTHRB 0x0624
95 #define EDMA_CCSTAT 0x0640
96
97 #define EDMA_M 0x1000 /* global channel registers */
98 #define EDMA_ECR 0x1008
99 #define EDMA_ECRH 0x100C
100 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
101 #define EDMA_PARM 0x4000 /* 128 param entries */
102
103 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
104
105 #define EDMA_DCHMAP 0x0100 /* 64 registers */
106
107 /* CCCFG register */
108 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
109 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
110 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
111 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
112 #define CHMAP_EXIST BIT(24)
113
114 #define EDMA_MAX_DMACH 64
115 #define EDMA_MAX_PARAMENTRY 512
116
117 /*****************************************************************************/
118
119 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
120
121 static inline unsigned int edma_read(unsigned ctlr, int offset)
122 {
123 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
124 }
125
126 static inline void edma_write(unsigned ctlr, int offset, int val)
127 {
128 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
129 }
130 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
131 unsigned or)
132 {
133 unsigned val = edma_read(ctlr, offset);
134 val &= and;
135 val |= or;
136 edma_write(ctlr, offset, val);
137 }
138 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
139 {
140 unsigned val = edma_read(ctlr, offset);
141 val &= and;
142 edma_write(ctlr, offset, val);
143 }
144 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
145 {
146 unsigned val = edma_read(ctlr, offset);
147 val |= or;
148 edma_write(ctlr, offset, val);
149 }
150 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
151 {
152 return edma_read(ctlr, offset + (i << 2));
153 }
154 static inline void edma_write_array(unsigned ctlr, int offset, int i,
155 unsigned val)
156 {
157 edma_write(ctlr, offset + (i << 2), val);
158 }
159 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
160 unsigned and, unsigned or)
161 {
162 edma_modify(ctlr, offset + (i << 2), and, or);
163 }
164 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
165 {
166 edma_or(ctlr, offset + (i << 2), or);
167 }
168 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
169 unsigned or)
170 {
171 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
172 }
173 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
174 unsigned val)
175 {
176 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
177 }
178 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
179 {
180 return edma_read(ctlr, EDMA_SHADOW0 + offset);
181 }
182 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
183 int i)
184 {
185 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
186 }
187 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
188 {
189 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
190 }
191 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
192 unsigned val)
193 {
194 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
195 }
196 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
197 int param_no)
198 {
199 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
200 }
201 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
202 unsigned val)
203 {
204 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
205 }
206 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
207 unsigned and, unsigned or)
208 {
209 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
210 }
211 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
212 unsigned and)
213 {
214 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
215 }
216 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
217 unsigned or)
218 {
219 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
220 }
221
222 static inline void set_bits(int offset, int len, unsigned long *p)
223 {
224 for (; len > 0; len--)
225 set_bit(offset + (len - 1), p);
226 }
227
228 static inline void clear_bits(int offset, int len, unsigned long *p)
229 {
230 for (; len > 0; len--)
231 clear_bit(offset + (len - 1), p);
232 }
233
234 /*****************************************************************************/
235
236 /* actual number of DMA channels and slots on this silicon */
237 struct edma {
238 /* how many dma resources of each type */
239 unsigned num_channels;
240 unsigned num_region;
241 unsigned num_slots;
242 unsigned num_tc;
243 enum dma_event_q default_queue;
244
245 /* list of channels with no even trigger; terminated by "-1" */
246 const s8 *noevent;
247
248 struct edma_soc_info *info;
249
250 /* The edma_inuse bit for each PaRAM slot is clear unless the
251 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
252 */
253 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
254
255 /* The edma_unused bit for each channel is clear unless
256 * it is not being used on this platform. It uses a bit
257 * of SOC-specific initialization code.
258 */
259 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
260
261 unsigned irq_res_start;
262 unsigned irq_res_end;
263
264 struct dma_interrupt_data {
265 void (*callback)(unsigned channel, unsigned short ch_status,
266 void *data);
267 void *data;
268 } intr_data[EDMA_MAX_DMACH];
269 };
270
271 static struct edma *edma_cc[EDMA_MAX_CC];
272 static int arch_num_cc;
273
274 /* dummy param set used to (re)initialize parameter RAM slots */
275 static const struct edmacc_param dummy_paramset = {
276 .link_bcntrld = 0xffff,
277 .ccnt = 1,
278 };
279
280 static const struct of_device_id edma_of_ids[] = {
281 { .compatible = "ti,edma3", },
282 {}
283 };
284
285 /*****************************************************************************/
286
287 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
288 enum dma_event_q queue_no)
289 {
290 int bit = (ch_no & 0x7) * 4;
291
292 /* default to low priority queue */
293 if (queue_no == EVENTQ_DEFAULT)
294 queue_no = edma_cc[ctlr]->default_queue;
295
296 queue_no &= 7;
297 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
298 ~(0x7 << bit), queue_no << bit);
299 }
300
301 static void assign_priority_to_queue(unsigned ctlr, int queue_no,
302 int priority)
303 {
304 int bit = queue_no * 4;
305 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
306 ((priority & 0x7) << bit));
307 }
308
309 /**
310 * map_dmach_param - Maps channel number to param entry number
311 *
312 * This maps the dma channel number to param entry numberter. In
313 * other words using the DMA channel mapping registers a param entry
314 * can be mapped to any channel
315 *
316 * Callers are responsible for ensuring the channel mapping logic is
317 * included in that particular EDMA variant (Eg : dm646x)
318 *
319 */
320 static void map_dmach_param(unsigned ctlr)
321 {
322 int i;
323 for (i = 0; i < EDMA_MAX_DMACH; i++)
324 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
325 }
326
327 static inline void
328 setup_dma_interrupt(unsigned lch,
329 void (*callback)(unsigned channel, u16 ch_status, void *data),
330 void *data)
331 {
332 unsigned ctlr;
333
334 ctlr = EDMA_CTLR(lch);
335 lch = EDMA_CHAN_SLOT(lch);
336
337 if (!callback)
338 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
339 BIT(lch & 0x1f));
340
341 edma_cc[ctlr]->intr_data[lch].callback = callback;
342 edma_cc[ctlr]->intr_data[lch].data = data;
343
344 if (callback) {
345 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
346 BIT(lch & 0x1f));
347 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
348 BIT(lch & 0x1f));
349 }
350 }
351
352 static int irq2ctlr(int irq)
353 {
354 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
355 return 0;
356 else if (irq >= edma_cc[1]->irq_res_start &&
357 irq <= edma_cc[1]->irq_res_end)
358 return 1;
359
360 return -1;
361 }
362
363 /******************************************************************************
364 *
365 * DMA interrupt handler
366 *
367 *****************************************************************************/
368 static irqreturn_t dma_irq_handler(int irq, void *data)
369 {
370 int ctlr;
371 u32 sh_ier;
372 u32 sh_ipr;
373 u32 bank;
374
375 ctlr = irq2ctlr(irq);
376 if (ctlr < 0)
377 return IRQ_NONE;
378
379 dev_dbg(data, "dma_irq_handler\n");
380
381 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
382 if (!sh_ipr) {
383 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
384 if (!sh_ipr)
385 return IRQ_NONE;
386 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
387 bank = 1;
388 } else {
389 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
390 bank = 0;
391 }
392
393 do {
394 u32 slot;
395 u32 channel;
396
397 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
398
399 slot = __ffs(sh_ipr);
400 sh_ipr &= ~(BIT(slot));
401
402 if (sh_ier & BIT(slot)) {
403 channel = (bank << 5) | slot;
404 /* Clear the corresponding IPR bits */
405 edma_shadow0_write_array(ctlr, SH_ICR, bank,
406 BIT(slot));
407 if (edma_cc[ctlr]->intr_data[channel].callback)
408 edma_cc[ctlr]->intr_data[channel].callback(
409 EDMA_CTLR_CHAN(ctlr, channel),
410 EDMA_DMA_COMPLETE,
411 edma_cc[ctlr]->intr_data[channel].data);
412 }
413 } while (sh_ipr);
414
415 edma_shadow0_write(ctlr, SH_IEVAL, 1);
416 return IRQ_HANDLED;
417 }
418
419 /******************************************************************************
420 *
421 * DMA error interrupt handler
422 *
423 *****************************************************************************/
424 static irqreturn_t dma_ccerr_handler(int irq, void *data)
425 {
426 int i;
427 int ctlr;
428 unsigned int cnt = 0;
429
430 ctlr = irq2ctlr(irq);
431 if (ctlr < 0)
432 return IRQ_NONE;
433
434 dev_dbg(data, "dma_ccerr_handler\n");
435
436 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
437 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
438 (edma_read(ctlr, EDMA_QEMR) == 0) &&
439 (edma_read(ctlr, EDMA_CCERR) == 0))
440 return IRQ_NONE;
441
442 while (1) {
443 int j = -1;
444 if (edma_read_array(ctlr, EDMA_EMR, 0))
445 j = 0;
446 else if (edma_read_array(ctlr, EDMA_EMR, 1))
447 j = 1;
448 if (j >= 0) {
449 dev_dbg(data, "EMR%d %08x\n", j,
450 edma_read_array(ctlr, EDMA_EMR, j));
451 for (i = 0; i < 32; i++) {
452 int k = (j << 5) + i;
453 if (edma_read_array(ctlr, EDMA_EMR, j) &
454 BIT(i)) {
455 /* Clear the corresponding EMR bits */
456 edma_write_array(ctlr, EDMA_EMCR, j,
457 BIT(i));
458 /* Clear any SER */
459 edma_shadow0_write_array(ctlr, SH_SECR,
460 j, BIT(i));
461 if (edma_cc[ctlr]->intr_data[k].
462 callback) {
463 edma_cc[ctlr]->intr_data[k].
464 callback(
465 EDMA_CTLR_CHAN(ctlr, k),
466 EDMA_DMA_CC_ERROR,
467 edma_cc[ctlr]->intr_data
468 [k].data);
469 }
470 }
471 }
472 } else if (edma_read(ctlr, EDMA_QEMR)) {
473 dev_dbg(data, "QEMR %02x\n",
474 edma_read(ctlr, EDMA_QEMR));
475 for (i = 0; i < 8; i++) {
476 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
477 /* Clear the corresponding IPR bits */
478 edma_write(ctlr, EDMA_QEMCR, BIT(i));
479 edma_shadow0_write(ctlr, SH_QSECR,
480 BIT(i));
481
482 /* NOTE: not reported!! */
483 }
484 }
485 } else if (edma_read(ctlr, EDMA_CCERR)) {
486 dev_dbg(data, "CCERR %08x\n",
487 edma_read(ctlr, EDMA_CCERR));
488 /* FIXME: CCERR.BIT(16) ignored! much better
489 * to just write CCERRCLR with CCERR value...
490 */
491 for (i = 0; i < 8; i++) {
492 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
493 /* Clear the corresponding IPR bits */
494 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
495
496 /* NOTE: not reported!! */
497 }
498 }
499 }
500 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
501 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
502 (edma_read(ctlr, EDMA_QEMR) == 0) &&
503 (edma_read(ctlr, EDMA_CCERR) == 0))
504 break;
505 cnt++;
506 if (cnt > 10)
507 break;
508 }
509 edma_write(ctlr, EDMA_EEVAL, 1);
510 return IRQ_HANDLED;
511 }
512
513 static int prepare_unused_channel_list(struct device *dev, void *data)
514 {
515 struct platform_device *pdev = to_platform_device(dev);
516 int i, count, ctlr;
517 struct of_phandle_args dma_spec;
518
519 if (dev->of_node) {
520 count = of_property_count_strings(dev->of_node, "dma-names");
521 if (count < 0)
522 return 0;
523 for (i = 0; i < count; i++) {
524 if (of_parse_phandle_with_args(dev->of_node, "dmas",
525 "#dma-cells", i,
526 &dma_spec))
527 continue;
528
529 if (!of_match_node(edma_of_ids, dma_spec.np)) {
530 of_node_put(dma_spec.np);
531 continue;
532 }
533
534 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
535 edma_cc[0]->edma_unused);
536 of_node_put(dma_spec.np);
537 }
538 return 0;
539 }
540
541 /* For non-OF case */
542 for (i = 0; i < pdev->num_resources; i++) {
543 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
544 (int)pdev->resource[i].start >= 0) {
545 ctlr = EDMA_CTLR(pdev->resource[i].start);
546 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
547 edma_cc[ctlr]->edma_unused);
548 }
549 }
550
551 return 0;
552 }
553
554 /*-----------------------------------------------------------------------*/
555
556 static bool unused_chan_list_done;
557
558 /* Resource alloc/free: dma channels, parameter RAM slots */
559
560 /**
561 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
562 * @channel: specific channel to allocate; negative for "any unmapped channel"
563 * @callback: optional; to be issued on DMA completion or errors
564 * @data: passed to callback
565 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
566 * Controller (TC) executes requests using this channel. Use
567 * EVENTQ_DEFAULT unless you really need a high priority queue.
568 *
569 * This allocates a DMA channel and its associated parameter RAM slot.
570 * The parameter RAM is initialized to hold a dummy transfer.
571 *
572 * Normal use is to pass a specific channel number as @channel, to make
573 * use of hardware events mapped to that channel. When the channel will
574 * be used only for software triggering or event chaining, channels not
575 * mapped to hardware events (or mapped to unused events) are preferable.
576 *
577 * DMA transfers start from a channel using edma_start(), or by
578 * chaining. When the transfer described in that channel's parameter RAM
579 * slot completes, that slot's data may be reloaded through a link.
580 *
581 * DMA errors are only reported to the @callback associated with the
582 * channel driving that transfer, but transfer completion callbacks can
583 * be sent to another channel under control of the TCC field in
584 * the option word of the transfer's parameter RAM set. Drivers must not
585 * use DMA transfer completion callbacks for channels they did not allocate.
586 * (The same applies to TCC codes used in transfer chaining.)
587 *
588 * Returns the number of the channel, else negative errno.
589 */
590 int edma_alloc_channel(int channel,
591 void (*callback)(unsigned channel, u16 ch_status, void *data),
592 void *data,
593 enum dma_event_q eventq_no)
594 {
595 unsigned i, done = 0, ctlr = 0;
596 int ret = 0;
597
598 if (!unused_chan_list_done) {
599 /*
600 * Scan all the platform devices to find out the EDMA channels
601 * used and clear them in the unused list, making the rest
602 * available for ARM usage.
603 */
604 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
605 prepare_unused_channel_list);
606 if (ret < 0)
607 return ret;
608
609 unused_chan_list_done = true;
610 }
611
612 if (channel >= 0) {
613 ctlr = EDMA_CTLR(channel);
614 channel = EDMA_CHAN_SLOT(channel);
615 }
616
617 if (channel < 0) {
618 for (i = 0; i < arch_num_cc; i++) {
619 channel = 0;
620 for (;;) {
621 channel = find_next_bit(edma_cc[i]->edma_unused,
622 edma_cc[i]->num_channels,
623 channel);
624 if (channel == edma_cc[i]->num_channels)
625 break;
626 if (!test_and_set_bit(channel,
627 edma_cc[i]->edma_inuse)) {
628 done = 1;
629 ctlr = i;
630 break;
631 }
632 channel++;
633 }
634 if (done)
635 break;
636 }
637 if (!done)
638 return -ENOMEM;
639 } else if (channel >= edma_cc[ctlr]->num_channels) {
640 return -EINVAL;
641 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
642 return -EBUSY;
643 }
644
645 /* ensure access through shadow region 0 */
646 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
647
648 /* ensure no events are pending */
649 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
650 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
651 &dummy_paramset, PARM_SIZE);
652
653 if (callback)
654 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
655 callback, data);
656
657 map_dmach_queue(ctlr, channel, eventq_no);
658
659 return EDMA_CTLR_CHAN(ctlr, channel);
660 }
661 EXPORT_SYMBOL(edma_alloc_channel);
662
663
664 /**
665 * edma_free_channel - deallocate DMA channel
666 * @channel: dma channel returned from edma_alloc_channel()
667 *
668 * This deallocates the DMA channel and associated parameter RAM slot
669 * allocated by edma_alloc_channel().
670 *
671 * Callers are responsible for ensuring the channel is inactive, and
672 * will not be reactivated by linking, chaining, or software calls to
673 * edma_start().
674 */
675 void edma_free_channel(unsigned channel)
676 {
677 unsigned ctlr;
678
679 ctlr = EDMA_CTLR(channel);
680 channel = EDMA_CHAN_SLOT(channel);
681
682 if (channel >= edma_cc[ctlr]->num_channels)
683 return;
684
685 setup_dma_interrupt(channel, NULL, NULL);
686 /* REVISIT should probably take out of shadow region 0 */
687
688 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
689 &dummy_paramset, PARM_SIZE);
690 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
691 }
692 EXPORT_SYMBOL(edma_free_channel);
693
694 /**
695 * edma_alloc_slot - allocate DMA parameter RAM
696 * @slot: specific slot to allocate; negative for "any unused slot"
697 *
698 * This allocates a parameter RAM slot, initializing it to hold a
699 * dummy transfer. Slots allocated using this routine have not been
700 * mapped to a hardware DMA channel, and will normally be used by
701 * linking to them from a slot associated with a DMA channel.
702 *
703 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
704 * slots may be allocated on behalf of DSP firmware.
705 *
706 * Returns the number of the slot, else negative errno.
707 */
708 int edma_alloc_slot(unsigned ctlr, int slot)
709 {
710 if (!edma_cc[ctlr])
711 return -EINVAL;
712
713 if (slot >= 0)
714 slot = EDMA_CHAN_SLOT(slot);
715
716 if (slot < 0) {
717 slot = edma_cc[ctlr]->num_channels;
718 for (;;) {
719 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
720 edma_cc[ctlr]->num_slots, slot);
721 if (slot == edma_cc[ctlr]->num_slots)
722 return -ENOMEM;
723 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
724 break;
725 }
726 } else if (slot < edma_cc[ctlr]->num_channels ||
727 slot >= edma_cc[ctlr]->num_slots) {
728 return -EINVAL;
729 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
730 return -EBUSY;
731 }
732
733 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
734 &dummy_paramset, PARM_SIZE);
735
736 return EDMA_CTLR_CHAN(ctlr, slot);
737 }
738 EXPORT_SYMBOL(edma_alloc_slot);
739
740 /**
741 * edma_free_slot - deallocate DMA parameter RAM
742 * @slot: parameter RAM slot returned from edma_alloc_slot()
743 *
744 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
745 * Callers are responsible for ensuring the slot is inactive, and will
746 * not be activated.
747 */
748 void edma_free_slot(unsigned slot)
749 {
750 unsigned ctlr;
751
752 ctlr = EDMA_CTLR(slot);
753 slot = EDMA_CHAN_SLOT(slot);
754
755 if (slot < edma_cc[ctlr]->num_channels ||
756 slot >= edma_cc[ctlr]->num_slots)
757 return;
758
759 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
760 &dummy_paramset, PARM_SIZE);
761 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
762 }
763 EXPORT_SYMBOL(edma_free_slot);
764
765 /*-----------------------------------------------------------------------*/
766
767 /* Parameter RAM operations (i) -- read/write partial slots */
768
769 /**
770 * edma_get_position - returns the current transfer point
771 * @slot: parameter RAM slot being examined
772 * @dst: true selects the dest position, false the source
773 *
774 * Returns the position of the current active slot
775 */
776 dma_addr_t edma_get_position(unsigned slot, bool dst)
777 {
778 u32 offs, ctlr = EDMA_CTLR(slot);
779
780 slot = EDMA_CHAN_SLOT(slot);
781
782 offs = PARM_OFFSET(slot);
783 offs += dst ? PARM_DST : PARM_SRC;
784
785 return edma_read(ctlr, offs);
786 }
787
788 /**
789 * edma_link - link one parameter RAM slot to another
790 * @from: parameter RAM slot originating the link
791 * @to: parameter RAM slot which is the link target
792 *
793 * The originating slot should not be part of any active DMA transfer.
794 */
795 void edma_link(unsigned from, unsigned to)
796 {
797 unsigned ctlr_from, ctlr_to;
798
799 ctlr_from = EDMA_CTLR(from);
800 from = EDMA_CHAN_SLOT(from);
801 ctlr_to = EDMA_CTLR(to);
802 to = EDMA_CHAN_SLOT(to);
803
804 if (from >= edma_cc[ctlr_from]->num_slots)
805 return;
806 if (to >= edma_cc[ctlr_to]->num_slots)
807 return;
808 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
809 PARM_OFFSET(to));
810 }
811 EXPORT_SYMBOL(edma_link);
812
813 /*-----------------------------------------------------------------------*/
814
815 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
816
817 /**
818 * edma_write_slot - write parameter RAM data for slot
819 * @slot: number of parameter RAM slot being modified
820 * @param: data to be written into parameter RAM slot
821 *
822 * Use this to assign all parameters of a transfer at once. This
823 * allows more efficient setup of transfers than issuing multiple
824 * calls to set up those parameters in small pieces, and provides
825 * complete control over all transfer options.
826 */
827 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
828 {
829 unsigned ctlr;
830
831 ctlr = EDMA_CTLR(slot);
832 slot = EDMA_CHAN_SLOT(slot);
833
834 if (slot >= edma_cc[ctlr]->num_slots)
835 return;
836 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
837 PARM_SIZE);
838 }
839 EXPORT_SYMBOL(edma_write_slot);
840
841 /**
842 * edma_read_slot - read parameter RAM data from slot
843 * @slot: number of parameter RAM slot being copied
844 * @param: where to store copy of parameter RAM data
845 *
846 * Use this to read data from a parameter RAM slot, perhaps to
847 * save them as a template for later reuse.
848 */
849 void edma_read_slot(unsigned slot, struct edmacc_param *param)
850 {
851 unsigned ctlr;
852
853 ctlr = EDMA_CTLR(slot);
854 slot = EDMA_CHAN_SLOT(slot);
855
856 if (slot >= edma_cc[ctlr]->num_slots)
857 return;
858 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
859 PARM_SIZE);
860 }
861 EXPORT_SYMBOL(edma_read_slot);
862
863 /*-----------------------------------------------------------------------*/
864
865 /* Various EDMA channel control operations */
866
867 /**
868 * edma_pause - pause dma on a channel
869 * @channel: on which edma_start() has been called
870 *
871 * This temporarily disables EDMA hardware events on the specified channel,
872 * preventing them from triggering new transfers on its behalf
873 */
874 void edma_pause(unsigned channel)
875 {
876 unsigned ctlr;
877
878 ctlr = EDMA_CTLR(channel);
879 channel = EDMA_CHAN_SLOT(channel);
880
881 if (channel < edma_cc[ctlr]->num_channels) {
882 unsigned int mask = BIT(channel & 0x1f);
883
884 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
885 }
886 }
887 EXPORT_SYMBOL(edma_pause);
888
889 /**
890 * edma_resume - resumes dma on a paused channel
891 * @channel: on which edma_pause() has been called
892 *
893 * This re-enables EDMA hardware events on the specified channel.
894 */
895 void edma_resume(unsigned channel)
896 {
897 unsigned ctlr;
898
899 ctlr = EDMA_CTLR(channel);
900 channel = EDMA_CHAN_SLOT(channel);
901
902 if (channel < edma_cc[ctlr]->num_channels) {
903 unsigned int mask = BIT(channel & 0x1f);
904
905 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
906 }
907 }
908 EXPORT_SYMBOL(edma_resume);
909
910 int edma_trigger_channel(unsigned channel)
911 {
912 unsigned ctlr;
913 unsigned int mask;
914
915 ctlr = EDMA_CTLR(channel);
916 channel = EDMA_CHAN_SLOT(channel);
917 mask = BIT(channel & 0x1f);
918
919 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
920
921 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
922 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
923 return 0;
924 }
925 EXPORT_SYMBOL(edma_trigger_channel);
926
927 /**
928 * edma_start - start dma on a channel
929 * @channel: channel being activated
930 *
931 * Channels with event associations will be triggered by their hardware
932 * events, and channels without such associations will be triggered by
933 * software. (At this writing there is no interface for using software
934 * triggers except with channels that don't support hardware triggers.)
935 *
936 * Returns zero on success, else negative errno.
937 */
938 int edma_start(unsigned channel)
939 {
940 unsigned ctlr;
941
942 ctlr = EDMA_CTLR(channel);
943 channel = EDMA_CHAN_SLOT(channel);
944
945 if (channel < edma_cc[ctlr]->num_channels) {
946 int j = channel >> 5;
947 unsigned int mask = BIT(channel & 0x1f);
948
949 /* EDMA channels without event association */
950 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
951 pr_debug("EDMA: ESR%d %08x\n", j,
952 edma_shadow0_read_array(ctlr, SH_ESR, j));
953 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
954 return 0;
955 }
956
957 /* EDMA channel with event association */
958 pr_debug("EDMA: ER%d %08x\n", j,
959 edma_shadow0_read_array(ctlr, SH_ER, j));
960 /* Clear any pending event or error */
961 edma_write_array(ctlr, EDMA_ECR, j, mask);
962 edma_write_array(ctlr, EDMA_EMCR, j, mask);
963 /* Clear any SER */
964 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
965 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
966 pr_debug("EDMA: EER%d %08x\n", j,
967 edma_shadow0_read_array(ctlr, SH_EER, j));
968 return 0;
969 }
970
971 return -EINVAL;
972 }
973 EXPORT_SYMBOL(edma_start);
974
975 /**
976 * edma_stop - stops dma on the channel passed
977 * @channel: channel being deactivated
978 *
979 * When @lch is a channel, any active transfer is paused and
980 * all pending hardware events are cleared. The current transfer
981 * may not be resumed, and the channel's Parameter RAM should be
982 * reinitialized before being reused.
983 */
984 void edma_stop(unsigned channel)
985 {
986 unsigned ctlr;
987
988 ctlr = EDMA_CTLR(channel);
989 channel = EDMA_CHAN_SLOT(channel);
990
991 if (channel < edma_cc[ctlr]->num_channels) {
992 int j = channel >> 5;
993 unsigned int mask = BIT(channel & 0x1f);
994
995 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
996 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
997 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
998 edma_write_array(ctlr, EDMA_EMCR, j, mask);
999
1000 /* clear possibly pending completion interrupt */
1001 edma_shadow0_write_array(ctlr, SH_ICR, j, mask);
1002
1003 pr_debug("EDMA: EER%d %08x\n", j,
1004 edma_shadow0_read_array(ctlr, SH_EER, j));
1005
1006 /* REVISIT: consider guarding against inappropriate event
1007 * chaining by overwriting with dummy_paramset.
1008 */
1009 }
1010 }
1011 EXPORT_SYMBOL(edma_stop);
1012
1013 /******************************************************************************
1014 *
1015 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1016 * been removed before EDMA has finished.It is usedful for removable media.
1017 * Arguments:
1018 * ch_no - channel no
1019 *
1020 * Return: zero on success, or corresponding error no on failure
1021 *
1022 * FIXME this should not be needed ... edma_stop() should suffice.
1023 *
1024 *****************************************************************************/
1025
1026 void edma_clean_channel(unsigned channel)
1027 {
1028 unsigned ctlr;
1029
1030 ctlr = EDMA_CTLR(channel);
1031 channel = EDMA_CHAN_SLOT(channel);
1032
1033 if (channel < edma_cc[ctlr]->num_channels) {
1034 int j = (channel >> 5);
1035 unsigned int mask = BIT(channel & 0x1f);
1036
1037 pr_debug("EDMA: EMR%d %08x\n", j,
1038 edma_read_array(ctlr, EDMA_EMR, j));
1039 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1040 /* Clear the corresponding EMR bits */
1041 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1042 /* Clear any SER */
1043 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1044 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1045 }
1046 }
1047 EXPORT_SYMBOL(edma_clean_channel);
1048
1049 /*
1050 * edma_assign_channel_eventq - move given channel to desired eventq
1051 * Arguments:
1052 * channel - channel number
1053 * eventq_no - queue to move the channel
1054 *
1055 * Can be used to move a channel to a selected event queue.
1056 */
1057 void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
1058 {
1059 unsigned ctlr;
1060
1061 ctlr = EDMA_CTLR(channel);
1062 channel = EDMA_CHAN_SLOT(channel);
1063
1064 if (channel >= edma_cc[ctlr]->num_channels)
1065 return;
1066
1067 /* default to low priority queue */
1068 if (eventq_no == EVENTQ_DEFAULT)
1069 eventq_no = edma_cc[ctlr]->default_queue;
1070 if (eventq_no >= edma_cc[ctlr]->num_tc)
1071 return;
1072
1073 map_dmach_queue(ctlr, channel, eventq_no);
1074 }
1075 EXPORT_SYMBOL(edma_assign_channel_eventq);
1076
1077 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1078 struct edma *edma_cc, int cc_id)
1079 {
1080 int i;
1081 u32 value, cccfg;
1082 s8 (*queue_priority_map)[2];
1083
1084 /* Decode the eDMA3 configuration from CCCFG register */
1085 cccfg = edma_read(cc_id, EDMA_CCCFG);
1086
1087 value = GET_NUM_REGN(cccfg);
1088 edma_cc->num_region = BIT(value);
1089
1090 value = GET_NUM_DMACH(cccfg);
1091 edma_cc->num_channels = BIT(value + 1);
1092
1093 value = GET_NUM_PAENTRY(cccfg);
1094 edma_cc->num_slots = BIT(value + 4);
1095
1096 value = GET_NUM_EVQUE(cccfg);
1097 edma_cc->num_tc = value + 1;
1098
1099 dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
1100 cccfg);
1101 dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1102 dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1103 dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
1104 dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
1105
1106 /* Nothing need to be done if queue priority is provided */
1107 if (pdata->queue_priority_mapping)
1108 return 0;
1109
1110 /*
1111 * Configure TC/queue priority as follows:
1112 * Q0 - priority 0
1113 * Q1 - priority 1
1114 * Q2 - priority 2
1115 * ...
1116 * The meaning of priority numbers: 0 highest priority, 7 lowest
1117 * priority. So Q0 is the highest priority queue and the last queue has
1118 * the lowest priority.
1119 */
1120 queue_priority_map = devm_kzalloc(dev,
1121 (edma_cc->num_tc + 1) * sizeof(s8),
1122 GFP_KERNEL);
1123 if (!queue_priority_map)
1124 return -ENOMEM;
1125
1126 for (i = 0; i < edma_cc->num_tc; i++) {
1127 queue_priority_map[i][0] = i;
1128 queue_priority_map[i][1] = i;
1129 }
1130 queue_priority_map[i][0] = -1;
1131 queue_priority_map[i][1] = -1;
1132
1133 pdata->queue_priority_mapping = queue_priority_map;
1134 /* Default queue has the lowest priority */
1135 pdata->default_queue = i - 1;
1136
1137 return 0;
1138 }
1139
1140 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1141
1142 static int edma_xbar_event_map(struct device *dev, struct device_node *node,
1143 struct edma_soc_info *pdata, size_t sz)
1144 {
1145 const char pname[] = "ti,edma-xbar-event-map";
1146 struct resource res;
1147 void __iomem *xbar;
1148 s16 (*xbar_chans)[2];
1149 size_t nelm = sz / sizeof(s16);
1150 u32 shift, offset, mux;
1151 int ret, i;
1152
1153 xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
1154 if (!xbar_chans)
1155 return -ENOMEM;
1156
1157 ret = of_address_to_resource(node, 1, &res);
1158 if (ret)
1159 return -ENOMEM;
1160
1161 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1162 if (!xbar)
1163 return -ENOMEM;
1164
1165 ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
1166 if (ret)
1167 return -EIO;
1168
1169 /* Invalidate last entry for the other user of this mess */
1170 nelm >>= 1;
1171 xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
1172
1173 for (i = 0; i < nelm; i++) {
1174 shift = (xbar_chans[i][1] & 0x03) << 3;
1175 offset = xbar_chans[i][1] & 0xfffffffc;
1176 mux = readl(xbar + offset);
1177 mux &= ~(0xff << shift);
1178 mux |= xbar_chans[i][0] << shift;
1179 writel(mux, (xbar + offset));
1180 }
1181
1182 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
1183 return 0;
1184 }
1185
1186 static int edma_of_parse_dt(struct device *dev,
1187 struct device_node *node,
1188 struct edma_soc_info *pdata)
1189 {
1190 int ret = 0;
1191 struct property *prop;
1192 size_t sz;
1193 struct edma_rsv_info *rsv_info;
1194
1195 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1196 if (!rsv_info)
1197 return -ENOMEM;
1198 pdata->rsv = rsv_info;
1199
1200 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1201 if (prop)
1202 ret = edma_xbar_event_map(dev, node, pdata, sz);
1203
1204 return ret;
1205 }
1206
1207 static struct of_dma_filter_info edma_filter_info = {
1208 .filter_fn = edma_filter_fn,
1209 };
1210
1211 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1212 struct device_node *node)
1213 {
1214 struct edma_soc_info *info;
1215 int ret;
1216
1217 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1218 if (!info)
1219 return ERR_PTR(-ENOMEM);
1220
1221 ret = edma_of_parse_dt(dev, node, info);
1222 if (ret)
1223 return ERR_PTR(ret);
1224
1225 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1226 dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
1227 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1228 &edma_filter_info);
1229
1230 return info;
1231 }
1232 #else
1233 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1234 struct device_node *node)
1235 {
1236 return ERR_PTR(-ENOSYS);
1237 }
1238 #endif
1239
1240 static int edma_probe(struct platform_device *pdev)
1241 {
1242 struct edma_soc_info **info = pdev->dev.platform_data;
1243 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1244 s8 (*queue_priority_mapping)[2];
1245 int i, j, off, ln, found = 0;
1246 int status = -1;
1247 const s16 (*rsv_chans)[2];
1248 const s16 (*rsv_slots)[2];
1249 const s16 (*xbar_chans)[2];
1250 int irq[EDMA_MAX_CC] = {0, 0};
1251 int err_irq[EDMA_MAX_CC] = {0, 0};
1252 struct resource *r[EDMA_MAX_CC] = {NULL};
1253 struct resource res[EDMA_MAX_CC];
1254 char res_name[10];
1255 struct device_node *node = pdev->dev.of_node;
1256 struct device *dev = &pdev->dev;
1257 int ret;
1258 struct platform_device_info edma_dev_info = {
1259 .name = "edma-dma-engine",
1260 .dma_mask = DMA_BIT_MASK(32),
1261 .parent = &pdev->dev,
1262 };
1263
1264 if (node) {
1265 /* Check if this is a second instance registered */
1266 if (arch_num_cc) {
1267 dev_err(dev, "only one EDMA instance is supported via DT\n");
1268 return -ENODEV;
1269 }
1270
1271 ninfo[0] = edma_setup_info_from_dt(dev, node);
1272 if (IS_ERR(ninfo[0])) {
1273 dev_err(dev, "failed to get DT data\n");
1274 return PTR_ERR(ninfo[0]);
1275 }
1276
1277 info = ninfo;
1278 }
1279
1280 if (!info)
1281 return -ENODEV;
1282
1283 pm_runtime_enable(dev);
1284 ret = pm_runtime_get_sync(dev);
1285 if (ret < 0) {
1286 dev_err(dev, "pm_runtime_get_sync() failed\n");
1287 return ret;
1288 }
1289
1290 for (j = 0; j < EDMA_MAX_CC; j++) {
1291 if (!info[j]) {
1292 if (!found)
1293 return -ENODEV;
1294 break;
1295 }
1296 if (node) {
1297 ret = of_address_to_resource(node, j, &res[j]);
1298 if (!ret)
1299 r[j] = &res[j];
1300 } else {
1301 sprintf(res_name, "edma_cc%d", j);
1302 r[j] = platform_get_resource_byname(pdev,
1303 IORESOURCE_MEM,
1304 res_name);
1305 }
1306 if (!r[j]) {
1307 if (found)
1308 break;
1309 else
1310 return -ENODEV;
1311 } else {
1312 found = 1;
1313 }
1314
1315 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1316 if (IS_ERR(edmacc_regs_base[j]))
1317 return PTR_ERR(edmacc_regs_base[j]);
1318
1319 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1320 GFP_KERNEL);
1321 if (!edma_cc[j])
1322 return -ENOMEM;
1323
1324 /* Get eDMA3 configuration from IP */
1325 ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
1326 if (ret)
1327 return ret;
1328
1329 edma_cc[j]->default_queue = info[j]->default_queue;
1330
1331 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1332 edmacc_regs_base[j]);
1333
1334 for (i = 0; i < edma_cc[j]->num_slots; i++)
1335 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1336 &dummy_paramset, PARM_SIZE);
1337
1338 /* Mark all channels as unused */
1339 memset(edma_cc[j]->edma_unused, 0xff,
1340 sizeof(edma_cc[j]->edma_unused));
1341
1342 if (info[j]->rsv) {
1343
1344 /* Clear the reserved channels in unused list */
1345 rsv_chans = info[j]->rsv->rsv_chans;
1346 if (rsv_chans) {
1347 for (i = 0; rsv_chans[i][0] != -1; i++) {
1348 off = rsv_chans[i][0];
1349 ln = rsv_chans[i][1];
1350 clear_bits(off, ln,
1351 edma_cc[j]->edma_unused);
1352 }
1353 }
1354
1355 /* Set the reserved slots in inuse list */
1356 rsv_slots = info[j]->rsv->rsv_slots;
1357 if (rsv_slots) {
1358 for (i = 0; rsv_slots[i][0] != -1; i++) {
1359 off = rsv_slots[i][0];
1360 ln = rsv_slots[i][1];
1361 set_bits(off, ln,
1362 edma_cc[j]->edma_inuse);
1363 }
1364 }
1365 }
1366
1367 /* Clear the xbar mapped channels in unused list */
1368 xbar_chans = info[j]->xbar_chans;
1369 if (xbar_chans) {
1370 for (i = 0; xbar_chans[i][1] != -1; i++) {
1371 off = xbar_chans[i][1];
1372 clear_bits(off, 1,
1373 edma_cc[j]->edma_unused);
1374 }
1375 }
1376
1377 if (node) {
1378 irq[j] = irq_of_parse_and_map(node, 0);
1379 err_irq[j] = irq_of_parse_and_map(node, 2);
1380 } else {
1381 char irq_name[10];
1382
1383 sprintf(irq_name, "edma%d", j);
1384 irq[j] = platform_get_irq_byname(pdev, irq_name);
1385
1386 sprintf(irq_name, "edma%d_err", j);
1387 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1388 }
1389 edma_cc[j]->irq_res_start = irq[j];
1390 edma_cc[j]->irq_res_end = err_irq[j];
1391
1392 status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
1393 "edma", dev);
1394 if (status < 0) {
1395 dev_dbg(&pdev->dev,
1396 "devm_request_irq %d failed --> %d\n",
1397 irq[j], status);
1398 return status;
1399 }
1400
1401 status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
1402 "edma_error", dev);
1403 if (status < 0) {
1404 dev_dbg(&pdev->dev,
1405 "devm_request_irq %d failed --> %d\n",
1406 err_irq[j], status);
1407 return status;
1408 }
1409
1410 for (i = 0; i < edma_cc[j]->num_channels; i++)
1411 map_dmach_queue(j, i, info[j]->default_queue);
1412
1413 queue_priority_mapping = info[j]->queue_priority_mapping;
1414
1415 /* Event queue priority mapping */
1416 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1417 assign_priority_to_queue(j,
1418 queue_priority_mapping[i][0],
1419 queue_priority_mapping[i][1]);
1420
1421 /* Map the channel to param entry if channel mapping logic
1422 * exist
1423 */
1424 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1425 map_dmach_param(j);
1426
1427 for (i = 0; i < edma_cc[j]->num_region; i++) {
1428 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1429 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1430 edma_write_array(j, EDMA_QRAE, i, 0x0);
1431 }
1432 edma_cc[j]->info = info[j];
1433 arch_num_cc++;
1434
1435 edma_dev_info.id = j;
1436 platform_device_register_full(&edma_dev_info);
1437 }
1438
1439 return 0;
1440 }
1441
1442 #ifdef CONFIG_PM_SLEEP
1443 static int edma_pm_resume(struct device *dev)
1444 {
1445 int i, j;
1446
1447 for (j = 0; j < arch_num_cc; j++) {
1448 struct edma *cc = edma_cc[j];
1449
1450 s8 (*queue_priority_mapping)[2];
1451
1452 queue_priority_mapping = cc->info->queue_priority_mapping;
1453
1454 /* Event queue priority mapping */
1455 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1456 assign_priority_to_queue(j,
1457 queue_priority_mapping[i][0],
1458 queue_priority_mapping[i][1]);
1459
1460 /*
1461 * Map the channel to param entry if channel mapping logic
1462 * exist
1463 */
1464 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1465 map_dmach_param(j);
1466
1467 for (i = 0; i < cc->num_channels; i++) {
1468 if (test_bit(i, cc->edma_inuse)) {
1469 /* ensure access through shadow region 0 */
1470 edma_or_array2(j, EDMA_DRAE, 0, i >> 5,
1471 BIT(i & 0x1f));
1472
1473 setup_dma_interrupt(i,
1474 cc->intr_data[i].callback,
1475 cc->intr_data[i].data);
1476 }
1477 }
1478 }
1479
1480 return 0;
1481 }
1482 #endif
1483
1484 static const struct dev_pm_ops edma_pm_ops = {
1485 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
1486 };
1487
1488 static struct platform_driver edma_driver = {
1489 .driver = {
1490 .name = "edma",
1491 .pm = &edma_pm_ops,
1492 .of_match_table = edma_of_ids,
1493 },
1494 .probe = edma_probe,
1495 };
1496
1497 static int __init edma_init(void)
1498 {
1499 return platform_driver_probe(&edma_driver, edma_probe);
1500 }
1501 arch_initcall(edma_init);
1502
Linux kernel - Deliverables
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