2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpumask.h>
33 #include <asm/mach/irq.h>
34 #include <asm/hardware/gic.h>
36 static DEFINE_SPINLOCK(irq_controller_lock
);
38 struct gic_chip_data
{
39 unsigned int irq_offset
;
40 void __iomem
*dist_base
;
41 void __iomem
*cpu_base
;
48 static struct gic_chip_data gic_data
[MAX_GIC_NR
];
50 static inline void __iomem
*gic_dist_base(unsigned int irq
)
52 struct gic_chip_data
*gic_data
= get_irq_chip_data(irq
);
53 return gic_data
->dist_base
;
56 static inline void __iomem
*gic_cpu_base(unsigned int irq
)
58 struct gic_chip_data
*gic_data
= get_irq_chip_data(irq
);
59 return gic_data
->cpu_base
;
62 static inline unsigned int gic_irq(unsigned int irq
)
64 struct gic_chip_data
*gic_data
= get_irq_chip_data(irq
);
65 return irq
- gic_data
->irq_offset
;
69 * Routines to acknowledge, disable and enable interrupts
71 static void gic_ack_irq(unsigned int irq
)
74 spin_lock(&irq_controller_lock
);
75 writel(gic_irq(irq
), gic_cpu_base(irq
) + GIC_CPU_EOI
);
76 spin_unlock(&irq_controller_lock
);
79 static void gic_mask_irq(unsigned int irq
)
81 u32 mask
= 1 << (irq
% 32);
83 spin_lock(&irq_controller_lock
);
84 writel(mask
, gic_dist_base(irq
) + GIC_DIST_ENABLE_CLEAR
+ (gic_irq(irq
) / 32) * 4);
85 spin_unlock(&irq_controller_lock
);
88 static void gic_unmask_irq(unsigned int irq
)
90 u32 mask
= 1 << (irq
% 32);
92 spin_lock(&irq_controller_lock
);
93 writel(mask
, gic_dist_base(irq
) + GIC_DIST_ENABLE_SET
+ (gic_irq(irq
) / 32) * 4);
94 spin_unlock(&irq_controller_lock
);
97 static int gic_set_type(unsigned int irq
, unsigned int type
)
99 void __iomem
*base
= gic_dist_base(irq
);
100 unsigned int gicirq
= gic_irq(irq
);
101 u32 enablemask
= 1 << (gicirq
% 32);
102 u32 enableoff
= (gicirq
/ 32) * 4;
103 u32 confmask
= 0x2 << ((gicirq
% 16) * 2);
104 u32 confoff
= (gicirq
/ 16) * 4;
105 bool enabled
= false;
108 /* Interrupt configuration for SGIs can't be changed */
112 if (type
!= IRQ_TYPE_LEVEL_HIGH
&& type
!= IRQ_TYPE_EDGE_RISING
)
115 spin_lock(&irq_controller_lock
);
117 val
= readl(base
+ GIC_DIST_CONFIG
+ confoff
);
118 if (type
== IRQ_TYPE_LEVEL_HIGH
)
120 else if (type
== IRQ_TYPE_EDGE_RISING
)
124 * As recommended by the spec, disable the interrupt before changing
127 if (readl(base
+ GIC_DIST_ENABLE_SET
+ enableoff
) & enablemask
) {
128 writel(enablemask
, base
+ GIC_DIST_ENABLE_CLEAR
+ enableoff
);
132 writel(val
, base
+ GIC_DIST_CONFIG
+ confoff
);
135 writel(enablemask
, base
+ GIC_DIST_ENABLE_SET
+ enableoff
);
137 spin_unlock(&irq_controller_lock
);
143 static int gic_set_cpu(unsigned int irq
, const struct cpumask
*mask_val
)
145 void __iomem
*reg
= gic_dist_base(irq
) + GIC_DIST_TARGET
+ (gic_irq(irq
) & ~3);
146 unsigned int shift
= (irq
% 4) * 8;
147 unsigned int cpu
= cpumask_first(mask_val
);
149 struct irq_desc
*desc
;
151 spin_lock(&irq_controller_lock
);
152 desc
= irq_to_desc(irq
);
154 spin_unlock(&irq_controller_lock
);
158 val
= readl(reg
) & ~(0xff << shift
);
159 val
|= 1 << (cpu
+ shift
);
161 spin_unlock(&irq_controller_lock
);
167 static void gic_handle_cascade_irq(unsigned int irq
, struct irq_desc
*desc
)
169 struct gic_chip_data
*chip_data
= get_irq_data(irq
);
170 struct irq_chip
*chip
= get_irq_chip(irq
);
171 unsigned int cascade_irq
, gic_irq
;
172 unsigned long status
;
174 /* primary controller ack'ing */
177 spin_lock(&irq_controller_lock
);
178 status
= readl(chip_data
->cpu_base
+ GIC_CPU_INTACK
);
179 spin_unlock(&irq_controller_lock
);
181 gic_irq
= (status
& 0x3ff);
185 cascade_irq
= gic_irq
+ chip_data
->irq_offset
;
186 if (unlikely(gic_irq
< 32 || gic_irq
> 1020 || cascade_irq
>= NR_IRQS
))
187 do_bad_IRQ(cascade_irq
, desc
);
189 generic_handle_irq(cascade_irq
);
192 /* primary controller unmasking */
196 static struct irq_chip gic_chip
= {
199 .mask
= gic_mask_irq
,
200 .unmask
= gic_unmask_irq
,
201 .set_type
= gic_set_type
,
203 .set_affinity
= gic_set_cpu
,
207 void __init
gic_cascade_irq(unsigned int gic_nr
, unsigned int irq
)
209 if (gic_nr
>= MAX_GIC_NR
)
211 if (set_irq_data(irq
, &gic_data
[gic_nr
]) != 0)
213 set_irq_chained_handler(irq
, gic_handle_cascade_irq
);
216 void __init
gic_dist_init(unsigned int gic_nr
, void __iomem
*base
,
217 unsigned int irq_start
)
219 unsigned int gic_irqs
, irq_limit
, i
;
220 u32 cpumask
= 1 << smp_processor_id();
222 if (gic_nr
>= MAX_GIC_NR
)
225 cpumask
|= cpumask
<< 8;
226 cpumask
|= cpumask
<< 16;
228 gic_data
[gic_nr
].dist_base
= base
;
229 gic_data
[gic_nr
].irq_offset
= (irq_start
- 1) & ~31;
231 writel(0, base
+ GIC_DIST_CTRL
);
234 * Find out how many interrupts are supported.
235 * The GIC only supports up to 1020 interrupt sources.
237 gic_irqs
= readl(base
+ GIC_DIST_CTR
) & 0x1f;
238 gic_irqs
= (gic_irqs
+ 1) * 32;
243 * Set all global interrupts to be level triggered, active low.
245 for (i
= 32; i
< gic_irqs
; i
+= 16)
246 writel(0, base
+ GIC_DIST_CONFIG
+ i
* 4 / 16);
249 * Set all global interrupts to this CPU only.
251 for (i
= 32; i
< gic_irqs
; i
+= 4)
252 writel(cpumask
, base
+ GIC_DIST_TARGET
+ i
* 4 / 4);
255 * Set priority on all global interrupts.
257 for (i
= 32; i
< gic_irqs
; i
+= 4)
258 writel(0xa0a0a0a0, base
+ GIC_DIST_PRI
+ i
* 4 / 4);
261 * Disable all interrupts. Leave the PPI and SGIs alone
262 * as these enables are banked registers.
264 for (i
= 32; i
< gic_irqs
; i
+= 32)
265 writel(0xffffffff, base
+ GIC_DIST_ENABLE_CLEAR
+ i
* 4 / 32);
268 * Limit number of interrupts registered to the platform maximum
270 irq_limit
= gic_data
[gic_nr
].irq_offset
+ gic_irqs
;
271 if (WARN_ON(irq_limit
> NR_IRQS
))
275 * Setup the Linux IRQ subsystem.
277 for (i
= irq_start
; i
< irq_limit
; i
++) {
278 set_irq_chip(i
, &gic_chip
);
279 set_irq_chip_data(i
, &gic_data
[gic_nr
]);
280 set_irq_handler(i
, handle_level_irq
);
281 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
284 writel(1, base
+ GIC_DIST_CTRL
);
287 void __cpuinit
gic_cpu_init(unsigned int gic_nr
, void __iomem
*base
)
289 void __iomem
*dist_base
;
292 if (gic_nr
>= MAX_GIC_NR
)
295 dist_base
= gic_data
[gic_nr
].dist_base
;
298 gic_data
[gic_nr
].cpu_base
= base
;
301 * Deal with the banked PPI and SGI interrupts - disable all
302 * PPI interrupts, ensure all SGI interrupts are enabled.
304 writel(0xffff0000, dist_base
+ GIC_DIST_ENABLE_CLEAR
);
305 writel(0x0000ffff, dist_base
+ GIC_DIST_ENABLE_SET
);
308 * Set priority on PPI and SGI interrupts
310 for (i
= 0; i
< 32; i
+= 4)
311 writel(0xa0a0a0a0, dist_base
+ GIC_DIST_PRI
+ i
* 4 / 4);
313 writel(0xf0, base
+ GIC_CPU_PRIMASK
);
314 writel(1, base
+ GIC_CPU_CTRL
);
318 void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
320 unsigned long map
= *cpus_addr(*mask
);
322 /* this always happens on GIC0 */
323 writel(map
<< 16 | irq
, gic_data
[0].dist_base
+ GIC_DIST_SOFTINT
);
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