1 #ifndef __ASM_ARM_CPUTYPE_H
2 #define __ASM_ARM_CPUTYPE_H
4 #include <linux/stringify.h>
5 #include <linux/kernel.h>
8 #define CPUID_CACHETYPE 1
10 #define CPUID_TLBTYPE 3
13 #define CPUID_REVIDR 6
16 #define CPUID_EXT_PFR0 0x40
17 #define CPUID_EXT_PFR1 0x44
18 #define CPUID_EXT_DFR0 0x48
19 #define CPUID_EXT_AFR0 0x4c
20 #define CPUID_EXT_MMFR0 0x50
21 #define CPUID_EXT_MMFR1 0x54
22 #define CPUID_EXT_MMFR2 0x58
23 #define CPUID_EXT_MMFR3 0x5c
24 #define CPUID_EXT_ISAR0 0x60
25 #define CPUID_EXT_ISAR1 0x64
26 #define CPUID_EXT_ISAR2 0x68
27 #define CPUID_EXT_ISAR3 0x6c
28 #define CPUID_EXT_ISAR4 0x70
29 #define CPUID_EXT_ISAR5 0x74
31 #define CPUID_EXT_PFR0 "c1, 0"
32 #define CPUID_EXT_PFR1 "c1, 1"
33 #define CPUID_EXT_DFR0 "c1, 2"
34 #define CPUID_EXT_AFR0 "c1, 3"
35 #define CPUID_EXT_MMFR0 "c1, 4"
36 #define CPUID_EXT_MMFR1 "c1, 5"
37 #define CPUID_EXT_MMFR2 "c1, 6"
38 #define CPUID_EXT_MMFR3 "c1, 7"
39 #define CPUID_EXT_ISAR0 "c2, 0"
40 #define CPUID_EXT_ISAR1 "c2, 1"
41 #define CPUID_EXT_ISAR2 "c2, 2"
42 #define CPUID_EXT_ISAR3 "c2, 3"
43 #define CPUID_EXT_ISAR4 "c2, 4"
44 #define CPUID_EXT_ISAR5 "c2, 5"
47 #define MPIDR_SMP_BITMASK (0x3 << 30)
48 #define MPIDR_SMP_VALUE (0x2 << 30)
50 #define MPIDR_MT_BITMASK (0x1 << 24)
52 #define MPIDR_HWID_BITMASK 0xFFFFFF
54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
56 #define MPIDR_LEVEL_BITS 8
57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
59 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
60 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
62 #define ARM_CPU_IMP_ARM 0x41
63 #define ARM_CPU_IMP_DEC 0x44
64 #define ARM_CPU_IMP_INTEL 0x69
66 /* ARM implemented processors */
67 #define ARM_CPU_PART_ARM1136 0x4100b360
68 #define ARM_CPU_PART_ARM1156 0x4100b560
69 #define ARM_CPU_PART_ARM1176 0x4100b760
70 #define ARM_CPU_PART_ARM11MPCORE 0x4100b020
71 #define ARM_CPU_PART_CORTEX_A8 0x4100c080
72 #define ARM_CPU_PART_CORTEX_A9 0x4100c090
73 #define ARM_CPU_PART_CORTEX_A5 0x4100c050
74 #define ARM_CPU_PART_CORTEX_A7 0x4100c070
75 #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
76 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
77 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
78 #define ARM_CPU_PART_MASK 0xff00fff0
80 /* DEC implemented cores */
81 #define ARM_CPU_PART_SA1100 0x4400a110
83 /* Intel implemented cores */
84 #define ARM_CPU_PART_SA1110 0x6900b110
85 #define ARM_CPU_REV_SA1110_A0 0
86 #define ARM_CPU_REV_SA1110_B0 4
87 #define ARM_CPU_REV_SA1110_B1 5
88 #define ARM_CPU_REV_SA1110_B2 6
89 #define ARM_CPU_REV_SA1110_B4 8
91 #define ARM_CPU_XSCALE_ARCH_MASK 0xe000
92 #define ARM_CPU_XSCALE_ARCH_V1 0x2000
93 #define ARM_CPU_XSCALE_ARCH_V2 0x4000
94 #define ARM_CPU_XSCALE_ARCH_V3 0x6000
96 extern unsigned int processor_id
;
98 #ifdef CONFIG_CPU_CP15
99 #define read_cpuid(reg) \
101 unsigned int __val; \
102 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
110 * The memory clobber prevents gcc 4.5 from reordering the mrc before
111 * any is_smp() tests, which can cause undefined instruction aborts on
112 * ARM1136 r0 due to the missing extended CP15 registers.
114 #define read_cpuid_ext(ext_reg) \
116 unsigned int __val; \
117 asm("mrc p15, 0, %0, c0, " ext_reg \
124 #elif defined(CONFIG_CPU_V7M)
129 #define read_cpuid(reg) \
135 static inline unsigned int __attribute_const__
read_cpuid_ext(unsigned offset
)
137 return readl(BASEADDR_V7M_SCB
+ offset
);
140 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
143 * read_cpuid and read_cpuid_ext should only ever be called on machines that
144 * have cp15 so warn on other usages.
146 #define read_cpuid(reg) \
152 #define read_cpuid_ext(reg) read_cpuid(reg)
154 #endif /* ifdef CONFIG_CPU_CP15 / else */
156 #ifdef CONFIG_CPU_CP15
158 * The CPU ID never changes at run time, so we might as well tell the
159 * compiler that it's constant. Use this function to read the CPU ID
160 * rather than directly reading processor_id or read_cpuid() directly.
162 static inline unsigned int __attribute_const__
read_cpuid_id(void)
164 return read_cpuid(CPUID_ID
);
167 static inline unsigned int __attribute_const__
read_cpuid_cachetype(void)
169 return read_cpuid(CPUID_CACHETYPE
);
172 #elif defined(CONFIG_CPU_V7M)
174 static inline unsigned int __attribute_const__
read_cpuid_id(void)
176 return readl(BASEADDR_V7M_SCB
+ V7M_SCB_CPUID
);
179 static inline unsigned int __attribute_const__
read_cpuid_cachetype(void)
181 return readl(BASEADDR_V7M_SCB
+ V7M_SCB_CTR
);
184 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
186 static inline unsigned int __attribute_const__
read_cpuid_id(void)
191 #endif /* ifdef CONFIG_CPU_CP15 / else */
193 static inline unsigned int __attribute_const__
read_cpuid_implementor(void)
195 return (read_cpuid_id() & 0xFF000000) >> 24;
198 static inline unsigned int __attribute_const__
read_cpuid_revision(void)
200 return read_cpuid_id() & 0x0000000f;
204 * The CPU part number is meaningless without referring to the CPU
205 * implementer: implementers are free to define their own part numbers
206 * which are permitted to clash with other implementer part numbers.
208 static inline unsigned int __attribute_const__
read_cpuid_part(void)
210 return read_cpuid_id() & ARM_CPU_PART_MASK
;
213 static inline unsigned int __attribute_const__ __deprecated
read_cpuid_part_number(void)
215 return read_cpuid_id() & 0xFFF0;
218 static inline unsigned int __attribute_const__
xscale_cpu_arch_version(void)
220 return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK
;
223 static inline unsigned int __attribute_const__
read_cpuid_tcmstatus(void)
225 return read_cpuid(CPUID_TCM
);
228 static inline unsigned int __attribute_const__
read_cpuid_mpidr(void)
230 return read_cpuid(CPUID_MPIDR
);
233 /* StrongARM-11x0 CPUs */
234 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
235 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
238 * Intel's XScale3 core supports some v6 features (supersections, L2)
239 * but advertises itself as v5 as it does not support the v6 ISA. For
240 * this reason, we need a way to explicitly test for this type of CPU.
242 #ifndef CONFIG_CPU_XSC3
243 #define cpu_is_xsc3() 0
245 static inline int cpu_is_xsc3(void)
248 id
= read_cpuid_id() & 0xffffe000;
249 /* It covers both Intel ID and Marvell ID */
250 if ((id
== 0x69056000) || (id
== 0x56056000))
257 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
258 !defined(CONFIG_CPU_MOHAWK)
259 #define cpu_is_xscale_family() 0
261 static inline int cpu_is_xscale_family(void)
264 id
= read_cpuid_id() & 0xffffe000;
267 case 0x69052000: /* Intel XScale 1 */
268 case 0x69054000: /* Intel XScale 2 */
269 case 0x69056000: /* Intel XScale 3 */
270 case 0x56056000: /* Marvell XScale 3 */
271 case 0x56158000: /* Marvell Mohawk */
280 * Marvell's PJ4 and PJ4B cores are based on V7 version,
281 * but require a specical sequence for enabling coprocessors.
282 * For this reason, we need a way to distinguish them.
284 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
285 static inline int cpu_is_pj4(void)
289 id
= read_cpuid_id();
290 if ((id
& 0xff0fff00) == 0x560f5800)
296 #define cpu_is_pj4() 0
299 static inline int __attribute_const__
cpuid_feature_extract_field(u32 features
,
302 int feature
= (features
>> field
) & 15;
304 /* feature registers are signed values */
311 #define cpuid_feature_extract(reg, field) \
312 cpuid_feature_extract_field(read_cpuid_ext(reg), field)