2 * linux/arch/arm/kernel/bios32.c
4 * PCI bios-type initialisation for PCI machines
6 * Bits taken from various places.
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
15 #include <asm/mach-types.h>
16 #include <asm/mach/map.h>
17 #include <asm/mach/pci.h>
22 * We can't use pci_get_device() here since we are
23 * called from interrupt context.
25 static void pcibios_bus_report_status(struct pci_bus
*bus
, u_int status_mask
, int warn
)
29 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
33 * ignore host bridge - we handle
36 if (dev
->bus
->number
== 0 && dev
->devfn
== 0)
39 pci_read_config_word(dev
, PCI_STATUS
, &status
);
43 if ((status
& status_mask
) == 0)
46 /* clear the status errors */
47 pci_write_config_word(dev
, PCI_STATUS
, status
& status_mask
);
50 printk("(%s: %04X) ", pci_name(dev
), status
);
53 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
55 pcibios_bus_report_status(dev
->subordinate
, status_mask
, warn
);
58 void pcibios_report_status(u_int status_mask
, int warn
)
62 list_for_each_entry(bus
, &pci_root_buses
, node
)
63 pcibios_bus_report_status(bus
, status_mask
, warn
);
67 * We don't use this to fix the device, but initialisation of it.
68 * It's not the correct use for this, but it works.
69 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
72 * 2. ISA bridge ping-pong
73 * 3. ISA bridge master handling of target RETRY
75 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
78 static void pci_fixup_83c553(struct pci_dev
*dev
)
81 * Set memory region to start at address 0, and enable IO
83 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
84 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_IO
);
86 dev
->resource
[0].end
-= dev
->resource
[0].start
;
87 dev
->resource
[0].start
= 0;
90 * All memory requests from ISA to be channelled to PCI
92 pci_write_config_byte(dev
, 0x48, 0xff);
95 * Enable ping-pong on bus master to ISA bridge transactions.
96 * This improves the sound DMA substantially. The fixed
97 * priority arbiter also helps (see below).
99 pci_write_config_byte(dev
, 0x42, 0x01);
104 pci_write_config_byte(dev
, 0x40, 0x22);
107 * We used to set the arbiter to "park on last master" (bit
108 * 1 set), but unfortunately the CyberPro does not park the
109 * bus. We must therefore park on CPU. Unfortunately, this
110 * may trigger yet another bug in the 553.
112 pci_write_config_byte(dev
, 0x83, 0x02);
115 * Make the ISA DMA request lowest priority, and disable
116 * rotating priorities completely.
118 pci_write_config_byte(dev
, 0x80, 0x11);
119 pci_write_config_byte(dev
, 0x81, 0x00);
122 * Route INTA input to IRQ 11, and set IRQ11 to be level
125 pci_write_config_word(dev
, 0x44, 0xb000);
128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND
, PCI_DEVICE_ID_WINBOND_83C553
, pci_fixup_83c553
);
130 static void pci_fixup_unassign(struct pci_dev
*dev
)
132 dev
->resource
[0].end
-= dev
->resource
[0].start
;
133 dev
->resource
[0].start
= 0;
135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2
, PCI_DEVICE_ID_WINBOND2_89C940F
, pci_fixup_unassign
);
138 * Prevent the PCI layer from seeing the resources allocated to this device
139 * if it is the host bridge by marking it as such. These resources are of
140 * no consequence to the PCI layer (they are handled elsewhere).
142 static void pci_fixup_dec21285(struct pci_dev
*dev
)
146 if (dev
->devfn
== 0) {
148 dev
->class |= PCI_CLASS_BRIDGE_HOST
<< 8;
149 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
150 dev
->resource
[i
].start
= 0;
151 dev
->resource
[i
].end
= 0;
152 dev
->resource
[i
].flags
= 0;
156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_21285
, pci_fixup_dec21285
);
159 * PCI IDE controllers use non-standard I/O port decoding, respect it.
161 static void pci_fixup_ide_bases(struct pci_dev
*dev
)
166 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
169 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
170 r
= dev
->resource
+ i
;
171 if ((r
->start
& ~0x80) == 0x374) {
177 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pci_fixup_ide_bases
);
180 * Put the DEC21142 to sleep
182 static void pci_fixup_dec21142(struct pci_dev
*dev
)
184 pci_write_config_dword(dev
, 0x40, 0x80000000);
186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_21142
, pci_fixup_dec21142
);
189 * The CY82C693 needs some rather major fixups to ensure that it does
190 * the right thing. Idea from the Alpha people, with a few additions.
192 * We ensure that the IDE base registers are set to 1f0/3f4 for the
193 * primary bus, and 170/374 for the secondary bus. Also, hide them
194 * from the PCI subsystem view as well so we won't try to perform
195 * our own auto-configuration on them.
197 * In addition, we ensure that the PCI IDE interrupts are routed to
198 * IRQ 14 and IRQ 15 respectively.
200 * The above gets us to a point where the IDE on this device is
201 * functional. However, The CY82C693U _does not work_ in bus
202 * master mode without locking the PCI bus solid.
204 static void pci_fixup_cy82c693(struct pci_dev
*dev
)
206 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
) {
209 if (dev
->class & 0x80) { /* primary */
212 } else { /* secondary */
217 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
,
218 base0
| PCI_BASE_ADDRESS_SPACE_IO
);
219 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_1
,
220 base1
| PCI_BASE_ADDRESS_SPACE_IO
);
222 dev
->resource
[0].start
= 0;
223 dev
->resource
[0].end
= 0;
224 dev
->resource
[0].flags
= 0;
226 dev
->resource
[1].start
= 0;
227 dev
->resource
[1].end
= 0;
228 dev
->resource
[1].flags
= 0;
229 } else if (PCI_FUNC(dev
->devfn
) == 0) {
231 * Setup IDE IRQ routing.
233 pci_write_config_byte(dev
, 0x4b, 14);
234 pci_write_config_byte(dev
, 0x4c, 15);
237 * Disable FREQACK handshake, enable USB.
239 pci_write_config_byte(dev
, 0x4d, 0x41);
242 * Enable PCI retry, and PCI post-write buffer.
244 pci_write_config_byte(dev
, 0x44, 0x17);
247 * Enable ISA master and DMA post write buffering.
249 pci_write_config_byte(dev
, 0x45, 0x03);
252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ
, PCI_DEVICE_ID_CONTAQ_82C693
, pci_fixup_cy82c693
);
254 static void pci_fixup_it8152(struct pci_dev
*dev
)
257 /* fixup for ITE 8152 devices */
258 /* FIXME: add defines for class 0x68000 and 0x80103 */
259 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
||
260 dev
->class == 0x68000 ||
261 dev
->class == 0x80103) {
262 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
263 dev
->resource
[i
].start
= 0;
264 dev
->resource
[i
].end
= 0;
265 dev
->resource
[i
].flags
= 0;
269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE
, PCI_DEVICE_ID_ITE_8152
, pci_fixup_it8152
);
272 * If the bus contains any of these devices, then we must not turn on
273 * parity checking of any kind. Currently this is CyberPro 20x0 only.
275 static inline int pdev_bad_for_parity(struct pci_dev
*dev
)
277 return ((dev
->vendor
== PCI_VENDOR_ID_INTERG
&&
278 (dev
->device
== PCI_DEVICE_ID_INTERG_2000
||
279 dev
->device
== PCI_DEVICE_ID_INTERG_2010
)) ||
280 (dev
->vendor
== PCI_VENDOR_ID_ITE
&&
281 dev
->device
== PCI_DEVICE_ID_ITE_8152
));
286 * pcibios_fixup_bus - Called after each bus is probed,
287 * but before its children are examined.
289 void pcibios_fixup_bus(struct pci_bus
*bus
)
292 u16 features
= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
| PCI_COMMAND_FAST_BACK
;
295 * Walk the devices on this bus, working out what we can
298 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
301 pci_read_config_word(dev
, PCI_STATUS
, &status
);
304 * If any device on this bus does not support fast back
305 * to back transfers, then the bus as a whole is not able
306 * to support them. Having fast back to back transfers
307 * on saves us one PCI cycle per transaction.
309 if (!(status
& PCI_STATUS_FAST_BACK
))
310 features
&= ~PCI_COMMAND_FAST_BACK
;
312 if (pdev_bad_for_parity(dev
))
313 features
&= ~(PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
315 switch (dev
->class >> 8) {
316 case PCI_CLASS_BRIDGE_PCI
:
317 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &status
);
318 status
|= PCI_BRIDGE_CTL_PARITY
|PCI_BRIDGE_CTL_MASTER_ABORT
;
319 status
&= ~(PCI_BRIDGE_CTL_BUS_RESET
|PCI_BRIDGE_CTL_FAST_BACK
);
320 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, status
);
323 case PCI_CLASS_BRIDGE_CARDBUS
:
324 pci_read_config_word(dev
, PCI_CB_BRIDGE_CONTROL
, &status
);
325 status
|= PCI_CB_BRIDGE_CTL_PARITY
|PCI_CB_BRIDGE_CTL_MASTER_ABORT
;
326 pci_write_config_word(dev
, PCI_CB_BRIDGE_CONTROL
, status
);
332 * Now walk the devices again, this time setting them up.
334 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
337 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
339 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
341 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
,
342 L1_CACHE_BYTES
>> 2);
346 * Propagate the flags to the PCI bridge.
348 if (bus
->self
&& bus
->self
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
349 if (features
& PCI_COMMAND_FAST_BACK
)
350 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_FAST_BACK
;
351 if (features
& PCI_COMMAND_PARITY
)
352 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_PARITY
;
356 * Report what we did for this bus
358 pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
359 bus
->number
, (features
& PCI_COMMAND_FAST_BACK
) ? "en" : "dis");
361 EXPORT_SYMBOL(pcibios_fixup_bus
);
363 void pcibios_add_bus(struct pci_bus
*bus
)
365 struct pci_sys_data
*sys
= bus
->sysdata
;
370 void pcibios_remove_bus(struct pci_bus
*bus
)
372 struct pci_sys_data
*sys
= bus
->sysdata
;
374 sys
->remove_bus(bus
);
378 * Swizzle the device pin each time we cross a bridge. If a platform does
379 * not provide a swizzle function, we perform the standard PCI swizzling.
381 * The default swizzling walks up the bus tree one level at a time, applying
382 * the standard swizzle function at each step, stopping when it finds the PCI
383 * root bus. This will return the slot number of the bridge device on the
384 * root bus and the interrupt pin on that device which should correspond
385 * with the downstream device interrupt.
387 * Platforms may override this, in which case the slot and pin returned
388 * depend entirely on the platform code. However, please note that the
389 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
390 * PCI extenders, so it can not be ignored.
392 static u8
pcibios_swizzle(struct pci_dev
*dev
, u8
*pin
)
394 struct pci_sys_data
*sys
= dev
->sysdata
;
395 int slot
, oldpin
= *pin
;
398 slot
= sys
->swizzle(dev
, pin
);
400 slot
= pci_common_swizzle(dev
, pin
);
403 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
404 pci_name(dev
), oldpin
, *pin
, slot
);
410 * Map a slot/pin to an IRQ.
412 static int pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
414 struct pci_sys_data
*sys
= dev
->sysdata
;
418 irq
= sys
->map_irq(dev
, slot
, pin
);
421 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
422 pci_name(dev
), slot
, pin
, irq
);
427 static int pcibios_init_resources(int busnr
, struct pci_sys_data
*sys
)
430 struct pci_host_bridge_window
*window
;
432 if (list_empty(&sys
->resources
)) {
433 pci_add_resource_offset(&sys
->resources
,
434 &iomem_resource
, sys
->mem_offset
);
437 list_for_each_entry(window
, &sys
->resources
, list
) {
438 if (resource_type(window
->res
) == IORESOURCE_IO
)
442 sys
->io_res
.start
= (busnr
* SZ_64K
) ? : pcibios_min_io
;
443 sys
->io_res
.end
= (busnr
+ 1) * SZ_64K
- 1;
444 sys
->io_res
.flags
= IORESOURCE_IO
;
445 sys
->io_res
.name
= sys
->io_res_name
;
446 sprintf(sys
->io_res_name
, "PCI%d I/O", busnr
);
448 ret
= request_resource(&ioport_resource
, &sys
->io_res
);
450 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret
);
453 pci_add_resource_offset(&sys
->resources
, &sys
->io_res
,
459 static void pcibios_init_hw(struct device
*parent
, struct hw_pci
*hw
,
460 struct list_head
*head
)
462 struct pci_sys_data
*sys
= NULL
;
466 for (nr
= busnr
= 0; nr
< hw
->nr_controllers
; nr
++) {
467 sys
= kzalloc(sizeof(struct pci_sys_data
), GFP_KERNEL
);
469 panic("PCI: unable to allocate sys data!");
471 #ifdef CONFIG_PCI_DOMAINS
472 sys
->domain
= hw
->domain
;
475 sys
->swizzle
= hw
->swizzle
;
476 sys
->map_irq
= hw
->map_irq
;
477 sys
->align_resource
= hw
->align_resource
;
478 sys
->add_bus
= hw
->add_bus
;
479 sys
->remove_bus
= hw
->remove_bus
;
480 INIT_LIST_HEAD(&sys
->resources
);
482 if (hw
->private_data
)
483 sys
->private_data
= hw
->private_data
[nr
];
485 ret
= hw
->setup(nr
, sys
);
488 ret
= pcibios_init_resources(nr
, sys
);
495 sys
->bus
= hw
->scan(nr
, sys
);
497 sys
->bus
= pci_scan_root_bus(parent
, sys
->busnr
,
498 hw
->ops
, sys
, &sys
->resources
);
501 panic("PCI: unable to scan bus!");
503 busnr
= sys
->bus
->busn_res
.end
+ 1;
505 list_add(&sys
->node
, head
);
514 void pci_common_init_dev(struct device
*parent
, struct hw_pci
*hw
)
516 struct pci_sys_data
*sys
;
519 pci_add_flags(PCI_REASSIGN_ALL_RSRC
);
522 pcibios_init_hw(parent
, hw
, &head
);
526 pci_fixup_irqs(pcibios_swizzle
, pcibios_map_irq
);
528 list_for_each_entry(sys
, &head
, node
) {
529 struct pci_bus
*bus
= sys
->bus
;
531 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
533 * Size the bridge windows.
535 pci_bus_size_bridges(bus
);
540 pci_bus_assign_resources(bus
);
544 * Tell drivers about devices found.
546 pci_bus_add_devices(bus
);
549 list_for_each_entry(sys
, &head
, node
) {
550 struct pci_bus
*bus
= sys
->bus
;
552 /* Configure PCI Express settings */
553 if (bus
&& !pci_has_flag(PCI_PROBE_ONLY
)) {
554 struct pci_bus
*child
;
556 list_for_each_entry(child
, &bus
->children
, node
)
557 pcie_bus_configure_settings(child
);
562 #ifndef CONFIG_PCI_HOST_ITE8152
563 void pcibios_set_master(struct pci_dev
*dev
)
565 /* No special bus mastering setup handling */
569 char * __init
pcibios_setup(char *str
)
571 if (!strcmp(str
, "debug")) {
574 } else if (!strcmp(str
, "firmware")) {
575 pci_add_flags(PCI_PROBE_ONLY
);
582 * From arch/i386/kernel/pci-i386.c:
584 * We need to avoid collisions with `mirrored' VGA ports
585 * and other strange ISA hardware, so we always want the
586 * addresses to be allocated in the 0x000-0x0ff region
589 * Why? Because some silly external IO cards only decode
590 * the low 10 bits of the IO address. The 0x00-0xff region
591 * is reserved for motherboard devices that decode all 16
592 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
593 * but we want to try to avoid allocating at 0x2900-0x2bff
594 * which might be mirrored at 0x0100-0x03ff..
596 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
597 resource_size_t size
, resource_size_t align
)
599 struct pci_dev
*dev
= data
;
600 struct pci_sys_data
*sys
= dev
->sysdata
;
601 resource_size_t start
= res
->start
;
603 if (res
->flags
& IORESOURCE_IO
&& start
& 0x300)
604 start
= (start
+ 0x3ff) & ~0x3ff;
606 start
= (start
+ align
- 1) & ~(align
- 1);
608 if (sys
->align_resource
)
609 return sys
->align_resource(dev
, res
, start
, size
, align
);
615 * pcibios_enable_device - Enable I/O and memory.
616 * @dev: PCI device to be enabled
618 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
620 if (pci_has_flag(PCI_PROBE_ONLY
))
623 return pci_enable_resources(dev
, mask
);
626 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
627 enum pci_mmap_state mmap_state
, int write_combine
)
629 struct pci_sys_data
*root
= dev
->sysdata
;
632 if (mmap_state
== pci_mmap_io
) {
635 phys
= vma
->vm_pgoff
+ (root
->mem_offset
>> PAGE_SHIFT
);
641 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
643 if (remap_pfn_range(vma
, vma
->vm_start
, phys
,
644 vma
->vm_end
- vma
->vm_start
,
651 void __init
pci_map_io_early(unsigned long pfn
)
653 struct map_desc pci_io_desc
= {
654 .virtual = PCI_IO_VIRT_BASE
,
659 pci_io_desc
.pfn
= pfn
;
660 iotable_init(&pci_io_desc
, 1);