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[ARM] 3060/1: allow constants found in asm/memory.h to be used in asm code
[deliverable/linux.git] / arch / arm / kernel / entry-armv.S
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Low-level vector interface routines
12 *
13 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
14 * it to save wrong values... Be aware!
15 */
16 #include <linux/config.h>
17
18 #include <asm/memory.h>
19 #include <asm/glue.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/hardware.h> /* should be moved into entry-macro.S */
22 #include <asm/arch/irqs.h> /* should be moved into entry-macro.S */
23 #include <asm/arch/entry-macro.S>
24
25 #include "entry-header.S"
26
27 /*
28 * Interrupt handling. Preserves r7, r8, r9
29 */
30 .macro irq_handler
31 1: get_irqnr_and_base r0, r6, r5, lr
32 movne r1, sp
33 @
34 @ routine called with r0 = irq number, r1 = struct pt_regs *
35 @
36 adrne lr, 1b
37 bne asm_do_IRQ
38
39 #ifdef CONFIG_SMP
40 /*
41 * XXX
42 *
43 * this macro assumes that irqstat (r6) and base (r5) are
44 * preserved from get_irqnr_and_base above
45 */
46 test_for_ipi r0, r6, r5, lr
47 movne r0, sp
48 adrne lr, 1b
49 bne do_IPI
50 #endif
51
52 .endm
53
54 /*
55 * Invalid mode handlers
56 */
57 .macro inv_entry, reason
58 sub sp, sp, #S_FRAME_SIZE
59 stmib sp, {r1 - lr}
60 mov r1, #\reason
61 .endm
62
63 __pabt_invalid:
64 inv_entry BAD_PREFETCH
65 b common_invalid
66
67 __dabt_invalid:
68 inv_entry BAD_DATA
69 b common_invalid
70
71 __irq_invalid:
72 inv_entry BAD_IRQ
73 b common_invalid
74
75 __und_invalid:
76 inv_entry BAD_UNDEFINSTR
77
78 @
79 @ XXX fall through to common_invalid
80 @
81
82 @
83 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
84 @
85 common_invalid:
86 zero_fp
87
88 ldmia r0, {r4 - r6}
89 add r0, sp, #S_PC @ here for interlock avoidance
90 mov r7, #-1 @ "" "" "" ""
91 str r4, [sp] @ save preserved r0
92 stmia r0, {r5 - r7} @ lr_<exception>,
93 @ cpsr_<exception>, "old_r0"
94
95 mov r0, sp
96 and r2, r6, #0x1f
97 b bad_mode
98
99 /*
100 * SVC mode handlers
101 */
102 .macro svc_entry
103 sub sp, sp, #S_FRAME_SIZE
104 stmib sp, {r1 - r12}
105
106 ldmia r0, {r1 - r3}
107 add r5, sp, #S_SP @ here for interlock avoidance
108 mov r4, #-1 @ "" "" "" ""
109 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
110 str r1, [sp] @ save the "real" r0 copied
111 @ from the exception stack
112
113 mov r1, lr
114
115 @
116 @ We are now ready to fill in the remaining blanks on the stack:
117 @
118 @ r0 - sp_svc
119 @ r1 - lr_svc
120 @ r2 - lr_<exception>, already fixed up for correct return/restart
121 @ r3 - spsr_<exception>
122 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
123 @
124 stmia r5, {r0 - r4}
125 .endm
126
127 .align 5
128 __dabt_svc:
129 svc_entry
130
131 @
132 @ get ready to re-enable interrupts if appropriate
133 @
134 mrs r9, cpsr
135 tst r3, #PSR_I_BIT
136 biceq r9, r9, #PSR_I_BIT
137
138 @
139 @ Call the processor-specific abort handler:
140 @
141 @ r2 - aborted context pc
142 @ r3 - aborted context cpsr
143 @
144 @ The abort handler must return the aborted address in r0, and
145 @ the fault status register in r1. r9 must be preserved.
146 @
147 #ifdef MULTI_ABORT
148 ldr r4, .LCprocfns
149 mov lr, pc
150 ldr pc, [r4]
151 #else
152 bl CPU_ABORT_HANDLER
153 #endif
154
155 @
156 @ set desired IRQ state, then call main handler
157 @
158 msr cpsr_c, r9
159 mov r2, sp
160 bl do_DataAbort
161
162 @
163 @ IRQs off again before pulling preserved data off the stack
164 @
165 disable_irq
166
167 @
168 @ restore SPSR and restart the instruction
169 @
170 ldr r0, [sp, #S_PSR]
171 msr spsr_cxsf, r0
172 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
173
174 .align 5
175 __irq_svc:
176 svc_entry
177
178 #ifdef CONFIG_PREEMPT
179 get_thread_info tsk
180 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
181 add r7, r8, #1 @ increment it
182 str r7, [tsk, #TI_PREEMPT]
183 #endif
184
185 irq_handler
186 #ifdef CONFIG_PREEMPT
187 ldr r0, [tsk, #TI_FLAGS] @ get flags
188 tst r0, #_TIF_NEED_RESCHED
189 blne svc_preempt
190 preempt_return:
191 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
192 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
193 teq r0, r7
194 strne r0, [r0, -r0] @ bug()
195 #endif
196 ldr r0, [sp, #S_PSR] @ irqs are already disabled
197 msr spsr_cxsf, r0
198 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
199
200 .ltorg
201
202 #ifdef CONFIG_PREEMPT
203 svc_preempt:
204 teq r8, #0 @ was preempt count = 0
205 ldreq r6, .LCirq_stat
206 movne pc, lr @ no
207 ldr r0, [r6, #4] @ local_irq_count
208 ldr r1, [r6, #8] @ local_bh_count
209 adds r0, r0, r1
210 movne pc, lr
211 mov r7, #0 @ preempt_schedule_irq
212 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
213 1: bl preempt_schedule_irq @ irq en/disable is done inside
214 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
215 tst r0, #_TIF_NEED_RESCHED
216 beq preempt_return @ go again
217 b 1b
218 #endif
219
220 .align 5
221 __und_svc:
222 svc_entry
223
224 @
225 @ call emulation code, which returns using r9 if it has emulated
226 @ the instruction, or the more conventional lr if we are to treat
227 @ this as a real undefined instruction
228 @
229 @ r0 - instruction
230 @
231 ldr r0, [r2, #-4]
232 adr r9, 1f
233 bl call_fpe
234
235 mov r0, sp @ struct pt_regs *regs
236 bl do_undefinstr
237
238 @
239 @ IRQs off again before pulling preserved data off the stack
240 @
241 1: disable_irq
242
243 @
244 @ restore SPSR and restart the instruction
245 @
246 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
247 msr spsr_cxsf, lr
248 ldmia sp, {r0 - pc}^ @ Restore SVC registers
249
250 .align 5
251 __pabt_svc:
252 svc_entry
253
254 @
255 @ re-enable interrupts if appropriate
256 @
257 mrs r9, cpsr
258 tst r3, #PSR_I_BIT
259 biceq r9, r9, #PSR_I_BIT
260 msr cpsr_c, r9
261
262 @
263 @ set args, then call main handler
264 @
265 @ r0 - address of faulting instruction
266 @ r1 - pointer to registers on stack
267 @
268 mov r0, r2 @ address (pc)
269 mov r1, sp @ regs
270 bl do_PrefetchAbort @ call abort handler
271
272 @
273 @ IRQs off again before pulling preserved data off the stack
274 @
275 disable_irq
276
277 @
278 @ restore SPSR and restart the instruction
279 @
280 ldr r0, [sp, #S_PSR]
281 msr spsr_cxsf, r0
282 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
283
284 .align 5
285 .LCcralign:
286 .word cr_alignment
287 #ifdef MULTI_ABORT
288 .LCprocfns:
289 .word processor
290 #endif
291 .LCfp:
292 .word fp_enter
293 #ifdef CONFIG_PREEMPT
294 .LCirq_stat:
295 .word irq_stat
296 #endif
297
298 /*
299 * User mode handlers
300 */
301 .macro usr_entry
302 sub sp, sp, #S_FRAME_SIZE
303 stmib sp, {r1 - r12}
304
305 ldmia r0, {r1 - r3}
306 add r0, sp, #S_PC @ here for interlock avoidance
307 mov r4, #-1 @ "" "" "" ""
308
309 str r1, [sp] @ save the "real" r0 copied
310 @ from the exception stack
311
312 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
313 @ make sure our user space atomic helper is aborted
314 cmp r2, #TASK_SIZE
315 bichs r3, r3, #PSR_Z_BIT
316 #endif
317
318 @
319 @ We are now ready to fill in the remaining blanks on the stack:
320 @
321 @ r2 - lr_<exception>, already fixed up for correct return/restart
322 @ r3 - spsr_<exception>
323 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
324 @
325 @ Also, separately save sp_usr and lr_usr
326 @
327 stmia r0, {r2 - r4}
328 stmdb r0, {sp, lr}^
329
330 @
331 @ Enable the alignment trap while in kernel mode
332 @
333 alignment_trap r0
334
335 @
336 @ Clear FP to mark the first stack frame
337 @
338 zero_fp
339 .endm
340
341 .align 5
342 __dabt_usr:
343 usr_entry
344
345 @
346 @ Call the processor-specific abort handler:
347 @
348 @ r2 - aborted context pc
349 @ r3 - aborted context cpsr
350 @
351 @ The abort handler must return the aborted address in r0, and
352 @ the fault status register in r1.
353 @
354 #ifdef MULTI_ABORT
355 ldr r4, .LCprocfns
356 mov lr, pc
357 ldr pc, [r4]
358 #else
359 bl CPU_ABORT_HANDLER
360 #endif
361
362 @
363 @ IRQs on, then call the main handler
364 @
365 enable_irq
366 mov r2, sp
367 adr lr, ret_from_exception
368 b do_DataAbort
369
370 .align 5
371 __irq_usr:
372 usr_entry
373
374 get_thread_info tsk
375 #ifdef CONFIG_PREEMPT
376 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
377 add r7, r8, #1 @ increment it
378 str r7, [tsk, #TI_PREEMPT]
379 #endif
380
381 irq_handler
382 #ifdef CONFIG_PREEMPT
383 ldr r0, [tsk, #TI_PREEMPT]
384 str r8, [tsk, #TI_PREEMPT]
385 teq r0, r7
386 strne r0, [r0, -r0]
387 #endif
388
389 mov why, #0
390 b ret_to_user
391
392 .ltorg
393
394 .align 5
395 __und_usr:
396 usr_entry
397
398 tst r3, #PSR_T_BIT @ Thumb mode?
399 bne fpundefinstr @ ignore FP
400 sub r4, r2, #4
401
402 @
403 @ fall through to the emulation code, which returns using r9 if
404 @ it has emulated the instruction, or the more conventional lr
405 @ if we are to treat this as a real undefined instruction
406 @
407 @ r0 - instruction
408 @
409 1: ldrt r0, [r4]
410 adr r9, ret_from_exception
411 adr lr, fpundefinstr
412 @
413 @ fallthrough to call_fpe
414 @
415
416 /*
417 * The out of line fixup for the ldrt above.
418 */
419 .section .fixup, "ax"
420 2: mov pc, r9
421 .previous
422 .section __ex_table,"a"
423 .long 1b, 2b
424 .previous
425
426 /*
427 * Check whether the instruction is a co-processor instruction.
428 * If yes, we need to call the relevant co-processor handler.
429 *
430 * Note that we don't do a full check here for the co-processor
431 * instructions; all instructions with bit 27 set are well
432 * defined. The only instructions that should fault are the
433 * co-processor instructions. However, we have to watch out
434 * for the ARM6/ARM7 SWI bug.
435 *
436 * Emulators may wish to make use of the following registers:
437 * r0 = instruction opcode.
438 * r2 = PC+4
439 * r10 = this threads thread_info structure.
440 */
441 call_fpe:
442 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
443 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
444 and r8, r0, #0x0f000000 @ mask out op-code bits
445 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
446 #endif
447 moveq pc, lr
448 get_thread_info r10 @ get current thread
449 and r8, r0, #0x00000f00 @ mask out CP number
450 mov r7, #1
451 add r6, r10, #TI_USED_CP
452 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
453 #ifdef CONFIG_IWMMXT
454 @ Test if we need to give access to iWMMXt coprocessors
455 ldr r5, [r10, #TI_FLAGS]
456 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
457 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
458 bcs iwmmxt_task_enable
459 #endif
460 enable_irq
461 add pc, pc, r8, lsr #6
462 mov r0, r0
463
464 mov pc, lr @ CP#0
465 b do_fpe @ CP#1 (FPE)
466 b do_fpe @ CP#2 (FPE)
467 mov pc, lr @ CP#3
468 mov pc, lr @ CP#4
469 mov pc, lr @ CP#5
470 mov pc, lr @ CP#6
471 mov pc, lr @ CP#7
472 mov pc, lr @ CP#8
473 mov pc, lr @ CP#9
474 #ifdef CONFIG_VFP
475 b do_vfp @ CP#10 (VFP)
476 b do_vfp @ CP#11 (VFP)
477 #else
478 mov pc, lr @ CP#10 (VFP)
479 mov pc, lr @ CP#11 (VFP)
480 #endif
481 mov pc, lr @ CP#12
482 mov pc, lr @ CP#13
483 mov pc, lr @ CP#14 (Debug)
484 mov pc, lr @ CP#15 (Control)
485
486 do_fpe:
487 ldr r4, .LCfp
488 add r10, r10, #TI_FPSTATE @ r10 = workspace
489 ldr pc, [r4] @ Call FP module USR entry point
490
491 /*
492 * The FP module is called with these registers set:
493 * r0 = instruction
494 * r2 = PC+4
495 * r9 = normal "successful" return address
496 * r10 = FP workspace
497 * lr = unrecognised FP instruction return address
498 */
499
500 .data
501 ENTRY(fp_enter)
502 .word fpundefinstr
503 .text
504
505 fpundefinstr:
506 mov r0, sp
507 adr lr, ret_from_exception
508 b do_undefinstr
509
510 .align 5
511 __pabt_usr:
512 usr_entry
513
514 enable_irq @ Enable interrupts
515 mov r0, r2 @ address (pc)
516 mov r1, sp @ regs
517 bl do_PrefetchAbort @ call abort handler
518 /* fall through */
519 /*
520 * This is the return code to user mode for abort handlers
521 */
522 ENTRY(ret_from_exception)
523 get_thread_info tsk
524 mov why, #0
525 b ret_to_user
526
527 /*
528 * Register switch for ARMv3 and ARMv4 processors
529 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
530 * previous and next are guaranteed not to be the same.
531 */
532 ENTRY(__switch_to)
533 add ip, r1, #TI_CPU_SAVE
534 ldr r3, [r2, #TI_TP_VALUE]
535 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
536 ldr r6, [r2, #TI_CPU_DOMAIN]!
537 #if __LINUX_ARM_ARCH__ >= 6
538 #ifdef CONFIG_CPU_MPCORE
539 clrex
540 #else
541 strex r5, r4, [ip] @ Clear exclusive monitor
542 #endif
543 #endif
544 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
545 mra r4, r5, acc0
546 stmia ip, {r4, r5}
547 #endif
548 #if defined(CONFIG_HAS_TLS_REG)
549 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
550 #elif !defined(CONFIG_TLS_REG_EMUL)
551 mov r4, #0xffff0fff
552 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
553 #endif
554 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
555 #ifdef CONFIG_VFP
556 @ Always disable VFP so we can lazily save/restore the old
557 @ state. This occurs in the context of the previous thread.
558 VFPFMRX r4, FPEXC
559 bic r4, r4, #FPEXC_ENABLE
560 VFPFMXR FPEXC, r4
561 #endif
562 #if defined(CONFIG_IWMMXT)
563 bl iwmmxt_task_switch
564 #elif defined(CONFIG_CPU_XSCALE)
565 add r4, r2, #40 @ cpu_context_save->extra
566 ldmib r4, {r4, r5}
567 mar acc0, r4, r5
568 #endif
569 ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
570
571 __INIT
572
573 /*
574 * User helpers.
575 *
576 * These are segment of kernel provided user code reachable from user space
577 * at a fixed address in kernel memory. This is used to provide user space
578 * with some operations which require kernel help because of unimplemented
579 * native feature and/or instructions in many ARM CPUs. The idea is for
580 * this code to be executed directly in user mode for best efficiency but
581 * which is too intimate with the kernel counter part to be left to user
582 * libraries. In fact this code might even differ from one CPU to another
583 * depending on the available instruction set and restrictions like on
584 * SMP systems. In other words, the kernel reserves the right to change
585 * this code as needed without warning. Only the entry points and their
586 * results are guaranteed to be stable.
587 *
588 * Each segment is 32-byte aligned and will be moved to the top of the high
589 * vector page. New segments (if ever needed) must be added in front of
590 * existing ones. This mechanism should be used only for things that are
591 * really small and justified, and not be abused freely.
592 *
593 * User space is expected to implement those things inline when optimizing
594 * for a processor that has the necessary native support, but only if such
595 * resulting binaries are already to be incompatible with earlier ARM
596 * processors due to the use of unsupported instructions other than what
597 * is provided here. In other words don't make binaries unable to run on
598 * earlier processors just for the sake of not using these kernel helpers
599 * if your compiled code is not going to use the new instructions for other
600 * purpose.
601 */
602
603 .align 5
604 .globl __kuser_helper_start
605 __kuser_helper_start:
606
607 /*
608 * Reference prototype:
609 *
610 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
611 *
612 * Input:
613 *
614 * r0 = oldval
615 * r1 = newval
616 * r2 = ptr
617 * lr = return address
618 *
619 * Output:
620 *
621 * r0 = returned value (zero or non-zero)
622 * C flag = set if r0 == 0, clear if r0 != 0
623 *
624 * Clobbered:
625 *
626 * r3, ip, flags
627 *
628 * Definition and user space usage example:
629 *
630 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
631 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
632 *
633 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
634 * Return zero if *ptr was changed or non-zero if no exchange happened.
635 * The C flag is also set if *ptr was changed to allow for assembly
636 * optimization in the calling code.
637 *
638 * For example, a user space atomic_add implementation could look like this:
639 *
640 * #define atomic_add(ptr, val) \
641 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
642 * register unsigned int __result asm("r1"); \
643 * asm volatile ( \
644 * "1: @ atomic_add\n\t" \
645 * "ldr r0, [r2]\n\t" \
646 * "mov r3, #0xffff0fff\n\t" \
647 * "add lr, pc, #4\n\t" \
648 * "add r1, r0, %2\n\t" \
649 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
650 * "bcc 1b" \
651 * : "=&r" (__result) \
652 * : "r" (__ptr), "rIL" (val) \
653 * : "r0","r3","ip","lr","cc","memory" ); \
654 * __result; })
655 */
656
657 __kuser_cmpxchg: @ 0xffff0fc0
658
659 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
660
661 /*
662 * Poor you. No fast solution possible...
663 * The kernel itself must perform the operation.
664 * A special ghost syscall is used for that (see traps.c).
665 */
666 swi #0x9ffff0
667 mov pc, lr
668
669 #elif __LINUX_ARM_ARCH__ < 6
670
671 /*
672 * Theory of operation:
673 *
674 * We set the Z flag before loading oldval. If ever an exception
675 * occurs we can not be sure the loaded value will still be the same
676 * when the exception returns, therefore the user exception handler
677 * will clear the Z flag whenever the interrupted user code was
678 * actually from the kernel address space (see the usr_entry macro).
679 *
680 * The post-increment on the str is used to prevent a race with an
681 * exception happening just after the str instruction which would
682 * clear the Z flag although the exchange was done.
683 */
684 teq ip, ip @ set Z flag
685 ldr ip, [r2] @ load current val
686 add r3, r2, #1 @ prepare store ptr
687 teqeq ip, r0 @ compare with oldval if still allowed
688 streq r1, [r3, #-1]! @ store newval if still allowed
689 subs r0, r2, r3 @ if r2 == r3 the str occured
690 mov pc, lr
691
692 #else
693
694 ldrex r3, [r2]
695 subs r3, r3, r0
696 strexeq r3, r1, [r2]
697 rsbs r0, r3, #0
698 mov pc, lr
699
700 #endif
701
702 .align 5
703
704 /*
705 * Reference prototype:
706 *
707 * int __kernel_get_tls(void)
708 *
709 * Input:
710 *
711 * lr = return address
712 *
713 * Output:
714 *
715 * r0 = TLS value
716 *
717 * Clobbered:
718 *
719 * the Z flag might be lost
720 *
721 * Definition and user space usage example:
722 *
723 * typedef int (__kernel_get_tls_t)(void);
724 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
725 *
726 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
727 *
728 * This could be used as follows:
729 *
730 * #define __kernel_get_tls() \
731 * ({ register unsigned int __val asm("r0"); \
732 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
733 * : "=r" (__val) : : "lr","cc" ); \
734 * __val; })
735 */
736
737 __kuser_get_tls: @ 0xffff0fe0
738
739 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
740
741 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
742 mov pc, lr
743
744 #else
745
746 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
747 mov pc, lr
748
749 #endif
750
751 .rep 5
752 .word 0 @ pad up to __kuser_helper_version
753 .endr
754
755 /*
756 * Reference declaration:
757 *
758 * extern unsigned int __kernel_helper_version;
759 *
760 * Definition and user space usage example:
761 *
762 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
763 *
764 * User space may read this to determine the curent number of helpers
765 * available.
766 */
767
768 __kuser_helper_version: @ 0xffff0ffc
769 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
770
771 .globl __kuser_helper_end
772 __kuser_helper_end:
773
774
775 /*
776 * Vector stubs.
777 *
778 * This code is copied to 0xffff0200 so we can use branches in the
779 * vectors, rather than ldr's. Note that this code must not
780 * exceed 0x300 bytes.
781 *
782 * Common stub entry macro:
783 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
784 *
785 * SP points to a minimal amount of processor-private memory, the address
786 * of which is copied into r0 for the mode specific abort handler.
787 */
788 .macro vector_stub, name, correction=0
789 .align 5
790
791 vector_\name:
792 .if \correction
793 sub lr, lr, #\correction
794 .endif
795
796 @
797 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
798 @ (parent CPSR)
799 @
800 stmia sp, {r0, lr} @ save r0, lr
801 mrs lr, spsr
802 str lr, [sp, #8] @ save spsr
803
804 @
805 @ Prepare for SVC32 mode. IRQs remain disabled.
806 @
807 mrs r0, cpsr
808 bic r0, r0, #MODE_MASK
809 orr r0, r0, #SVC_MODE
810 msr spsr_cxsf, r0
811
812 @
813 @ the branch table must immediately follow this code
814 @
815 mov r0, sp
816 and lr, lr, #0x0f
817 ldr lr, [pc, lr, lsl #2]
818 movs pc, lr @ branch to handler in SVC mode
819 .endm
820
821 .globl __stubs_start
822 __stubs_start:
823 /*
824 * Interrupt dispatcher
825 */
826 vector_stub irq, 4
827
828 .long __irq_usr @ 0 (USR_26 / USR_32)
829 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
830 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
831 .long __irq_svc @ 3 (SVC_26 / SVC_32)
832 .long __irq_invalid @ 4
833 .long __irq_invalid @ 5
834 .long __irq_invalid @ 6
835 .long __irq_invalid @ 7
836 .long __irq_invalid @ 8
837 .long __irq_invalid @ 9
838 .long __irq_invalid @ a
839 .long __irq_invalid @ b
840 .long __irq_invalid @ c
841 .long __irq_invalid @ d
842 .long __irq_invalid @ e
843 .long __irq_invalid @ f
844
845 /*
846 * Data abort dispatcher
847 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
848 */
849 vector_stub dabt, 8
850
851 .long __dabt_usr @ 0 (USR_26 / USR_32)
852 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
853 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
854 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
855 .long __dabt_invalid @ 4
856 .long __dabt_invalid @ 5
857 .long __dabt_invalid @ 6
858 .long __dabt_invalid @ 7
859 .long __dabt_invalid @ 8
860 .long __dabt_invalid @ 9
861 .long __dabt_invalid @ a
862 .long __dabt_invalid @ b
863 .long __dabt_invalid @ c
864 .long __dabt_invalid @ d
865 .long __dabt_invalid @ e
866 .long __dabt_invalid @ f
867
868 /*
869 * Prefetch abort dispatcher
870 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
871 */
872 vector_stub pabt, 4
873
874 .long __pabt_usr @ 0 (USR_26 / USR_32)
875 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
876 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
877 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
878 .long __pabt_invalid @ 4
879 .long __pabt_invalid @ 5
880 .long __pabt_invalid @ 6
881 .long __pabt_invalid @ 7
882 .long __pabt_invalid @ 8
883 .long __pabt_invalid @ 9
884 .long __pabt_invalid @ a
885 .long __pabt_invalid @ b
886 .long __pabt_invalid @ c
887 .long __pabt_invalid @ d
888 .long __pabt_invalid @ e
889 .long __pabt_invalid @ f
890
891 /*
892 * Undef instr entry dispatcher
893 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
894 */
895 vector_stub und
896
897 .long __und_usr @ 0 (USR_26 / USR_32)
898 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
899 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
900 .long __und_svc @ 3 (SVC_26 / SVC_32)
901 .long __und_invalid @ 4
902 .long __und_invalid @ 5
903 .long __und_invalid @ 6
904 .long __und_invalid @ 7
905 .long __und_invalid @ 8
906 .long __und_invalid @ 9
907 .long __und_invalid @ a
908 .long __und_invalid @ b
909 .long __und_invalid @ c
910 .long __und_invalid @ d
911 .long __und_invalid @ e
912 .long __und_invalid @ f
913
914 .align 5
915
916 /*=============================================================================
917 * Undefined FIQs
918 *-----------------------------------------------------------------------------
919 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
920 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
921 * Basically to switch modes, we *HAVE* to clobber one register... brain
922 * damage alert! I don't think that we can execute any code in here in any
923 * other mode than FIQ... Ok you can switch to another mode, but you can't
924 * get out of that mode without clobbering one register.
925 */
926 vector_fiq:
927 disable_fiq
928 subs pc, lr, #4
929
930 /*=============================================================================
931 * Address exception handler
932 *-----------------------------------------------------------------------------
933 * These aren't too critical.
934 * (they're not supposed to happen, and won't happen in 32-bit data mode).
935 */
936
937 vector_addrexcptn:
938 b vector_addrexcptn
939
940 /*
941 * We group all the following data together to optimise
942 * for CPUs with separate I & D caches.
943 */
944 .align 5
945
946 .LCvswi:
947 .word vector_swi
948
949 .globl __stubs_end
950 __stubs_end:
951
952 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
953
954 .globl __vectors_start
955 __vectors_start:
956 swi SYS_ERROR0
957 b vector_und + stubs_offset
958 ldr pc, .LCvswi + stubs_offset
959 b vector_pabt + stubs_offset
960 b vector_dabt + stubs_offset
961 b vector_addrexcptn + stubs_offset
962 b vector_irq + stubs_offset
963 b vector_fiq + stubs_offset
964
965 .globl __vectors_end
966 __vectors_end:
967
968 .data
969
970 .globl cr_alignment
971 .globl cr_no_alignment
972 cr_alignment:
973 .space 4
974 cr_no_alignment:
975 .space 4
Linux kernel - Deliverables
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