arch/arm/kernel/head.S

   1 /*
   2  *  linux/arch/arm/kernel/head.S
   3  *
   4  *  Copyright (C) 1994-2002 Russell King
   5  *  Copyright (c) 2003 ARM Limited
   6  *  All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  *  Kernel startup code for all 32-bit CPUs
  13  */
  14 #include <linux/linkage.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/assembler.h>
  18 #include <asm/domain.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/asm-offsets.h>
  21 #include <asm/memory.h>
  22 #include <asm/thread_info.h>
  23 #include <asm/system.h>
  24
  25 #ifdef CONFIG_DEBUG_LL
  26 #include <mach/debug-macro.S>
  27 #endif
  28
  29 #if (PHYS_OFFSET & 0x001fffff)
  30 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
  31 #endif
  32
  33 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
  34 #define KERNEL_RAM_PADDR        (PHYS_OFFSET + TEXT_OFFSET)
  35
  36
  37 /*
  38  * swapper_pg_dir is the virtual address of the initial page table.
  39  * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
  40  * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
  41  * the least significant 16 bits to be 0x8000, but we could probably
  42  * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
  43  */
  44 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  45 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  46 #endif
  47
  48         .globl  swapper_pg_dir
  49         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
  50
  51         .macro  pgtbl, rd
  52         ldr     \rd, =(KERNEL_RAM_PADDR - 0x4000)
  53         .endm
  54
  55 #ifdef CONFIG_XIP_KERNEL
  56 #define KERNEL_START    XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
  57 #define KERNEL_END      _edata_loc
  58 #else
  59 #define KERNEL_START    KERNEL_RAM_VADDR
  60 #define KERNEL_END      _end
  61 #endif
  62
  63 /*
  64  * Kernel startup entry point.
  65  * ---------------------------
  66  *
  67  * This is normally called from the decompressor code.  The requirements
  68  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  69  * r1 = machine nr, r2 = atags pointer.
  70  *
  71  * This code is mostly position independent, so if you link the kernel at
  72  * 0xc0008000, you call this at __pa(0xc0008000).
  73  *
  74  * See linux/arch/arm/tools/mach-types for the complete list of machine
  75  * numbers for r1.
  76  *
  77  * We're trying to keep crap to a minimum; DO NOT add any machine specific
  78  * crap here - that's what the boot loader (or in extreme, well justified
  79  * circumstances, zImage) is for.
  80  */
  81         __HEAD
  82 ENTRY(stext)
  83         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
  84                                                 @ and irqs disabled
  85         mrc     p15, 0, r9, c0, c0              @ get processor id
  86         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
  87         movs    r10, r5                         @ invalid processor (r5=0)?
  88  THUMB( it      eq )            @ force fixup-able long branch encoding
  89         beq     __error_p                       @ yes, error 'p'
  90         bl      __lookup_machine_type           @ r5=machinfo
  91         movs    r8, r5                          @ invalid machine (r5=0)?
  92  THUMB( it      eq )            @ force fixup-able long branch encoding
  93         beq     __error_a                       @ yes, error 'a'
  94         bl      __vet_atags
  95 #ifdef CONFIG_SMP_ON_UP
  96         bl      __fixup_smp
  97 #endif
  98         bl      __create_page_tables
  99
 100         /*
 101          * The following calls CPU specific code in a position independent
 102          * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
 103          * xxx_proc_info structure selected by __lookup_machine_type
 104          * above.  On return, the CPU will be ready for the MMU to be
 105          * turned on, and r0 will hold the CPU control register value.
 106          */
 107         ldr     r13, =__mmap_switched           @ address to jump to after
 108                                                 @ mmu has been enabled
 109         adr     lr, BSYM(1f)                    @ return (PIC) address
 110  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
 111  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 112  THUMB( mov     pc, r12                         )
 113 1:      b       __enable_mmu
 114 ENDPROC(stext)
 115         .ltorg
 116
 117 /*
 118  * Setup the initial page tables.  We only setup the barest
 119  * amount which are required to get the kernel running, which
 120  * generally means mapping in the kernel code.
 121  *
 122  * r8  = machinfo
 123  * r9  = cpuid
 124  * r10 = procinfo
 125  *
 126  * Returns:
 127  *  r0, r3, r5-r7 corrupted
 128  *  r4 = physical page table address
 129  */
 130 __create_page_tables:
 131         pgtbl   r4                              @ page table address
 132
 133         /*
 134          * Clear the 16K level 1 swapper page table
 135          */
 136         mov     r0, r4
 137         mov     r3, #0
 138         add     r6, r0, #0x4000
 139 1:      str     r3, [r0], #4
 140         str     r3, [r0], #4
 141         str     r3, [r0], #4
 142         str     r3, [r0], #4
 143         teq     r0, r6
 144         bne     1b
 145
 146         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 147
 148         /*
 149          * Create identity mapping to cater for __enable_mmu.
 150          * This identity mapping will be removed by paging_init().
 151          */
 152         adr     r0, __enable_mmu_loc
 153         ldmia   r0, {r3, r5, r6}
 154         sub     r0, r0, r3                      @ virt->phys offset
 155         add     r5, r5, r0                      @ phys __enable_mmu
 156         add     r6, r6, r0                      @ phys __enable_mmu_end
 157         mov     r5, r5, lsr #20
 158         mov     r6, r6, lsr #20
 159
 160 1:      orr     r3, r7, r5, lsl #20             @ flags + kernel base
 161         str     r3, [r4, r5, lsl #2]            @ identity mapping
 162         teq     r5, r6
 163         addne   r5, r5, #1                      @ next section
 164         bne     1b
 165
 166         /*
 167          * Now setup the pagetables for our kernel direct
 168          * mapped region.
 169          */
 170         mov     r3, pc
 171         mov     r3, r3, lsr #20
 172         orr     r3, r7, r3, lsl #20
 173         add     r0, r4,  #(KERNEL_START & 0xff000000) >> 18
 174         str     r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
 175         ldr     r6, =(KERNEL_END - 1)
 176         add     r0, r0, #4
 177         add     r6, r4, r6, lsr #18
 178 1:      cmp     r0, r6
 179         add     r3, r3, #1 << 20
 180         strls   r3, [r0], #4
 181         bls     1b
 182
 183 #ifdef CONFIG_XIP_KERNEL
 184         /*
 185          * Map some ram to cover our .data and .bss areas.
 186          */
 187         orr     r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
 188         .if     (KERNEL_RAM_PADDR & 0x00f00000)
 189         orr     r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
 190         .endif
 191         add     r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> 18
 192         str     r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
 193         ldr     r6, =(_end - 1)
 194         add     r0, r0, #4
 195         add     r6, r4, r6, lsr #18
 196 1:      cmp     r0, r6
 197         add     r3, r3, #1 << 20
 198         strls   r3, [r0], #4
 199         bls     1b
 200 #endif
 201
 202         /*
 203          * Then map first 1MB of ram in case it contains our boot params.
 204          */
 205         add     r0, r4, #PAGE_OFFSET >> 18
 206         orr     r6, r7, #(PHYS_OFFSET & 0xff000000)
 207         .if     (PHYS_OFFSET & 0x00f00000)
 208         orr     r6, r6, #(PHYS_OFFSET & 0x00f00000)
 209         .endif
 210         str     r6, [r0]
 211
 212 #ifdef CONFIG_DEBUG_LL
 213 #ifndef CONFIG_DEBUG_ICEDCC
 214         /*
 215          * Map in IO space for serial debugging.
 216          * This allows debug messages to be output
 217          * via a serial console before paging_init.
 218          */
 219         addruart r7, r3
 220
 221         mov     r3, r3, lsr #20
 222         mov     r3, r3, lsl #2
 223
 224         add     r0, r4, r3
 225         rsb     r3, r3, #0x4000                 @ PTRS_PER_PGD*sizeof(long)
 226         cmp     r3, #0x0800                     @ limit to 512MB
 227         movhi   r3, #0x0800
 228         add     r6, r0, r3
 229         mov     r3, r7, lsr #20
 230         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 231         orr     r3, r7, r3, lsl #20
 232 1:      str     r3, [r0], #4
 233         add     r3, r3, #1 << 20
 234         teq     r0, r6
 235         bne     1b
 236
 237 #else /* CONFIG_DEBUG_ICEDCC */
 238         /* we don't need any serial debugging mappings for ICEDCC */
 239         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 240 #endif /* !CONFIG_DEBUG_ICEDCC */
 241
 242 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
 243         /*
 244          * If we're using the NetWinder or CATS, we also need to map
 245          * in the 16550-type serial port for the debug messages
 246          */
 247         add     r0, r4, #0xff000000 >> 18
 248         orr     r3, r7, #0x7c000000
 249         str     r3, [r0]
 250 #endif
 251 #ifdef CONFIG_ARCH_RPC
 252         /*
 253          * Map in screen at 0x02000000 & SCREEN2_BASE
 254          * Similar reasons here - for debug.  This is
 255          * only for Acorn RiscPC architectures.
 256          */
 257         add     r0, r4, #0x02000000 >> 18
 258         orr     r3, r7, #0x02000000
 259         str     r3, [r0]
 260         add     r0, r4, #0xd8000000 >> 18
 261         str     r3, [r0]
 262 #endif
 263 #endif
 264         mov     pc, lr
 265 ENDPROC(__create_page_tables)
 266         .ltorg
 267         .align
 268 __enable_mmu_loc:
 269         .long   .
 270         .long   __enable_mmu
 271         .long   __enable_mmu_end
 272
 273 #if defined(CONFIG_SMP)
 274         __CPUINIT
 275 ENTRY(secondary_startup)
 276         /*
 277          * Common entry point for secondary CPUs.
 278          *
 279          * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
 280          * the processor type - there is no need to check the machine type
 281          * as it has already been validated by the primary processor.
 282          */
 283         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
 284         mrc     p15, 0, r9, c0, c0              @ get processor id
 285         bl      __lookup_processor_type
 286         movs    r10, r5                         @ invalid processor?
 287         moveq   r0, #'p'                        @ yes, error 'p'
 288  THUMB( it      eq )            @ force fixup-able long branch encoding
 289         beq     __error_p
 290
 291         /*
 292          * Use the page tables supplied from  __cpu_up.
 293          */
 294         adr     r4, __secondary_data
 295         ldmia   r4, {r5, r7, r12}               @ address to jump to after
 296         sub     r4, r4, r5                      @ mmu has been enabled
 297         ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
 298         adr     lr, BSYM(__enable_mmu)          @ return address
 299         mov     r13, r12                        @ __secondary_switched address
 300  ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
 301                                                   @ (return control reg)
 302  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 303  THUMB( mov     pc, r12                         )
 304 ENDPROC(secondary_startup)
 305
 306         /*
 307          * r6  = &secondary_data
 308          */
 309 ENTRY(__secondary_switched)
 310         ldr     sp, [r7, #4]                    @ get secondary_data.stack
 311         mov     fp, #0
 312         b       secondary_start_kernel
 313 ENDPROC(__secondary_switched)
 314
 315         .align
 316
 317         .type   __secondary_data, %object
 318 __secondary_data:
 319         .long   .
 320         .long   secondary_data
 321         .long   __secondary_switched
 322 #endif /* defined(CONFIG_SMP) */
 323
 324
 325
 326 /*
 327  * Setup common bits before finally enabling the MMU.  Essentially
 328  * this is just loading the page table pointer and domain access
 329  * registers.
 330  *
 331  *  r0  = cp#15 control register
 332  *  r1  = machine ID
 333  *  r2  = atags pointer
 334  *  r4  = page table pointer
 335  *  r9  = processor ID
 336  *  r13 = *virtual* address to jump to upon completion
 337  */
 338 __enable_mmu:
 339 #ifdef CONFIG_ALIGNMENT_TRAP
 340         orr     r0, r0, #CR_A
 341 #else
 342         bic     r0, r0, #CR_A
 343 #endif
 344 #ifdef CONFIG_CPU_DCACHE_DISABLE
 345         bic     r0, r0, #CR_C
 346 #endif
 347 #ifdef CONFIG_CPU_BPREDICT_DISABLE
 348         bic     r0, r0, #CR_Z
 349 #endif
 350 #ifdef CONFIG_CPU_ICACHE_DISABLE
 351         bic     r0, r0, #CR_I
 352 #endif
 353         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 354                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 355                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
 356                       domain_val(DOMAIN_IO, DOMAIN_CLIENT))
 357         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
 358         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
 359         b       __turn_mmu_on
 360 ENDPROC(__enable_mmu)
 361
 362 /*
 363  * Enable the MMU.  This completely changes the structure of the visible
 364  * memory space.  You will not be able to trace execution through this.
 365  * If you have an enquiry about this, *please* check the linux-arm-kernel
 366  * mailing list archives BEFORE sending another post to the list.
 367  *
 368  *  r0  = cp#15 control register
 369  *  r1  = machine ID
 370  *  r2  = atags pointer
 371  *  r9  = processor ID
 372  *  r13 = *virtual* address to jump to upon completion
 373  *
 374  * other registers depend on the function called upon completion
 375  */
 376         .align  5
 377 __turn_mmu_on:
 378         mov     r0, r0
 379         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 380         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
 381         mov     r3, r3
 382         mov     r3, r13
 383         mov     pc, r3
 384 __enable_mmu_end:
 385 ENDPROC(__turn_mmu_on)
 386
 387
 388 #ifdef CONFIG_SMP_ON_UP
 389 __fixup_smp:
 390         mov     r7, #0x00070000
 391         orr     r6, r7, #0xff000000     @ mask 0xff070000
 392         orr     r7, r7, #0x41000000     @ val 0x41070000
 393         and     r0, r9, r6
 394         teq     r0, r7                  @ ARM CPU and ARMv6/v7?
 395         bne     __fixup_smp_on_up       @ no, assume UP
 396
 397         orr     r6, r6, #0x0000ff00
 398         orr     r6, r6, #0x000000f0     @ mask 0xff07fff0
 399         orr     r7, r7, #0x0000b000
 400         orr     r7, r7, #0x00000020     @ val 0x4107b020
 401         and     r0, r9, r6
 402         teq     r0, r7                  @ ARM 11MPCore?
 403         moveq   pc, lr                  @ yes, assume SMP
 404
 405         mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
 406         tst     r0, #1 << 31
 407         movne   pc, lr                  @ bit 31 => SMP
 408
 409 __fixup_smp_on_up:
 410         adr     r0, 1f
 411         ldmia   r0, {r3, r6, r7}
 412         sub     r3, r0, r3
 413         add     r6, r6, r3
 414         add     r7, r7, r3
 415 2:      cmp     r6, r7
 416         ldmia   r6!, {r0, r4}
 417         strlo   r4, [r0, r3]
 418         blo     2b
 419         mov     pc, lr
 420 ENDPROC(__fixup_smp)
 421
 422         .align
 423 1:      .word   .
 424         .word   __smpalt_begin
 425         .word   __smpalt_end
 426
 427         .pushsection .data
 428         .globl  smp_on_up
 429 smp_on_up:
 430         ALT_SMP(.long   1)
 431         ALT_UP(.long    0)
 432         .popsection
 433
 434 #endif
 435
 436 #include "head-common.S"