2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/config.h>
15 #include <linux/linkage.h>
16 #include <linux/init.h>
18 #include <asm/assembler.h>
19 #include <asm/domain.h>
20 #include <asm/mach-types.h>
21 #include <asm/procinfo.h>
22 #include <asm/ptrace.h>
23 #include <asm/asm-offsets.h>
24 #include <asm/memory.h>
25 #include <asm/thread_info.h>
26 #include <asm/system.h>
28 #define PROCINFO_MMUFLAGS 8
29 #define PROCINFO_INITFUNC 12
31 #define MACHINFO_TYPE 0
32 #define MACHINFO_PHYSRAM 4
33 #define MACHINFO_PHYSIO 8
34 #define MACHINFO_PGOFFIO 12
35 #define MACHINFO_NAME 16
37 #ifndef CONFIG_XIP_KERNEL
39 * We place the page tables 16K below TEXTADDR. Therefore, we must make sure
40 * that TEXTADDR is correctly set. Currently, we expect the least significant
41 * 16 bits to be 0x8000, but we could probably relax this restriction to
42 * TEXTADDR >= PAGE_OFFSET + 0x4000
44 * Note that swapper_pg_dir is the virtual address of the page tables, and
45 * pgtbl gives us a position-independent reference to these tables. We can
46 * do this because stext == TEXTADDR
48 #if (TEXTADDR & 0xffff) != 0x8000
49 #error TEXTADDR must start at 0xXXXX8000
53 .equ swapper_pg_dir, TEXTADDR - 0x4000
55 .macro pgtbl, rd, phys
63 * We place the page tables 16K below DATAADDR. Therefore, we must make sure
64 * that DATAADDR is correctly set. Currently, we expect the least significant
65 * 16 bits to be 0x8000, but we could probably relax this restriction to
66 * DATAADDR >= PAGE_OFFSET + 0x4000
68 * Note that pgtbl is meant to return the physical address of swapper_pg_dir.
69 * We can't make it relative to the kernel position in this case since
70 * the kernel can physically be anywhere.
72 #if (DATAADDR & 0xffff) != 0x8000
73 #error DATAADDR must start at 0xXXXX8000
77 .equ swapper_pg_dir, DATAADDR - 0x4000
79 .macro pgtbl, rd, phys
80 ldr \rd, =((DATAADDR - 0x4000) - PAGE_OFFSET)
86 * Kernel startup entry point.
87 * ---------------------------
89 * This is normally called from the decompressor code. The requirements
90 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
93 * This code is mostly position independent, so if you link the kernel at
94 * 0xc0008000, you call this at __pa(0xc0008000).
96 * See linux/arch/arm/tools/mach-types for the complete list of machine
99 * We're trying to keep crap to a minimum; DO NOT add any machine specific
100 * crap here - that's what the boot loader (or in extreme, well justified
101 * circumstances, zImage) is for.
104 .type stext, %function
106 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
108 bl __lookup_processor_type @ r5=procinfo r9=cpuid
109 movs r10, r5 @ invalid processor (r5=0)?
110 beq __error_p @ yes, error 'p'
111 bl __lookup_machine_type @ r5=machinfo
112 movs r8, r5 @ invalid machine (r5=0)?
113 beq __error_a @ yes, error 'a'
114 bl __create_page_tables
117 * The following calls CPU specific code in a position independent
118 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
119 * xxx_proc_info structure selected by __lookup_machine_type
120 * above. On return, the CPU will be ready for the MMU to be
121 * turned on, and r0 will hold the CPU control register value.
123 ldr r13, __switch_data @ address to jump to after
124 @ mmu has been enabled
125 adr lr, __enable_mmu @ return (PIC) address
126 add pc, r10, #PROCINFO_INITFUNC
128 .type __switch_data, %object
130 .long __mmap_switched
131 .long __data_loc @ r4
132 .long __data_start @ r5
133 .long __bss_start @ r6
135 .long processor_id @ r4
136 .long __machine_arch_type @ r5
137 .long cr_alignment @ r6
138 .long init_thread_union + THREAD_START_SP @ sp
141 * The following fragment of code is executed with the MMU on, and uses
142 * absolute addresses; this is not position independent.
144 * r0 = cp#15 control register
148 .type __mmap_switched, %function
150 adr r3, __switch_data + 4
152 ldmia r3!, {r4, r5, r6, r7}
153 cmp r4, r5 @ Copy data segment if needed
159 mov fp, #0 @ Clear BSS (and zero fp)
164 ldmia r3, {r4, r5, r6, sp}
165 str r9, [r4] @ Save processor ID
166 str r1, [r5] @ Save machine type
167 bic r4, r0, #CR_A @ Clear 'A' bit
168 stmia r6, {r0, r4} @ Save control register values
171 #if defined(CONFIG_SMP)
172 .type secondary_startup, #function
173 ENTRY(secondary_startup)
175 * Common entry point for secondary CPUs.
177 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
178 * the processor type - there is no need to check the machine type
179 * as it has already been validated by the primary processor.
181 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
182 bl __lookup_processor_type
183 movs r10, r5 @ invalid processor?
184 moveq r0, #'p' @ yes, error 'p'
188 * Use the page tables supplied from __cpu_up.
190 adr r4, __secondary_data
191 ldmia r4, {r5, r6, r13} @ address to jump to after
192 sub r4, r4, r5 @ mmu has been enabled
193 ldr r4, [r6, r4] @ get secondary_data.pgdir
194 adr lr, __enable_mmu @ return address
195 add pc, r10, #12 @ initialise processor
196 @ (return control reg)
199 * r6 = &secondary_data
201 ENTRY(__secondary_switched)
202 ldr sp, [r6, #4] @ get secondary_data.stack
204 b secondary_start_kernel
206 .type __secondary_data, %object
210 .long __secondary_switched
211 #endif /* defined(CONFIG_SMP) */
216 * Setup common bits before finally enabling the MMU. Essentially
217 * this is just loading the page table pointer and domain access
220 .type __enable_mmu, %function
222 #ifdef CONFIG_ALIGNMENT_TRAP
227 #ifdef CONFIG_CPU_DCACHE_DISABLE
230 #ifdef CONFIG_CPU_BPREDICT_DISABLE
233 #ifdef CONFIG_CPU_ICACHE_DISABLE
236 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
237 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
238 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
239 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
240 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
241 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
245 * Enable the MMU. This completely changes the structure of the visible
246 * memory space. You will not be able to trace execution through this.
247 * If you have an enquiry about this, *please* check the linux-arm-kernel
248 * mailing list archives BEFORE sending another post to the list.
250 * r0 = cp#15 control register
251 * r13 = *virtual* address to jump to upon completion
253 * other registers depend on the function called upon completion
256 .type __turn_mmu_on, %function
259 mcr p15, 0, r0, c1, c0, 0 @ write control reg
260 mrc p15, 0, r3, c0, c0, 0 @ read id reg
268 * Setup the initial page tables. We only setup the barest
269 * amount which are required to get the kernel running, which
270 * generally means mapping in the kernel code.
277 * r0, r3, r5, r6, r7 corrupted
278 * r4 = physical page table address
280 .type __create_page_tables, %function
281 __create_page_tables:
282 ldr r5, [r8, #MACHINFO_PHYSRAM] @ physram
283 pgtbl r4, r5 @ page table address
286 * Clear the 16K level 1 swapper page table
298 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags
301 * Create identity mapping for first MB of kernel to
302 * cater for the MMU enable. This identity mapping
303 * will be removed by paging_init(). We use our current program
304 * counter to determine corresponding section base address.
306 mov r6, pc, lsr #20 @ start of kernel section
307 orr r3, r7, r6, lsl #20 @ flags + kernel base
308 str r3, [r4, r6, lsl #2] @ identity mapping
311 * Now setup the pagetables for our kernel direct
312 * mapped region. We round TEXTADDR down to the
313 * nearest megabyte boundary. It is assumed that
314 * the kernel fits within 4 contigous 1MB sections.
316 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
317 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
319 str r3, [r0, #4]! @ KERNEL + 1MB
321 str r3, [r0, #4]! @ KERNEL + 2MB
323 str r3, [r0, #4] @ KERNEL + 3MB
326 * Then map first 1MB of ram in case it contains our boot params.
328 add r0, r4, #PAGE_OFFSET >> 18
332 #ifdef CONFIG_XIP_KERNEL
334 * Map some ram to cover our .data and .bss areas.
335 * Mapping 3MB should be plenty.
339 add r0, r0, r3, lsl #2
340 add r6, r6, r3, lsl #20
342 add r6, r6, #(1 << 20)
344 add r6, r6, #(1 << 20)
348 #ifdef CONFIG_DEBUG_LL
349 bic r7, r7, #0x0c @ turn off cacheable
350 @ and bufferable bits
352 * Map in IO space for serial debugging.
353 * This allows debug messages to be output
354 * via a serial console before paging_init.
356 ldr r3, [r8, #MACHINFO_PGOFFIO]
358 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
359 cmp r3, #0x0800 @ limit to 512MB
362 ldr r3, [r8, #MACHINFO_PHYSIO]
368 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
370 * If we're using the NetWinder, we need to map in
371 * the 16550-type serial port for the debug messages
373 teq r1, #MACH_TYPE_NETWINDER
374 teqne r1, #MACH_TYPE_CATS
376 add r0, r4, #0xff000000 >> 18
377 orr r3, r7, #0x7c000000
381 #ifdef CONFIG_ARCH_RPC
383 * Map in screen at 0x02000000 & SCREEN2_BASE
384 * Similar reasons here - for debug. This is
385 * only for Acorn RiscPC architectures.
387 add r0, r4, #0x02000000 >> 18
388 orr r3, r7, #0x02000000
390 add r0, r4, #0xd8000000 >> 18
400 * Exception handling. Something went wrong and we can't proceed. We
401 * ought to tell the user, but since we don't have any guarantee that
402 * we're even running on the right architecture, we do virtually nothing.
404 * If CONFIG_DEBUG_LL is set we try to print out something about the error
405 * and hope for the best (useful if bootloader fails to pass a proper
406 * machine ID for example).
409 .type __error_p, %function
411 #ifdef CONFIG_DEBUG_LL
415 str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
419 .type __error_a, %function
421 #ifdef CONFIG_DEBUG_LL
422 mov r4, r1 @ preserve machine ID
430 ldmia r3, {r4, r5, r6} @ get machine desc list
431 sub r4, r3, r4 @ get offset between virt&phys
432 add r5, r5, r4 @ convert virt addresses to
433 add r6, r6, r4 @ physical address space
434 1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type
438 ldr r0, [r5, #MACHINFO_NAME] @ get machine name
443 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
449 str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x"
450 str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n"
451 str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n"
455 .type __error, %function
457 #ifdef CONFIG_ARCH_RPC
459 * Turn the screen red on a error - RiscPC only.
463 orr r3, r3, r3, lsl #8
464 orr r3, r3, r3, lsl #16
475 * Read processor ID register (CP#15, CR0), and look up in the linker-built
476 * supported processor list. Note that we can't use the absolute addresses
477 * for the __proc_info lists since we aren't running with the MMU on
478 * (and therefore, we are not in the correct address space). We have to
479 * calculate the offset.
482 * r3, r4, r6 corrupted
483 * r5 = proc_info pointer in physical address space
486 .type __lookup_processor_type, %function
487 __lookup_processor_type:
489 ldmda r3, {r5, r6, r9}
490 sub r3, r3, r9 @ get offset between virt&phys
491 add r5, r5, r3 @ convert virt addresses to
492 add r6, r6, r3 @ physical address space
493 mrc p15, 0, r9, c0, c0 @ get processor id
494 1: ldmia r5, {r3, r4} @ value, mask
495 and r4, r4, r9 @ mask wanted bits
498 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
501 mov r5, #0 @ unknown processor
505 * This provides a C-API version of the above function.
507 ENTRY(lookup_processor_type)
508 stmfd sp!, {r4 - r6, r9, lr}
509 bl __lookup_processor_type
511 ldmfd sp!, {r4 - r6, r9, pc}
514 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
515 * more information about the __proc_info and __arch_info structures.
517 .long __proc_info_begin
518 .long __proc_info_end
520 .long __arch_info_begin
521 .long __arch_info_end
524 * Lookup machine architecture in the linker-build list of architectures.
525 * Note that we can't use the absolute addresses for the __arch_info
526 * lists since we aren't running with the MMU on (and therefore, we are
527 * not in the correct address space). We have to calculate the offset.
529 * r1 = machine architecture number
531 * r3, r4, r6 corrupted
532 * r5 = mach_info pointer in physical address space
534 .type __lookup_machine_type, %function
535 __lookup_machine_type:
537 ldmia r3, {r4, r5, r6}
538 sub r3, r3, r4 @ get offset between virt&phys
539 add r5, r5, r3 @ convert virt addresses to
540 add r6, r6, r3 @ physical address space
541 1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type
542 teq r3, r1 @ matches loader number?
544 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
547 mov r5, #0 @ unknown machine
551 * This provides a C-API version of the above function.
553 ENTRY(lookup_machine_type)
554 stmfd sp!, {r4 - r6, lr}
556 bl __lookup_machine_type
558 ldmfd sp!, {r4 - r6, pc}