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Merge tag 'at91-for-next-dt' of git://github.com/at91linux/linux-at91 into next/dt
[deliverable/linux.git] / arch / arm / mach-at91 / at91rm9200_devices.c
1 /*
2 * arch/arm/mach-at91/at91rm9200_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15
16 #include <linux/dma-mapping.h>
17 #include <linux/gpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20
21 #include <mach/board.h>
22 #include <mach/at91rm9200.h>
23 #include <mach/at91rm9200_mc.h>
24 #include <mach/at91_ramc.h>
25
26 #include "generic.h"
27
28
29 /* --------------------------------------------------------------------
30 * USB Host
31 * -------------------------------------------------------------------- */
32
33 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
34 static u64 ohci_dmamask = DMA_BIT_MASK(32);
35 static struct at91_usbh_data usbh_data;
36
37 static struct resource usbh_resources[] = {
38 [0] = {
39 .start = AT91RM9200_UHP_BASE,
40 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .start = AT91RM9200_ID_UHP,
45 .end = AT91RM9200_ID_UHP,
46 .flags = IORESOURCE_IRQ,
47 },
48 };
49
50 static struct platform_device at91rm9200_usbh_device = {
51 .name = "at91_ohci",
52 .id = -1,
53 .dev = {
54 .dma_mask = &ohci_dmamask,
55 .coherent_dma_mask = DMA_BIT_MASK(32),
56 .platform_data = &usbh_data,
57 },
58 .resource = usbh_resources,
59 .num_resources = ARRAY_SIZE(usbh_resources),
60 };
61
62 void __init at91_add_device_usbh(struct at91_usbh_data *data)
63 {
64 int i;
65
66 if (!data)
67 return;
68
69 /* Enable overcurrent notification */
70 for (i = 0; i < data->ports; i++) {
71 if (data->overcurrent_pin[i])
72 at91_set_gpio_input(data->overcurrent_pin[i], 1);
73 }
74
75 usbh_data = *data;
76 platform_device_register(&at91rm9200_usbh_device);
77 }
78 #else
79 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
80 #endif
81
82
83 /* --------------------------------------------------------------------
84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */
86
87 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
88 static struct at91_udc_data udc_data;
89
90 static struct resource udc_resources[] = {
91 [0] = {
92 .start = AT91RM9200_BASE_UDP,
93 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91RM9200_ID_UDP,
98 .end = AT91RM9200_ID_UDP,
99 .flags = IORESOURCE_IRQ,
100 },
101 };
102
103 static struct platform_device at91rm9200_udc_device = {
104 .name = "at91_udc",
105 .id = -1,
106 .dev = {
107 .platform_data = &udc_data,
108 },
109 .resource = udc_resources,
110 .num_resources = ARRAY_SIZE(udc_resources),
111 };
112
113 void __init at91_add_device_udc(struct at91_udc_data *data)
114 {
115 if (!data)
116 return;
117
118 if (gpio_is_valid(data->vbus_pin)) {
119 at91_set_gpio_input(data->vbus_pin, 0);
120 at91_set_deglitch(data->vbus_pin, 1);
121 }
122 if (gpio_is_valid(data->pullup_pin))
123 at91_set_gpio_output(data->pullup_pin, 0);
124
125 udc_data = *data;
126 platform_device_register(&at91rm9200_udc_device);
127 }
128 #else
129 void __init at91_add_device_udc(struct at91_udc_data *data) {}
130 #endif
131
132
133 /* --------------------------------------------------------------------
134 * Ethernet
135 * -------------------------------------------------------------------- */
136
137 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
138 static u64 eth_dmamask = DMA_BIT_MASK(32);
139 static struct macb_platform_data eth_data;
140
141 static struct resource eth_resources[] = {
142 [0] = {
143 .start = AT91_VA_BASE_EMAC,
144 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = AT91RM9200_ID_EMAC,
149 .end = AT91RM9200_ID_EMAC,
150 .flags = IORESOURCE_IRQ,
151 },
152 };
153
154 static struct platform_device at91rm9200_eth_device = {
155 .name = "at91_ether",
156 .id = -1,
157 .dev = {
158 .dma_mask = &eth_dmamask,
159 .coherent_dma_mask = DMA_BIT_MASK(32),
160 .platform_data = &eth_data,
161 },
162 .resource = eth_resources,
163 .num_resources = ARRAY_SIZE(eth_resources),
164 };
165
166 void __init at91_add_device_eth(struct macb_platform_data *data)
167 {
168 if (!data)
169 return;
170
171 if (gpio_is_valid(data->phy_irq_pin)) {
172 at91_set_gpio_input(data->phy_irq_pin, 0);
173 at91_set_deglitch(data->phy_irq_pin, 1);
174 }
175
176 /* Pins used for MII and RMII */
177 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
178 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
179 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
180 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
181 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
182 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
183 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
184 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
185 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
186 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
187
188 if (!data->is_rmii) {
189 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
190 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
191 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
192 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
193 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
194 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
195 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
196 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
197 }
198
199 eth_data = *data;
200 platform_device_register(&at91rm9200_eth_device);
201 }
202 #else
203 void __init at91_add_device_eth(struct macb_platform_data *data) {}
204 #endif
205
206
207 /* --------------------------------------------------------------------
208 * Compact Flash / PCMCIA
209 * -------------------------------------------------------------------- */
210
211 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
212 static struct at91_cf_data cf_data;
213
214 #define CF_BASE AT91_CHIPSELECT_4
215
216 static struct resource cf_resources[] = {
217 [0] = {
218 .start = CF_BASE,
219 /* ties up CS4, CS5 and CS6 */
220 .end = CF_BASE + (0x30000000 - 1),
221 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
222 },
223 };
224
225 static struct platform_device at91rm9200_cf_device = {
226 .name = "at91_cf",
227 .id = -1,
228 .dev = {
229 .platform_data = &cf_data,
230 },
231 .resource = cf_resources,
232 .num_resources = ARRAY_SIZE(cf_resources),
233 };
234
235 void __init at91_add_device_cf(struct at91_cf_data *data)
236 {
237 unsigned int csa;
238
239 if (!data)
240 return;
241
242 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
243
244 /* CF takes over CS4, CS5, CS6 */
245 csa = at91_ramc_read(0, AT91_EBI_CSA);
246 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
247
248 /*
249 * Static memory controller timing adjustments.
250 * REVISIT: these timings are in terms of MCK cycles, so
251 * when MCK changes (cpufreq etc) so must these values...
252 */
253 at91_ramc_write(0, AT91_SMC_CSR(4),
254 AT91_SMC_ACSS_STD
255 | AT91_SMC_DBW_16
256 | AT91_SMC_BAT
257 | AT91_SMC_WSEN
258 | AT91_SMC_NWS_(32) /* wait states */
259 | AT91_SMC_RWSETUP_(6) /* setup time */
260 | AT91_SMC_RWHOLD_(4) /* hold time */
261 );
262
263 /* input/irq */
264 if (gpio_is_valid(data->irq_pin)) {
265 at91_set_gpio_input(data->irq_pin, 1);
266 at91_set_deglitch(data->irq_pin, 1);
267 }
268 at91_set_gpio_input(data->det_pin, 1);
269 at91_set_deglitch(data->det_pin, 1);
270
271 /* outputs, initially off */
272 if (gpio_is_valid(data->vcc_pin))
273 at91_set_gpio_output(data->vcc_pin, 0);
274 at91_set_gpio_output(data->rst_pin, 0);
275
276 /* force poweron defaults for these pins ... */
277 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
278 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
279 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
280 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
281
282 /* nWAIT is _not_ a default setting */
283 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
284
285 cf_data = *data;
286 platform_device_register(&at91rm9200_cf_device);
287 }
288 #else
289 void __init at91_add_device_cf(struct at91_cf_data *data) {}
290 #endif
291
292
293 /* --------------------------------------------------------------------
294 * MMC / SD
295 * -------------------------------------------------------------------- */
296
297 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
298 static u64 mmc_dmamask = DMA_BIT_MASK(32);
299 static struct at91_mmc_data mmc_data;
300
301 static struct resource mmc_resources[] = {
302 [0] = {
303 .start = AT91RM9200_BASE_MCI,
304 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
308 .start = AT91RM9200_ID_MCI,
309 .end = AT91RM9200_ID_MCI,
310 .flags = IORESOURCE_IRQ,
311 },
312 };
313
314 static struct platform_device at91rm9200_mmc_device = {
315 .name = "at91_mci",
316 .id = -1,
317 .dev = {
318 .dma_mask = &mmc_dmamask,
319 .coherent_dma_mask = DMA_BIT_MASK(32),
320 .platform_data = &mmc_data,
321 },
322 .resource = mmc_resources,
323 .num_resources = ARRAY_SIZE(mmc_resources),
324 };
325
326 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
327 {
328 if (!data)
329 return;
330
331 /* input/irq */
332 if (gpio_is_valid(data->det_pin)) {
333 at91_set_gpio_input(data->det_pin, 1);
334 at91_set_deglitch(data->det_pin, 1);
335 }
336 if (gpio_is_valid(data->wp_pin))
337 at91_set_gpio_input(data->wp_pin, 1);
338 if (gpio_is_valid(data->vcc_pin))
339 at91_set_gpio_output(data->vcc_pin, 0);
340
341 /* CLK */
342 at91_set_A_periph(AT91_PIN_PA27, 0);
343
344 if (data->slot_b) {
345 /* CMD */
346 at91_set_B_periph(AT91_PIN_PA8, 1);
347
348 /* DAT0, maybe DAT1..DAT3 */
349 at91_set_B_periph(AT91_PIN_PA9, 1);
350 if (data->wire4) {
351 at91_set_B_periph(AT91_PIN_PA10, 1);
352 at91_set_B_periph(AT91_PIN_PA11, 1);
353 at91_set_B_periph(AT91_PIN_PA12, 1);
354 }
355 } else {
356 /* CMD */
357 at91_set_A_periph(AT91_PIN_PA28, 1);
358
359 /* DAT0, maybe DAT1..DAT3 */
360 at91_set_A_periph(AT91_PIN_PA29, 1);
361 if (data->wire4) {
362 at91_set_B_periph(AT91_PIN_PB3, 1);
363 at91_set_B_periph(AT91_PIN_PB4, 1);
364 at91_set_B_periph(AT91_PIN_PB5, 1);
365 }
366 }
367
368 mmc_data = *data;
369 platform_device_register(&at91rm9200_mmc_device);
370 }
371 #else
372 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
373 #endif
374
375
376 /* --------------------------------------------------------------------
377 * NAND / SmartMedia
378 * -------------------------------------------------------------------- */
379
380 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
381 static struct atmel_nand_data nand_data;
382
383 #define NAND_BASE AT91_CHIPSELECT_3
384
385 static struct resource nand_resources[] = {
386 {
387 .start = NAND_BASE,
388 .end = NAND_BASE + SZ_256M - 1,
389 .flags = IORESOURCE_MEM,
390 }
391 };
392
393 static struct platform_device at91rm9200_nand_device = {
394 .name = "atmel_nand",
395 .id = -1,
396 .dev = {
397 .platform_data = &nand_data,
398 },
399 .resource = nand_resources,
400 .num_resources = ARRAY_SIZE(nand_resources),
401 };
402
403 void __init at91_add_device_nand(struct atmel_nand_data *data)
404 {
405 unsigned int csa;
406
407 if (!data)
408 return;
409
410 /* enable the address range of CS3 */
411 csa = at91_ramc_read(0, AT91_EBI_CSA);
412 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
413
414 /* set the bus interface characteristics */
415 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
416 | AT91_SMC_NWS_(5)
417 | AT91_SMC_TDF_(1)
418 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
419 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
420 );
421
422 /* enable pin */
423 if (gpio_is_valid(data->enable_pin))
424 at91_set_gpio_output(data->enable_pin, 1);
425
426 /* ready/busy pin */
427 if (gpio_is_valid(data->rdy_pin))
428 at91_set_gpio_input(data->rdy_pin, 1);
429
430 /* card detect pin */
431 if (gpio_is_valid(data->det_pin))
432 at91_set_gpio_input(data->det_pin, 1);
433
434 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
435 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
436
437 nand_data = *data;
438 platform_device_register(&at91rm9200_nand_device);
439 }
440 #else
441 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
442 #endif
443
444
445 /* --------------------------------------------------------------------
446 * TWI (i2c)
447 * -------------------------------------------------------------------- */
448
449 /*
450 * Prefer the GPIO code since the TWI controller isn't robust
451 * (gets overruns and underruns under load) and can only issue
452 * repeated STARTs in one scenario (the driver doesn't yet handle them).
453 */
454 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
455
456 static struct i2c_gpio_platform_data pdata = {
457 .sda_pin = AT91_PIN_PA25,
458 .sda_is_open_drain = 1,
459 .scl_pin = AT91_PIN_PA26,
460 .scl_is_open_drain = 1,
461 .udelay = 2, /* ~100 kHz */
462 };
463
464 static struct platform_device at91rm9200_twi_device = {
465 .name = "i2c-gpio",
466 .id = -1,
467 .dev.platform_data = &pdata,
468 };
469
470 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
471 {
472 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
473 at91_set_multi_drive(AT91_PIN_PA25, 1);
474
475 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
476 at91_set_multi_drive(AT91_PIN_PA26, 1);
477
478 i2c_register_board_info(0, devices, nr_devices);
479 platform_device_register(&at91rm9200_twi_device);
480 }
481
482 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
483
484 static struct resource twi_resources[] = {
485 [0] = {
486 .start = AT91RM9200_BASE_TWI,
487 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
488 .flags = IORESOURCE_MEM,
489 },
490 [1] = {
491 .start = AT91RM9200_ID_TWI,
492 .end = AT91RM9200_ID_TWI,
493 .flags = IORESOURCE_IRQ,
494 },
495 };
496
497 static struct platform_device at91rm9200_twi_device = {
498 .name = "at91_i2c",
499 .id = -1,
500 .resource = twi_resources,
501 .num_resources = ARRAY_SIZE(twi_resources),
502 };
503
504 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
505 {
506 /* pins used for TWI interface */
507 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
508 at91_set_multi_drive(AT91_PIN_PA25, 1);
509
510 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
511 at91_set_multi_drive(AT91_PIN_PA26, 1);
512
513 i2c_register_board_info(0, devices, nr_devices);
514 platform_device_register(&at91rm9200_twi_device);
515 }
516 #else
517 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
518 #endif
519
520
521 /* --------------------------------------------------------------------
522 * SPI
523 * -------------------------------------------------------------------- */
524
525 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
526 static u64 spi_dmamask = DMA_BIT_MASK(32);
527
528 static struct resource spi_resources[] = {
529 [0] = {
530 .start = AT91RM9200_BASE_SPI,
531 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
532 .flags = IORESOURCE_MEM,
533 },
534 [1] = {
535 .start = AT91RM9200_ID_SPI,
536 .end = AT91RM9200_ID_SPI,
537 .flags = IORESOURCE_IRQ,
538 },
539 };
540
541 static struct platform_device at91rm9200_spi_device = {
542 .name = "atmel_spi",
543 .id = 0,
544 .dev = {
545 .dma_mask = &spi_dmamask,
546 .coherent_dma_mask = DMA_BIT_MASK(32),
547 },
548 .resource = spi_resources,
549 .num_resources = ARRAY_SIZE(spi_resources),
550 };
551
552 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
553
554 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
555 {
556 int i;
557 unsigned long cs_pin;
558
559 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
560 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
561 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
562
563 /* Enable SPI chip-selects */
564 for (i = 0; i < nr_devices; i++) {
565 if (devices[i].controller_data)
566 cs_pin = (unsigned long) devices[i].controller_data;
567 else
568 cs_pin = spi_standard_cs[devices[i].chip_select];
569
570 if (devices[i].chip_select == 0) /* for CS0 errata */
571 at91_set_A_periph(cs_pin, 0);
572 else
573 at91_set_gpio_output(cs_pin, 1);
574
575
576 /* pass chip-select pin to driver */
577 devices[i].controller_data = (void *) cs_pin;
578 }
579
580 spi_register_board_info(devices, nr_devices);
581 platform_device_register(&at91rm9200_spi_device);
582 }
583 #else
584 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
585 #endif
586
587
588 /* --------------------------------------------------------------------
589 * Timer/Counter blocks
590 * -------------------------------------------------------------------- */
591
592 #ifdef CONFIG_ATMEL_TCLIB
593
594 static struct resource tcb0_resources[] = {
595 [0] = {
596 .start = AT91RM9200_BASE_TCB0,
597 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
598 .flags = IORESOURCE_MEM,
599 },
600 [1] = {
601 .start = AT91RM9200_ID_TC0,
602 .end = AT91RM9200_ID_TC0,
603 .flags = IORESOURCE_IRQ,
604 },
605 [2] = {
606 .start = AT91RM9200_ID_TC1,
607 .end = AT91RM9200_ID_TC1,
608 .flags = IORESOURCE_IRQ,
609 },
610 [3] = {
611 .start = AT91RM9200_ID_TC2,
612 .end = AT91RM9200_ID_TC2,
613 .flags = IORESOURCE_IRQ,
614 },
615 };
616
617 static struct platform_device at91rm9200_tcb0_device = {
618 .name = "atmel_tcb",
619 .id = 0,
620 .resource = tcb0_resources,
621 .num_resources = ARRAY_SIZE(tcb0_resources),
622 };
623
624 static struct resource tcb1_resources[] = {
625 [0] = {
626 .start = AT91RM9200_BASE_TCB1,
627 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 [1] = {
631 .start = AT91RM9200_ID_TC3,
632 .end = AT91RM9200_ID_TC3,
633 .flags = IORESOURCE_IRQ,
634 },
635 [2] = {
636 .start = AT91RM9200_ID_TC4,
637 .end = AT91RM9200_ID_TC4,
638 .flags = IORESOURCE_IRQ,
639 },
640 [3] = {
641 .start = AT91RM9200_ID_TC5,
642 .end = AT91RM9200_ID_TC5,
643 .flags = IORESOURCE_IRQ,
644 },
645 };
646
647 static struct platform_device at91rm9200_tcb1_device = {
648 .name = "atmel_tcb",
649 .id = 1,
650 .resource = tcb1_resources,
651 .num_resources = ARRAY_SIZE(tcb1_resources),
652 };
653
654 static void __init at91_add_device_tc(void)
655 {
656 platform_device_register(&at91rm9200_tcb0_device);
657 platform_device_register(&at91rm9200_tcb1_device);
658 }
659 #else
660 static void __init at91_add_device_tc(void) { }
661 #endif
662
663
664 /* --------------------------------------------------------------------
665 * RTC
666 * -------------------------------------------------------------------- */
667
668 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
669 static struct resource rtc_resources[] = {
670 [0] = {
671 .start = AT91RM9200_BASE_RTC,
672 .end = AT91RM9200_BASE_RTC + SZ_256 - 1,
673 .flags = IORESOURCE_MEM,
674 },
675 [1] = {
676 .start = AT91_ID_SYS,
677 .end = AT91_ID_SYS,
678 .flags = IORESOURCE_IRQ,
679 },
680 };
681
682 static struct platform_device at91rm9200_rtc_device = {
683 .name = "at91_rtc",
684 .id = -1,
685 .resource = rtc_resources,
686 .num_resources = ARRAY_SIZE(rtc_resources),
687 };
688
689 static void __init at91_add_device_rtc(void)
690 {
691 platform_device_register(&at91rm9200_rtc_device);
692 }
693 #else
694 static void __init at91_add_device_rtc(void) {}
695 #endif
696
697
698 /* --------------------------------------------------------------------
699 * Watchdog
700 * -------------------------------------------------------------------- */
701
702 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
703 static struct platform_device at91rm9200_wdt_device = {
704 .name = "at91_wdt",
705 .id = -1,
706 .num_resources = 0,
707 };
708
709 static void __init at91_add_device_watchdog(void)
710 {
711 platform_device_register(&at91rm9200_wdt_device);
712 }
713 #else
714 static void __init at91_add_device_watchdog(void) {}
715 #endif
716
717
718 /* --------------------------------------------------------------------
719 * SSC -- Synchronous Serial Controller
720 * -------------------------------------------------------------------- */
721
722 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
723 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
724
725 static struct resource ssc0_resources[] = {
726 [0] = {
727 .start = AT91RM9200_BASE_SSC0,
728 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
729 .flags = IORESOURCE_MEM,
730 },
731 [1] = {
732 .start = AT91RM9200_ID_SSC0,
733 .end = AT91RM9200_ID_SSC0,
734 .flags = IORESOURCE_IRQ,
735 },
736 };
737
738 static struct platform_device at91rm9200_ssc0_device = {
739 .name = "ssc",
740 .id = 0,
741 .dev = {
742 .dma_mask = &ssc0_dmamask,
743 .coherent_dma_mask = DMA_BIT_MASK(32),
744 },
745 .resource = ssc0_resources,
746 .num_resources = ARRAY_SIZE(ssc0_resources),
747 };
748
749 static inline void configure_ssc0_pins(unsigned pins)
750 {
751 if (pins & ATMEL_SSC_TF)
752 at91_set_A_periph(AT91_PIN_PB0, 1);
753 if (pins & ATMEL_SSC_TK)
754 at91_set_A_periph(AT91_PIN_PB1, 1);
755 if (pins & ATMEL_SSC_TD)
756 at91_set_A_periph(AT91_PIN_PB2, 1);
757 if (pins & ATMEL_SSC_RD)
758 at91_set_A_periph(AT91_PIN_PB3, 1);
759 if (pins & ATMEL_SSC_RK)
760 at91_set_A_periph(AT91_PIN_PB4, 1);
761 if (pins & ATMEL_SSC_RF)
762 at91_set_A_periph(AT91_PIN_PB5, 1);
763 }
764
765 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
766
767 static struct resource ssc1_resources[] = {
768 [0] = {
769 .start = AT91RM9200_BASE_SSC1,
770 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
771 .flags = IORESOURCE_MEM,
772 },
773 [1] = {
774 .start = AT91RM9200_ID_SSC1,
775 .end = AT91RM9200_ID_SSC1,
776 .flags = IORESOURCE_IRQ,
777 },
778 };
779
780 static struct platform_device at91rm9200_ssc1_device = {
781 .name = "ssc",
782 .id = 1,
783 .dev = {
784 .dma_mask = &ssc1_dmamask,
785 .coherent_dma_mask = DMA_BIT_MASK(32),
786 },
787 .resource = ssc1_resources,
788 .num_resources = ARRAY_SIZE(ssc1_resources),
789 };
790
791 static inline void configure_ssc1_pins(unsigned pins)
792 {
793 if (pins & ATMEL_SSC_TF)
794 at91_set_A_periph(AT91_PIN_PB6, 1);
795 if (pins & ATMEL_SSC_TK)
796 at91_set_A_periph(AT91_PIN_PB7, 1);
797 if (pins & ATMEL_SSC_TD)
798 at91_set_A_periph(AT91_PIN_PB8, 1);
799 if (pins & ATMEL_SSC_RD)
800 at91_set_A_periph(AT91_PIN_PB9, 1);
801 if (pins & ATMEL_SSC_RK)
802 at91_set_A_periph(AT91_PIN_PB10, 1);
803 if (pins & ATMEL_SSC_RF)
804 at91_set_A_periph(AT91_PIN_PB11, 1);
805 }
806
807 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
808
809 static struct resource ssc2_resources[] = {
810 [0] = {
811 .start = AT91RM9200_BASE_SSC2,
812 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
813 .flags = IORESOURCE_MEM,
814 },
815 [1] = {
816 .start = AT91RM9200_ID_SSC2,
817 .end = AT91RM9200_ID_SSC2,
818 .flags = IORESOURCE_IRQ,
819 },
820 };
821
822 static struct platform_device at91rm9200_ssc2_device = {
823 .name = "ssc",
824 .id = 2,
825 .dev = {
826 .dma_mask = &ssc2_dmamask,
827 .coherent_dma_mask = DMA_BIT_MASK(32),
828 },
829 .resource = ssc2_resources,
830 .num_resources = ARRAY_SIZE(ssc2_resources),
831 };
832
833 static inline void configure_ssc2_pins(unsigned pins)
834 {
835 if (pins & ATMEL_SSC_TF)
836 at91_set_A_periph(AT91_PIN_PB12, 1);
837 if (pins & ATMEL_SSC_TK)
838 at91_set_A_periph(AT91_PIN_PB13, 1);
839 if (pins & ATMEL_SSC_TD)
840 at91_set_A_periph(AT91_PIN_PB14, 1);
841 if (pins & ATMEL_SSC_RD)
842 at91_set_A_periph(AT91_PIN_PB15, 1);
843 if (pins & ATMEL_SSC_RK)
844 at91_set_A_periph(AT91_PIN_PB16, 1);
845 if (pins & ATMEL_SSC_RF)
846 at91_set_A_periph(AT91_PIN_PB17, 1);
847 }
848
849 /*
850 * SSC controllers are accessed through library code, instead of any
851 * kind of all-singing/all-dancing driver. For example one could be
852 * used by a particular I2S audio codec's driver, while another one
853 * on the same system might be used by a custom data capture driver.
854 */
855 void __init at91_add_device_ssc(unsigned id, unsigned pins)
856 {
857 struct platform_device *pdev;
858
859 /*
860 * NOTE: caller is responsible for passing information matching
861 * "pins" to whatever will be using each particular controller.
862 */
863 switch (id) {
864 case AT91RM9200_ID_SSC0:
865 pdev = &at91rm9200_ssc0_device;
866 configure_ssc0_pins(pins);
867 break;
868 case AT91RM9200_ID_SSC1:
869 pdev = &at91rm9200_ssc1_device;
870 configure_ssc1_pins(pins);
871 break;
872 case AT91RM9200_ID_SSC2:
873 pdev = &at91rm9200_ssc2_device;
874 configure_ssc2_pins(pins);
875 break;
876 default:
877 return;
878 }
879
880 platform_device_register(pdev);
881 }
882
883 #else
884 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
885 #endif
886
887
888 /* --------------------------------------------------------------------
889 * UART
890 * -------------------------------------------------------------------- */
891
892 #if defined(CONFIG_SERIAL_ATMEL)
893 static struct resource dbgu_resources[] = {
894 [0] = {
895 .start = AT91RM9200_BASE_DBGU,
896 .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
897 .flags = IORESOURCE_MEM,
898 },
899 [1] = {
900 .start = AT91_ID_SYS,
901 .end = AT91_ID_SYS,
902 .flags = IORESOURCE_IRQ,
903 },
904 };
905
906 static struct atmel_uart_data dbgu_data = {
907 .use_dma_tx = 0,
908 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
909 };
910
911 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
912
913 static struct platform_device at91rm9200_dbgu_device = {
914 .name = "atmel_usart",
915 .id = 0,
916 .dev = {
917 .dma_mask = &dbgu_dmamask,
918 .coherent_dma_mask = DMA_BIT_MASK(32),
919 .platform_data = &dbgu_data,
920 },
921 .resource = dbgu_resources,
922 .num_resources = ARRAY_SIZE(dbgu_resources),
923 };
924
925 static inline void configure_dbgu_pins(void)
926 {
927 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
928 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
929 }
930
931 static struct resource uart0_resources[] = {
932 [0] = {
933 .start = AT91RM9200_BASE_US0,
934 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
935 .flags = IORESOURCE_MEM,
936 },
937 [1] = {
938 .start = AT91RM9200_ID_US0,
939 .end = AT91RM9200_ID_US0,
940 .flags = IORESOURCE_IRQ,
941 },
942 };
943
944 static struct atmel_uart_data uart0_data = {
945 .use_dma_tx = 1,
946 .use_dma_rx = 1,
947 };
948
949 static u64 uart0_dmamask = DMA_BIT_MASK(32);
950
951 static struct platform_device at91rm9200_uart0_device = {
952 .name = "atmel_usart",
953 .id = 1,
954 .dev = {
955 .dma_mask = &uart0_dmamask,
956 .coherent_dma_mask = DMA_BIT_MASK(32),
957 .platform_data = &uart0_data,
958 },
959 .resource = uart0_resources,
960 .num_resources = ARRAY_SIZE(uart0_resources),
961 };
962
963 static inline void configure_usart0_pins(unsigned pins)
964 {
965 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
966 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
967
968 if (pins & ATMEL_UART_CTS)
969 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
970
971 if (pins & ATMEL_UART_RTS) {
972 /*
973 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
974 * We need to drive the pin manually. Default is off (RTS is active low).
975 */
976 at91_set_gpio_output(AT91_PIN_PA21, 1);
977 }
978 }
979
980 static struct resource uart1_resources[] = {
981 [0] = {
982 .start = AT91RM9200_BASE_US1,
983 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
984 .flags = IORESOURCE_MEM,
985 },
986 [1] = {
987 .start = AT91RM9200_ID_US1,
988 .end = AT91RM9200_ID_US1,
989 .flags = IORESOURCE_IRQ,
990 },
991 };
992
993 static struct atmel_uart_data uart1_data = {
994 .use_dma_tx = 1,
995 .use_dma_rx = 1,
996 };
997
998 static u64 uart1_dmamask = DMA_BIT_MASK(32);
999
1000 static struct platform_device at91rm9200_uart1_device = {
1001 .name = "atmel_usart",
1002 .id = 2,
1003 .dev = {
1004 .dma_mask = &uart1_dmamask,
1005 .coherent_dma_mask = DMA_BIT_MASK(32),
1006 .platform_data = &uart1_data,
1007 },
1008 .resource = uart1_resources,
1009 .num_resources = ARRAY_SIZE(uart1_resources),
1010 };
1011
1012 static inline void configure_usart1_pins(unsigned pins)
1013 {
1014 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1015 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1016
1017 if (pins & ATMEL_UART_RI)
1018 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1019 if (pins & ATMEL_UART_DTR)
1020 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1021 if (pins & ATMEL_UART_DCD)
1022 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1023 if (pins & ATMEL_UART_CTS)
1024 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1025 if (pins & ATMEL_UART_DSR)
1026 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1027 if (pins & ATMEL_UART_RTS)
1028 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1029 }
1030
1031 static struct resource uart2_resources[] = {
1032 [0] = {
1033 .start = AT91RM9200_BASE_US2,
1034 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
1035 .flags = IORESOURCE_MEM,
1036 },
1037 [1] = {
1038 .start = AT91RM9200_ID_US2,
1039 .end = AT91RM9200_ID_US2,
1040 .flags = IORESOURCE_IRQ,
1041 },
1042 };
1043
1044 static struct atmel_uart_data uart2_data = {
1045 .use_dma_tx = 1,
1046 .use_dma_rx = 1,
1047 };
1048
1049 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1050
1051 static struct platform_device at91rm9200_uart2_device = {
1052 .name = "atmel_usart",
1053 .id = 3,
1054 .dev = {
1055 .dma_mask = &uart2_dmamask,
1056 .coherent_dma_mask = DMA_BIT_MASK(32),
1057 .platform_data = &uart2_data,
1058 },
1059 .resource = uart2_resources,
1060 .num_resources = ARRAY_SIZE(uart2_resources),
1061 };
1062
1063 static inline void configure_usart2_pins(unsigned pins)
1064 {
1065 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1066 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
1067
1068 if (pins & ATMEL_UART_CTS)
1069 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
1070 if (pins & ATMEL_UART_RTS)
1071 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
1072 }
1073
1074 static struct resource uart3_resources[] = {
1075 [0] = {
1076 .start = AT91RM9200_BASE_US3,
1077 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
1078 .flags = IORESOURCE_MEM,
1079 },
1080 [1] = {
1081 .start = AT91RM9200_ID_US3,
1082 .end = AT91RM9200_ID_US3,
1083 .flags = IORESOURCE_IRQ,
1084 },
1085 };
1086
1087 static struct atmel_uart_data uart3_data = {
1088 .use_dma_tx = 1,
1089 .use_dma_rx = 1,
1090 };
1091
1092 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1093
1094 static struct platform_device at91rm9200_uart3_device = {
1095 .name = "atmel_usart",
1096 .id = 4,
1097 .dev = {
1098 .dma_mask = &uart3_dmamask,
1099 .coherent_dma_mask = DMA_BIT_MASK(32),
1100 .platform_data = &uart3_data,
1101 },
1102 .resource = uart3_resources,
1103 .num_resources = ARRAY_SIZE(uart3_resources),
1104 };
1105
1106 static inline void configure_usart3_pins(unsigned pins)
1107 {
1108 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1109 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1110
1111 if (pins & ATMEL_UART_CTS)
1112 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1113 if (pins & ATMEL_UART_RTS)
1114 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1115 }
1116
1117 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1118
1119 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1120 {
1121 struct platform_device *pdev;
1122 struct atmel_uart_data *pdata;
1123
1124 switch (id) {
1125 case 0: /* DBGU */
1126 pdev = &at91rm9200_dbgu_device;
1127 configure_dbgu_pins();
1128 break;
1129 case AT91RM9200_ID_US0:
1130 pdev = &at91rm9200_uart0_device;
1131 configure_usart0_pins(pins);
1132 break;
1133 case AT91RM9200_ID_US1:
1134 pdev = &at91rm9200_uart1_device;
1135 configure_usart1_pins(pins);
1136 break;
1137 case AT91RM9200_ID_US2:
1138 pdev = &at91rm9200_uart2_device;
1139 configure_usart2_pins(pins);
1140 break;
1141 case AT91RM9200_ID_US3:
1142 pdev = &at91rm9200_uart3_device;
1143 configure_usart3_pins(pins);
1144 break;
1145 default:
1146 return;
1147 }
1148 pdata = pdev->dev.platform_data;
1149 pdata->num = portnr; /* update to mapped ID */
1150
1151 if (portnr < ATMEL_MAX_UART)
1152 at91_uarts[portnr] = pdev;
1153 }
1154
1155 void __init at91_add_device_serial(void)
1156 {
1157 int i;
1158
1159 for (i = 0; i < ATMEL_MAX_UART; i++) {
1160 if (at91_uarts[i])
1161 platform_device_register(at91_uarts[i]);
1162 }
1163 }
1164 #else
1165 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1166 void __init at91_add_device_serial(void) {}
1167 #endif
1168
1169
1170 /* -------------------------------------------------------------------- */
1171
1172 /*
1173 * These devices are always present and don't need any board-specific
1174 * setup.
1175 */
1176 static int __init at91_add_standard_devices(void)
1177 {
1178 at91_add_device_rtc();
1179 at91_add_device_watchdog();
1180 at91_add_device_tc();
1181 return 0;
1182 }
1183
1184 arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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