2 * Copyright (C) 2007 Atmel Corporation
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c-gpio.h>
17 #include <video/atmel_lcdc.h>
19 #include <asm/arch/board.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/at91sam9rl.h>
22 #include <asm/arch/at91sam9rl_matrix.h>
23 #include <asm/arch/at91sam9_smc.h>
28 /* --------------------------------------------------------------------
30 * -------------------------------------------------------------------- */
32 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
33 static u64 mmc_dmamask
= DMA_BIT_MASK(32);
34 static struct at91_mmc_data mmc_data
;
36 static struct resource mmc_resources
[] = {
38 .start
= AT91SAM9RL_BASE_MCI
,
39 .end
= AT91SAM9RL_BASE_MCI
+ SZ_16K
- 1,
40 .flags
= IORESOURCE_MEM
,
43 .start
= AT91SAM9RL_ID_MCI
,
44 .end
= AT91SAM9RL_ID_MCI
,
45 .flags
= IORESOURCE_IRQ
,
49 static struct platform_device at91sam9rl_mmc_device
= {
53 .dma_mask
= &mmc_dmamask
,
54 .coherent_dma_mask
= DMA_BIT_MASK(32),
55 .platform_data
= &mmc_data
,
57 .resource
= mmc_resources
,
58 .num_resources
= ARRAY_SIZE(mmc_resources
),
61 void __init
at91_add_device_mmc(short mmc_id
, struct at91_mmc_data
*data
)
68 at91_set_gpio_input(data
->det_pin
, 1);
69 at91_set_deglitch(data
->det_pin
, 1);
72 at91_set_gpio_input(data
->wp_pin
, 1);
74 at91_set_gpio_output(data
->vcc_pin
, 0);
77 at91_set_A_periph(AT91_PIN_PA2
, 0);
80 at91_set_A_periph(AT91_PIN_PA1
, 1);
82 /* DAT0, maybe DAT1..DAT3 */
83 at91_set_A_periph(AT91_PIN_PA0
, 1);
85 at91_set_A_periph(AT91_PIN_PA3
, 1);
86 at91_set_A_periph(AT91_PIN_PA4
, 1);
87 at91_set_A_periph(AT91_PIN_PA5
, 1);
91 platform_device_register(&at91sam9rl_mmc_device
);
94 void __init
at91_add_device_mmc(short mmc_id
, struct at91_mmc_data
*data
) {}
98 /* --------------------------------------------------------------------
100 * -------------------------------------------------------------------- */
102 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
103 static struct at91_nand_data nand_data
;
105 #define NAND_BASE AT91_CHIPSELECT_3
107 static struct resource nand_resources
[] = {
110 .end
= NAND_BASE
+ SZ_256M
- 1,
111 .flags
= IORESOURCE_MEM
,
114 .start
= AT91_BASE_SYS
+ AT91_ECC
,
115 .end
= AT91_BASE_SYS
+ AT91_ECC
+ SZ_512
- 1,
116 .flags
= IORESOURCE_MEM
,
120 static struct platform_device at91_nand_device
= {
124 .platform_data
= &nand_data
,
126 .resource
= nand_resources
,
127 .num_resources
= ARRAY_SIZE(nand_resources
),
130 void __init
at91_add_device_nand(struct at91_nand_data
*data
)
137 csa
= at91_sys_read(AT91_MATRIX_EBICSA
);
138 at91_sys_write(AT91_MATRIX_EBICSA
, csa
| AT91_MATRIX_CS3A_SMC_SMARTMEDIA
);
140 /* set the bus interface characteristics */
141 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
142 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
144 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
145 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
147 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
149 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8
| AT91_SMC_READMODE
| AT91_SMC_WRITEMODE
| AT91_SMC_EXNWMODE_DISABLE
| AT91_SMC_TDF_(1));
152 if (data
->enable_pin
)
153 at91_set_gpio_output(data
->enable_pin
, 1);
157 at91_set_gpio_input(data
->rdy_pin
, 1);
159 /* card detect pin */
161 at91_set_gpio_input(data
->det_pin
, 1);
163 at91_set_A_periph(AT91_PIN_PB4
, 0); /* NANDOE */
164 at91_set_A_periph(AT91_PIN_PB5
, 0); /* NANDWE */
167 platform_device_register(&at91_nand_device
);
171 void __init
at91_add_device_nand(struct at91_nand_data
*data
) {}
175 /* --------------------------------------------------------------------
177 * -------------------------------------------------------------------- */
180 * Prefer the GPIO code since the TWI controller isn't robust
181 * (gets overruns and underruns under load) and can only issue
182 * repeated STARTs in one scenario (the driver doesn't yet handle them).
184 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
186 static struct i2c_gpio_platform_data pdata
= {
187 .sda_pin
= AT91_PIN_PA23
,
188 .sda_is_open_drain
= 1,
189 .scl_pin
= AT91_PIN_PA24
,
190 .scl_is_open_drain
= 1,
191 .udelay
= 2, /* ~100 kHz */
194 static struct platform_device at91sam9rl_twi_device
= {
197 .dev
.platform_data
= &pdata
,
200 void __init
at91_add_device_i2c(struct i2c_board_info
*devices
, int nr_devices
)
202 at91_set_GPIO_periph(AT91_PIN_PA23
, 1); /* TWD (SDA) */
203 at91_set_multi_drive(AT91_PIN_PA23
, 1);
205 at91_set_GPIO_periph(AT91_PIN_PA24
, 1); /* TWCK (SCL) */
206 at91_set_multi_drive(AT91_PIN_PA24
, 1);
208 i2c_register_board_info(0, devices
, nr_devices
);
209 platform_device_register(&at91sam9rl_twi_device
);
212 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
214 static struct resource twi_resources
[] = {
216 .start
= AT91SAM9RL_BASE_TWI0
,
217 .end
= AT91SAM9RL_BASE_TWI0
+ SZ_16K
- 1,
218 .flags
= IORESOURCE_MEM
,
221 .start
= AT91SAM9RL_ID_TWI0
,
222 .end
= AT91SAM9RL_ID_TWI0
,
223 .flags
= IORESOURCE_IRQ
,
227 static struct platform_device at91sam9rl_twi_device
= {
230 .resource
= twi_resources
,
231 .num_resources
= ARRAY_SIZE(twi_resources
),
234 void __init
at91_add_device_i2c(struct i2c_board_info
*devices
, int nr_devices
)
236 /* pins used for TWI interface */
237 at91_set_A_periph(AT91_PIN_PA23
, 0); /* TWD */
238 at91_set_multi_drive(AT91_PIN_PA23
, 1);
240 at91_set_A_periph(AT91_PIN_PA24
, 0); /* TWCK */
241 at91_set_multi_drive(AT91_PIN_PA24
, 1);
243 i2c_register_board_info(0, devices
, nr_devices
);
244 platform_device_register(&at91sam9rl_twi_device
);
247 void __init
at91_add_device_i2c(struct i2c_board_info
*devices
, int nr_devices
) {}
251 /* --------------------------------------------------------------------
253 * -------------------------------------------------------------------- */
255 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
256 static u64 spi_dmamask
= DMA_BIT_MASK(32);
258 static struct resource spi_resources
[] = {
260 .start
= AT91SAM9RL_BASE_SPI
,
261 .end
= AT91SAM9RL_BASE_SPI
+ SZ_16K
- 1,
262 .flags
= IORESOURCE_MEM
,
265 .start
= AT91SAM9RL_ID_SPI
,
266 .end
= AT91SAM9RL_ID_SPI
,
267 .flags
= IORESOURCE_IRQ
,
271 static struct platform_device at91sam9rl_spi_device
= {
275 .dma_mask
= &spi_dmamask
,
276 .coherent_dma_mask
= DMA_BIT_MASK(32),
278 .resource
= spi_resources
,
279 .num_resources
= ARRAY_SIZE(spi_resources
),
282 static const unsigned spi_standard_cs
[4] = { AT91_PIN_PA28
, AT91_PIN_PB7
, AT91_PIN_PD8
, AT91_PIN_PD9
};
285 void __init
at91_add_device_spi(struct spi_board_info
*devices
, int nr_devices
)
288 unsigned long cs_pin
;
290 at91_set_A_periph(AT91_PIN_PA25
, 0); /* MISO */
291 at91_set_A_periph(AT91_PIN_PA26
, 0); /* MOSI */
292 at91_set_A_periph(AT91_PIN_PA27
, 0); /* SPCK */
294 /* Enable SPI chip-selects */
295 for (i
= 0; i
< nr_devices
; i
++) {
296 if (devices
[i
].controller_data
)
297 cs_pin
= (unsigned long) devices
[i
].controller_data
;
299 cs_pin
= spi_standard_cs
[devices
[i
].chip_select
];
301 /* enable chip-select pin */
302 at91_set_gpio_output(cs_pin
, 1);
304 /* pass chip-select pin to driver */
305 devices
[i
].controller_data
= (void *) cs_pin
;
308 spi_register_board_info(devices
, nr_devices
);
309 platform_device_register(&at91sam9rl_spi_device
);
312 void __init
at91_add_device_spi(struct spi_board_info
*devices
, int nr_devices
) {}
316 /* --------------------------------------------------------------------
318 * -------------------------------------------------------------------- */
320 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
321 static u64 lcdc_dmamask
= DMA_BIT_MASK(32);
322 static struct atmel_lcdfb_info lcdc_data
;
324 static struct resource lcdc_resources
[] = {
326 .start
= AT91SAM9RL_LCDC_BASE
,
327 .end
= AT91SAM9RL_LCDC_BASE
+ SZ_4K
- 1,
328 .flags
= IORESOURCE_MEM
,
331 .start
= AT91SAM9RL_ID_LCDC
,
332 .end
= AT91SAM9RL_ID_LCDC
,
333 .flags
= IORESOURCE_IRQ
,
335 #if defined(CONFIG_FB_INTSRAM)
337 .start
= AT91SAM9RL_SRAM_BASE
,
338 .end
= AT91SAM9RL_SRAM_BASE
+ AT91SAM9RL_SRAM_SIZE
- 1,
339 .flags
= IORESOURCE_MEM
,
344 static struct platform_device at91_lcdc_device
= {
345 .name
= "atmel_lcdfb",
348 .dma_mask
= &lcdc_dmamask
,
349 .coherent_dma_mask
= DMA_BIT_MASK(32),
350 .platform_data
= &lcdc_data
,
352 .resource
= lcdc_resources
,
353 .num_resources
= ARRAY_SIZE(lcdc_resources
),
356 void __init
at91_add_device_lcdc(struct atmel_lcdfb_info
*data
)
362 at91_set_B_periph(AT91_PIN_PC1
, 0); /* LCDPWR */
363 at91_set_A_periph(AT91_PIN_PC5
, 0); /* LCDHSYNC */
364 at91_set_A_periph(AT91_PIN_PC6
, 0); /* LCDDOTCK */
365 at91_set_A_periph(AT91_PIN_PC7
, 0); /* LCDDEN */
366 at91_set_A_periph(AT91_PIN_PC3
, 0); /* LCDCC */
367 at91_set_B_periph(AT91_PIN_PC9
, 0); /* LCDD3 */
368 at91_set_B_periph(AT91_PIN_PC10
, 0); /* LCDD4 */
369 at91_set_B_periph(AT91_PIN_PC11
, 0); /* LCDD5 */
370 at91_set_B_periph(AT91_PIN_PC12
, 0); /* LCDD6 */
371 at91_set_B_periph(AT91_PIN_PC13
, 0); /* LCDD7 */
372 at91_set_B_periph(AT91_PIN_PC15
, 0); /* LCDD11 */
373 at91_set_B_periph(AT91_PIN_PC16
, 0); /* LCDD12 */
374 at91_set_B_periph(AT91_PIN_PC17
, 0); /* LCDD13 */
375 at91_set_B_periph(AT91_PIN_PC18
, 0); /* LCDD14 */
376 at91_set_B_periph(AT91_PIN_PC19
, 0); /* LCDD15 */
377 at91_set_B_periph(AT91_PIN_PC20
, 0); /* LCDD18 */
378 at91_set_B_periph(AT91_PIN_PC21
, 0); /* LCDD19 */
379 at91_set_B_periph(AT91_PIN_PC22
, 0); /* LCDD20 */
380 at91_set_B_periph(AT91_PIN_PC23
, 0); /* LCDD21 */
381 at91_set_B_periph(AT91_PIN_PC24
, 0); /* LCDD22 */
382 at91_set_B_periph(AT91_PIN_PC25
, 0); /* LCDD23 */
385 platform_device_register(&at91_lcdc_device
);
388 void __init
at91_add_device_lcdc(struct atmel_lcdfb_info
*data
) {}
392 /* --------------------------------------------------------------------
394 * -------------------------------------------------------------------- */
396 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
397 static struct platform_device at91sam9rl_rtc_device
= {
403 static void __init
at91_add_device_rtc(void)
405 platform_device_register(&at91sam9rl_rtc_device
);
408 static void __init
at91_add_device_rtc(void) {}
412 /* --------------------------------------------------------------------
414 * -------------------------------------------------------------------- */
416 static struct resource rtt_resources
[] = {
418 .start
= AT91_BASE_SYS
+ AT91_RTT
,
419 .end
= AT91_BASE_SYS
+ AT91_RTT
+ SZ_16
- 1,
420 .flags
= IORESOURCE_MEM
,
424 static struct platform_device at91sam9rl_rtt_device
= {
427 .resource
= rtt_resources
,
428 .num_resources
= ARRAY_SIZE(rtt_resources
),
431 static void __init
at91_add_device_rtt(void)
433 platform_device_register(&at91sam9rl_rtt_device
);
437 /* --------------------------------------------------------------------
439 * -------------------------------------------------------------------- */
441 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
442 static struct platform_device at91sam9rl_wdt_device
= {
448 static void __init
at91_add_device_watchdog(void)
450 platform_device_register(&at91sam9rl_wdt_device
);
453 static void __init
at91_add_device_watchdog(void) {}
457 /* --------------------------------------------------------------------
458 * SSC -- Synchronous Serial Controller
459 * -------------------------------------------------------------------- */
461 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
462 static u64 ssc0_dmamask
= DMA_BIT_MASK(32);
464 static struct resource ssc0_resources
[] = {
466 .start
= AT91SAM9RL_BASE_SSC0
,
467 .end
= AT91SAM9RL_BASE_SSC0
+ SZ_16K
- 1,
468 .flags
= IORESOURCE_MEM
,
471 .start
= AT91SAM9RL_ID_SSC0
,
472 .end
= AT91SAM9RL_ID_SSC0
,
473 .flags
= IORESOURCE_IRQ
,
477 static struct platform_device at91sam9rl_ssc0_device
= {
481 .dma_mask
= &ssc0_dmamask
,
482 .coherent_dma_mask
= DMA_BIT_MASK(32),
484 .resource
= ssc0_resources
,
485 .num_resources
= ARRAY_SIZE(ssc0_resources
),
488 static inline void configure_ssc0_pins(unsigned pins
)
490 if (pins
& ATMEL_SSC_TF
)
491 at91_set_A_periph(AT91_PIN_PC0
, 1);
492 if (pins
& ATMEL_SSC_TK
)
493 at91_set_A_periph(AT91_PIN_PC1
, 1);
494 if (pins
& ATMEL_SSC_TD
)
495 at91_set_A_periph(AT91_PIN_PA15
, 1);
496 if (pins
& ATMEL_SSC_RD
)
497 at91_set_A_periph(AT91_PIN_PA16
, 1);
498 if (pins
& ATMEL_SSC_RK
)
499 at91_set_B_periph(AT91_PIN_PA10
, 1);
500 if (pins
& ATMEL_SSC_RF
)
501 at91_set_B_periph(AT91_PIN_PA22
, 1);
504 static u64 ssc1_dmamask
= DMA_BIT_MASK(32);
506 static struct resource ssc1_resources
[] = {
508 .start
= AT91SAM9RL_BASE_SSC1
,
509 .end
= AT91SAM9RL_BASE_SSC1
+ SZ_16K
- 1,
510 .flags
= IORESOURCE_MEM
,
513 .start
= AT91SAM9RL_ID_SSC1
,
514 .end
= AT91SAM9RL_ID_SSC1
,
515 .flags
= IORESOURCE_IRQ
,
519 static struct platform_device at91sam9rl_ssc1_device
= {
523 .dma_mask
= &ssc1_dmamask
,
524 .coherent_dma_mask
= DMA_BIT_MASK(32),
526 .resource
= ssc1_resources
,
527 .num_resources
= ARRAY_SIZE(ssc1_resources
),
530 static inline void configure_ssc1_pins(unsigned pins
)
532 if (pins
& ATMEL_SSC_TF
)
533 at91_set_B_periph(AT91_PIN_PA29
, 1);
534 if (pins
& ATMEL_SSC_TK
)
535 at91_set_B_periph(AT91_PIN_PA30
, 1);
536 if (pins
& ATMEL_SSC_TD
)
537 at91_set_B_periph(AT91_PIN_PA13
, 1);
538 if (pins
& ATMEL_SSC_RD
)
539 at91_set_B_periph(AT91_PIN_PA14
, 1);
540 if (pins
& ATMEL_SSC_RK
)
541 at91_set_B_periph(AT91_PIN_PA9
, 1);
542 if (pins
& ATMEL_SSC_RF
)
543 at91_set_B_periph(AT91_PIN_PA8
, 1);
547 * Return the device node so that board init code can use it as the
548 * parent for the device node reflecting how it's used on this board.
550 * SSC controllers are accessed through library code, instead of any
551 * kind of all-singing/all-dancing driver. For example one could be
552 * used by a particular I2S audio codec's driver, while another one
553 * on the same system might be used by a custom data capture driver.
555 void __init
at91_add_device_ssc(unsigned id
, unsigned pins
)
557 struct platform_device
*pdev
;
560 * NOTE: caller is responsible for passing information matching
561 * "pins" to whatever will be using each particular controller.
564 case AT91SAM9RL_ID_SSC0
:
565 pdev
= &at91sam9rl_ssc0_device
;
566 configure_ssc0_pins(pins
);
567 at91_clock_associate("ssc0_clk", &pdev
->dev
, "pclk");
569 case AT91SAM9RL_ID_SSC1
:
570 pdev
= &at91sam9rl_ssc1_device
;
571 configure_ssc1_pins(pins
);
572 at91_clock_associate("ssc1_clk", &pdev
->dev
, "pclk");
578 platform_device_register(pdev
);
582 void __init
at91_add_device_ssc(unsigned id
, unsigned pins
) {}
586 /* --------------------------------------------------------------------
588 * -------------------------------------------------------------------- */
590 #if defined(CONFIG_SERIAL_ATMEL)
591 static struct resource dbgu_resources
[] = {
593 .start
= AT91_VA_BASE_SYS
+ AT91_DBGU
,
594 .end
= AT91_VA_BASE_SYS
+ AT91_DBGU
+ SZ_512
- 1,
595 .flags
= IORESOURCE_MEM
,
598 .start
= AT91_ID_SYS
,
600 .flags
= IORESOURCE_IRQ
,
604 static struct atmel_uart_data dbgu_data
= {
606 .use_dma_rx
= 0, /* DBGU not capable of receive DMA */
607 .regs
= (void __iomem
*)(AT91_VA_BASE_SYS
+ AT91_DBGU
),
610 static u64 dbgu_dmamask
= DMA_BIT_MASK(32);
612 static struct platform_device at91sam9rl_dbgu_device
= {
613 .name
= "atmel_usart",
616 .dma_mask
= &dbgu_dmamask
,
617 .coherent_dma_mask
= DMA_BIT_MASK(32),
618 .platform_data
= &dbgu_data
,
620 .resource
= dbgu_resources
,
621 .num_resources
= ARRAY_SIZE(dbgu_resources
),
624 static inline void configure_dbgu_pins(void)
626 at91_set_A_periph(AT91_PIN_PA21
, 0); /* DRXD */
627 at91_set_A_periph(AT91_PIN_PA22
, 1); /* DTXD */
630 static struct resource uart0_resources
[] = {
632 .start
= AT91SAM9RL_BASE_US0
,
633 .end
= AT91SAM9RL_BASE_US0
+ SZ_16K
- 1,
634 .flags
= IORESOURCE_MEM
,
637 .start
= AT91SAM9RL_ID_US0
,
638 .end
= AT91SAM9RL_ID_US0
,
639 .flags
= IORESOURCE_IRQ
,
643 static struct atmel_uart_data uart0_data
= {
648 static u64 uart0_dmamask
= DMA_BIT_MASK(32);
650 static struct platform_device at91sam9rl_uart0_device
= {
651 .name
= "atmel_usart",
654 .dma_mask
= &uart0_dmamask
,
655 .coherent_dma_mask
= DMA_BIT_MASK(32),
656 .platform_data
= &uart0_data
,
658 .resource
= uart0_resources
,
659 .num_resources
= ARRAY_SIZE(uart0_resources
),
662 static inline void configure_usart0_pins(unsigned pins
)
664 at91_set_A_periph(AT91_PIN_PA6
, 1); /* TXD0 */
665 at91_set_A_periph(AT91_PIN_PA7
, 0); /* RXD0 */
667 if (pins
& ATMEL_UART_RTS
)
668 at91_set_A_periph(AT91_PIN_PA9
, 0); /* RTS0 */
669 if (pins
& ATMEL_UART_CTS
)
670 at91_set_A_periph(AT91_PIN_PA10
, 0); /* CTS0 */
671 if (pins
& ATMEL_UART_DSR
)
672 at91_set_A_periph(AT91_PIN_PD14
, 0); /* DSR0 */
673 if (pins
& ATMEL_UART_DTR
)
674 at91_set_A_periph(AT91_PIN_PD15
, 0); /* DTR0 */
675 if (pins
& ATMEL_UART_DCD
)
676 at91_set_A_periph(AT91_PIN_PD16
, 0); /* DCD0 */
677 if (pins
& ATMEL_UART_RI
)
678 at91_set_A_periph(AT91_PIN_PD17
, 0); /* RI0 */
681 static struct resource uart1_resources
[] = {
683 .start
= AT91SAM9RL_BASE_US1
,
684 .end
= AT91SAM9RL_BASE_US1
+ SZ_16K
- 1,
685 .flags
= IORESOURCE_MEM
,
688 .start
= AT91SAM9RL_ID_US1
,
689 .end
= AT91SAM9RL_ID_US1
,
690 .flags
= IORESOURCE_IRQ
,
694 static struct atmel_uart_data uart1_data
= {
699 static u64 uart1_dmamask
= DMA_BIT_MASK(32);
701 static struct platform_device at91sam9rl_uart1_device
= {
702 .name
= "atmel_usart",
705 .dma_mask
= &uart1_dmamask
,
706 .coherent_dma_mask
= DMA_BIT_MASK(32),
707 .platform_data
= &uart1_data
,
709 .resource
= uart1_resources
,
710 .num_resources
= ARRAY_SIZE(uart1_resources
),
713 static inline void configure_usart1_pins(unsigned pins
)
715 at91_set_A_periph(AT91_PIN_PA11
, 1); /* TXD1 */
716 at91_set_A_periph(AT91_PIN_PA12
, 0); /* RXD1 */
718 if (pins
& ATMEL_UART_RTS
)
719 at91_set_B_periph(AT91_PIN_PA18
, 0); /* RTS1 */
720 if (pins
& ATMEL_UART_CTS
)
721 at91_set_B_periph(AT91_PIN_PA19
, 0); /* CTS1 */
724 static struct resource uart2_resources
[] = {
726 .start
= AT91SAM9RL_BASE_US2
,
727 .end
= AT91SAM9RL_BASE_US2
+ SZ_16K
- 1,
728 .flags
= IORESOURCE_MEM
,
731 .start
= AT91SAM9RL_ID_US2
,
732 .end
= AT91SAM9RL_ID_US2
,
733 .flags
= IORESOURCE_IRQ
,
737 static struct atmel_uart_data uart2_data
= {
742 static u64 uart2_dmamask
= DMA_BIT_MASK(32);
744 static struct platform_device at91sam9rl_uart2_device
= {
745 .name
= "atmel_usart",
748 .dma_mask
= &uart2_dmamask
,
749 .coherent_dma_mask
= DMA_BIT_MASK(32),
750 .platform_data
= &uart2_data
,
752 .resource
= uart2_resources
,
753 .num_resources
= ARRAY_SIZE(uart2_resources
),
756 static inline void configure_usart2_pins(unsigned pins
)
758 at91_set_A_periph(AT91_PIN_PA13
, 1); /* TXD2 */
759 at91_set_A_periph(AT91_PIN_PA14
, 0); /* RXD2 */
761 if (pins
& ATMEL_UART_RTS
)
762 at91_set_A_periph(AT91_PIN_PA29
, 0); /* RTS2 */
763 if (pins
& ATMEL_UART_CTS
)
764 at91_set_A_periph(AT91_PIN_PA30
, 0); /* CTS2 */
767 static struct resource uart3_resources
[] = {
769 .start
= AT91SAM9RL_BASE_US3
,
770 .end
= AT91SAM9RL_BASE_US3
+ SZ_16K
- 1,
771 .flags
= IORESOURCE_MEM
,
774 .start
= AT91SAM9RL_ID_US3
,
775 .end
= AT91SAM9RL_ID_US3
,
776 .flags
= IORESOURCE_IRQ
,
780 static struct atmel_uart_data uart3_data
= {
785 static u64 uart3_dmamask
= DMA_BIT_MASK(32);
787 static struct platform_device at91sam9rl_uart3_device
= {
788 .name
= "atmel_usart",
791 .dma_mask
= &uart3_dmamask
,
792 .coherent_dma_mask
= DMA_BIT_MASK(32),
793 .platform_data
= &uart3_data
,
795 .resource
= uart3_resources
,
796 .num_resources
= ARRAY_SIZE(uart3_resources
),
799 static inline void configure_usart3_pins(unsigned pins
)
801 at91_set_A_periph(AT91_PIN_PB0
, 1); /* TXD3 */
802 at91_set_A_periph(AT91_PIN_PB1
, 0); /* RXD3 */
804 if (pins
& ATMEL_UART_RTS
)
805 at91_set_B_periph(AT91_PIN_PD4
, 0); /* RTS3 */
806 if (pins
& ATMEL_UART_CTS
)
807 at91_set_B_periph(AT91_PIN_PD3
, 0); /* CTS3 */
810 static struct platform_device
*at91_uarts
[ATMEL_MAX_UART
]; /* the UARTs to use */
811 struct platform_device
*atmel_default_console_device
; /* the serial console device */
813 void __init __deprecated
at91_init_serial(struct at91_uart_config
*config
)
817 /* Fill in list of supported UARTs */
818 for (i
= 0; i
< config
->nr_tty
; i
++) {
819 switch (config
->tty_map
[i
]) {
821 configure_usart0_pins(ATMEL_UART_CTS
| ATMEL_UART_RTS
);
822 at91_uarts
[i
] = &at91sam9rl_uart0_device
;
823 at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device
.dev
, "usart");
826 configure_usart1_pins(0);
827 at91_uarts
[i
] = &at91sam9rl_uart1_device
;
828 at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device
.dev
, "usart");
831 configure_usart2_pins(0);
832 at91_uarts
[i
] = &at91sam9rl_uart2_device
;
833 at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device
.dev
, "usart");
836 configure_usart3_pins(0);
837 at91_uarts
[i
] = &at91sam9rl_uart3_device
;
838 at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device
.dev
, "usart");
841 configure_dbgu_pins();
842 at91_uarts
[i
] = &at91sam9rl_dbgu_device
;
843 at91_clock_associate("mck", &at91sam9rl_dbgu_device
.dev
, "usart");
848 at91_uarts
[i
]->id
= i
; /* update ID number to mapped ID */
851 /* Set serial console device */
852 if (config
->console_tty
< ATMEL_MAX_UART
)
853 atmel_default_console_device
= at91_uarts
[config
->console_tty
];
854 if (!atmel_default_console_device
)
855 printk(KERN_INFO
"AT91: No default serial console defined.\n");
858 void __init
at91_register_uart(unsigned id
, unsigned portnr
, unsigned pins
)
860 struct platform_device
*pdev
;
864 pdev
= &at91sam9rl_dbgu_device
;
865 configure_dbgu_pins();
866 at91_clock_associate("mck", &pdev
->dev
, "usart");
868 case AT91SAM9RL_ID_US0
:
869 pdev
= &at91sam9rl_uart0_device
;
870 configure_usart0_pins(pins
);
871 at91_clock_associate("usart0_clk", &pdev
->dev
, "usart");
873 case AT91SAM9RL_ID_US1
:
874 pdev
= &at91sam9rl_uart1_device
;
875 configure_usart1_pins(pins
);
876 at91_clock_associate("usart1_clk", &pdev
->dev
, "usart");
878 case AT91SAM9RL_ID_US2
:
879 pdev
= &at91sam9rl_uart2_device
;
880 configure_usart2_pins(pins
);
881 at91_clock_associate("usart2_clk", &pdev
->dev
, "usart");
883 case AT91SAM9RL_ID_US3
:
884 pdev
= &at91sam9rl_uart3_device
;
885 configure_usart3_pins(pins
);
886 at91_clock_associate("usart3_clk", &pdev
->dev
, "usart");
891 pdev
->id
= portnr
; /* update to mapped ID */
893 if (portnr
< ATMEL_MAX_UART
)
894 at91_uarts
[portnr
] = pdev
;
897 void __init
at91_set_serial_console(unsigned portnr
)
899 if (portnr
< ATMEL_MAX_UART
)
900 atmel_default_console_device
= at91_uarts
[portnr
];
901 if (!atmel_default_console_device
)
902 printk(KERN_INFO
"AT91: No default serial console defined.\n");
905 void __init
at91_add_device_serial(void)
909 for (i
= 0; i
< ATMEL_MAX_UART
; i
++) {
911 platform_device_register(at91_uarts
[i
]);
915 void __init __deprecated
at91_init_serial(struct at91_uart_config
*config
) {}
916 void __init
at91_register_uart(unsigned id
, unsigned portnr
, unsigned pins
) {}
917 void __init
at91_set_serial_console(unsigned portnr
) {}
918 void __init
at91_add_device_serial(void) {}
922 /* -------------------------------------------------------------------- */
925 * These devices are always present and don't need any board-specific
928 static int __init
at91_add_standard_devices(void)
930 at91_add_device_rtc();
931 at91_add_device_rtt();
932 at91_add_device_watchdog();
936 arch_initcall(at91_add_standard_devices
);