arch/arm/mach-at91/board-yl-9200.c

   1 /*
   2  * linux/arch/arm/mach-at91/board-yl-9200.c
   3  *
   4  * Adapted from various board files in arch/arm/mach-at91
   5  *
   6  * Modifications for YL-9200 platform:
   7  *  Copyright (C) 2007 S. Birtles
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #include <linux/types.h>
  25 #include <linux/gpio.h>
  26 #include <linux/init.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spi/spi.h>
  32 #include <linux/spi/ads7846.h>
  33 #include <linux/mtd/physmap.h>
  34 #include <linux/gpio_keys.h>
  35 #include <linux/input.h>
  36
  37 #include <asm/setup.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/irq.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/irq.h>
  44
  45 #include <mach/hardware.h>
  46 #include <mach/at91rm9200_mc.h>
  47 #include <mach/at91_ramc.h>
  48 #include <mach/cpu.h>
  49
  50 #include "at91_aic.h"
  51 #include "board.h"
  52 #include "generic.h"
  53 #include "gpio.h"
  54
  55
  56 static void __init yl9200_init_early(void)
  57 {
  58         /* Set cpu type: PQFP */
  59         at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
  60
  61         /* Initialize processor: 18.432 MHz crystal */
  62         at91_initialize(18432000);
  63 }
  64
  65 /*
  66  * LEDs
  67  */
  68 static struct gpio_led yl9200_leds[] = {
  69         {       /* D2 */
  70                 .name                   = "led2",
  71                 .gpio                   = AT91_PIN_PB17,
  72                 .active_low             = 1,
  73                 .default_trigger        = "timer",
  74         },
  75         {       /* D3 */
  76                 .name                   = "led3",
  77                 .gpio                   = AT91_PIN_PB16,
  78                 .active_low             = 1,
  79                 .default_trigger        = "heartbeat",
  80         },
  81         {       /* D4 */
  82                 .name                   = "led4",
  83                 .gpio                   = AT91_PIN_PB15,
  84                 .active_low             = 1,
  85         },
  86         {       /* D5 */
  87                 .name                   = "led5",
  88                 .gpio                   = AT91_PIN_PB8,
  89                 .active_low             = 1,
  90         }
  91 };
  92
  93 /*
  94  * Ethernet
  95  */
  96 static struct macb_platform_data __initdata yl9200_eth_data = {
  97         .phy_irq_pin            = AT91_PIN_PB28,
  98         .is_rmii                = 1,
  99 };
 100
 101 /*
 102  * USB Host
 103  */
 104 static struct at91_usbh_data __initdata yl9200_usbh_data = {
 105         .ports                  = 1,    /* PQFP version of AT91RM9200 */
 106         .vbus_pin               = {-EINVAL, -EINVAL},
 107         .overcurrent_pin= {-EINVAL, -EINVAL},
 108 };
 109
 110 /*
 111  * USB Device
 112  */
 113 static struct at91_udc_data __initdata yl9200_udc_data = {
 114         .pullup_pin             = AT91_PIN_PC4,
 115         .vbus_pin               = AT91_PIN_PC5,
 116         .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
 117
 118 };
 119
 120 /*
 121  * MMC
 122  */
 123 static struct mci_platform_data __initdata yl9200_mci0_data = {
 124         .slot[0] = {
 125                 .bus_width      = 4,
 126                 .detect_pin     = AT91_PIN_PB9,
 127                 .wp_pin         = -EINVAL,
 128         },
 129 };
 130
 131 /*
 132  * NAND Flash
 133  */
 134 static struct mtd_partition __initdata yl9200_nand_partition[] = {
 135         {
 136                 .name   = "AT91 NAND partition 1, boot",
 137                 .offset = 0,
 138                 .size   = SZ_256K
 139         },
 140         {
 141                 .name   = "AT91 NAND partition 2, kernel",
 142                 .offset = MTDPART_OFS_NXTBLK,
 143                 .size   = (2 * SZ_1M) - SZ_256K
 144         },
 145         {
 146                 .name   = "AT91 NAND partition 3, filesystem",
 147                 .offset = MTDPART_OFS_NXTBLK,
 148                 .size   = 14 * SZ_1M
 149         },
 150         {
 151                 .name   = "AT91 NAND partition 4, storage",
 152                 .offset = MTDPART_OFS_NXTBLK,
 153                 .size   = SZ_16M
 154         },
 155         {
 156                 .name   = "AT91 NAND partition 5, ext-fs",
 157                 .offset = MTDPART_OFS_NXTBLK,
 158                 .size   = SZ_32M
 159         }
 160 };
 161
 162 static struct atmel_nand_data __initdata yl9200_nand_data = {
 163         .ale            = 6,
 164         .cle            = 7,
 165         .det_pin        = -EINVAL,
 166         .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
 167         .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
 168         .ecc_mode       = NAND_ECC_SOFT,
 169         .parts          = yl9200_nand_partition,
 170         .num_parts      = ARRAY_SIZE(yl9200_nand_partition),
 171 };
 172
 173 /*
 174  * NOR Flash
 175  */
 176 #define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
 177 #define YL9200_FLASH_SIZE       SZ_16M
 178
 179 static struct mtd_partition yl9200_flash_partitions[] = {
 180         {
 181                 .name           = "Bootloader",
 182                 .offset         = 0,
 183                 .size           = SZ_256K,
 184                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 185         },
 186         {
 187                 .name           = "Kernel",
 188                 .offset         = MTDPART_OFS_NXTBLK,
 189                 .size           = (2 * SZ_1M) - SZ_256K
 190         },
 191         {
 192                 .name           = "Filesystem",
 193                 .offset         = MTDPART_OFS_NXTBLK,
 194                 .size           = MTDPART_SIZ_FULL
 195         }
 196 };
 197
 198 static struct physmap_flash_data yl9200_flash_data = {
 199         .width          = 2,
 200         .parts          = yl9200_flash_partitions,
 201         .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
 202 };
 203
 204 static struct resource yl9200_flash_resources[] = {
 205         {
 206                 .start  = YL9200_FLASH_BASE,
 207                 .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
 208                 .flags  = IORESOURCE_MEM,
 209         }
 210 };
 211
 212 static struct platform_device yl9200_flash = {
 213         .name           = "physmap-flash",
 214         .id             = 0,
 215         .dev            = {
 216                                 .platform_data  = &yl9200_flash_data,
 217                         },
 218         .resource       = yl9200_flash_resources,
 219         .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
 220 };
 221
 222 /*
 223  * I2C (TWI)
 224  */
 225 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
 226         {       /* EEPROM */
 227                 I2C_BOARD_INFO("24c128", 0x50),
 228         }
 229 };
 230
 231 /*
 232  * GPIO Buttons
 233 */
 234 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 235 static struct gpio_keys_button yl9200_buttons[] = {
 236         {
 237                 .gpio           = AT91_PIN_PA24,
 238                 .code           = BTN_2,
 239                 .desc           = "SW2",
 240                 .active_low     = 1,
 241                 .wakeup         = 1,
 242         },
 243         {
 244                 .gpio           = AT91_PIN_PB1,
 245                 .code           = BTN_3,
 246                 .desc           = "SW3",
 247                 .active_low     = 1,
 248                 .wakeup         = 1,
 249         },
 250         {
 251                 .gpio           = AT91_PIN_PB2,
 252                 .code           = BTN_4,
 253                 .desc           = "SW4",
 254                 .active_low     = 1,
 255                 .wakeup         = 1,
 256         },
 257         {
 258                 .gpio           = AT91_PIN_PB6,
 259                 .code           = BTN_5,
 260                 .desc           = "SW5",
 261                 .active_low     = 1,
 262                 .wakeup         = 1,
 263         }
 264 };
 265
 266 static struct gpio_keys_platform_data yl9200_button_data = {
 267         .buttons        = yl9200_buttons,
 268         .nbuttons       = ARRAY_SIZE(yl9200_buttons),
 269 };
 270
 271 static struct platform_device yl9200_button_device = {
 272         .name           = "gpio-keys",
 273         .id             = -1,
 274         .num_resources  = 0,
 275         .dev            = {
 276                 .platform_data  = &yl9200_button_data,
 277         }
 278 };
 279
 280 static void __init yl9200_add_device_buttons(void)
 281 {
 282         at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
 283         at91_set_deglitch(AT91_PIN_PA24, 1);
 284         at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
 285         at91_set_deglitch(AT91_PIN_PB1, 1);
 286         at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
 287         at91_set_deglitch(AT91_PIN_PB2, 1);
 288         at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
 289         at91_set_deglitch(AT91_PIN_PB6, 1);
 290
 291         /* Enable buttons (Sheet 5) */
 292         at91_set_gpio_output(AT91_PIN_PB7, 1);
 293
 294         platform_device_register(&yl9200_button_device);
 295 }
 296 #else
 297 static void __init yl9200_add_device_buttons(void) {}
 298 #endif
 299
 300 /*
 301  * Touchscreen
 302  */
 303 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 304 static int ads7843_pendown_state(void)
 305 {
 306         return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
 307 }
 308
 309 static struct ads7846_platform_data ads_info = {
 310         .model                  = 7843,
 311         .x_min                  = 150,
 312         .x_max                  = 3830,
 313         .y_min                  = 190,
 314         .y_max                  = 3830,
 315         .vref_delay_usecs       = 100,
 316
 317         /* For a 8" touch-screen */
 318         // .x_plate_ohms                = 603,
 319         // .y_plate_ohms                = 332,
 320
 321         /* For a 10.4" touch-screen */
 322         // .x_plate_ohms                = 611,
 323         // .y_plate_ohms                = 325,
 324
 325         .x_plate_ohms           = 576,
 326         .y_plate_ohms           = 366,
 327
 328         .pressure_max           = 15000, /* generally nonsense on the 7843 */
 329         .debounce_max           = 1,
 330         .debounce_rep           = 0,
 331         .debounce_tol           = (~0),
 332         .get_pendown_state      = ads7843_pendown_state,
 333 };
 334
 335 static void __init yl9200_add_device_ts(void)
 336 {
 337         at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
 338         at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
 339 }
 340 #else
 341 static void __init yl9200_add_device_ts(void) {}
 342 #endif
 343
 344 /*
 345  * SPI devices
 346  */
 347 static struct spi_board_info yl9200_spi_devices[] = {
 348 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 349         {       /* Touchscreen */
 350                 .modalias       = "ads7846",
 351                 .chip_select    = 0,
 352                 .max_speed_hz   = 5000 * 26,
 353                 .platform_data  = &ads_info,
 354                 .irq            = AT91_PIN_PB11,
 355         },
 356 #endif
 357         {       /* CAN */
 358                 .modalias       = "mcp2510",
 359                 .chip_select    = 1,
 360                 .max_speed_hz   = 25000 * 26,
 361                 .irq            = AT91_PIN_PC0,
 362         }
 363 };
 364
 365 /*
 366  * LCD / VGA
 367  *
 368  * EPSON S1D13806 FB (discontinued chip)
 369  * EPSON S1D13506 FB
 370  */
 371 #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 372 #include <video/s1d13xxxfb.h>
 373
 374
 375 static void yl9200_init_video(void)
 376 {
 377         /* NWAIT Signal */
 378         at91_set_A_periph(AT91_PIN_PC6, 0);
 379
 380         /* Initialization of the Static Memory Controller for Chip Select 2 */
 381         at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
 382                         | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
 383                         | AT91_SMC_TDF_(0x100)                  /* float time */
 384         );
 385 }
 386
 387 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
 388 {
 389         {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
 390         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 391         {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
 392         {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
 393         {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
 394         {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
 395         {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
 396         {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
 397         {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
 398         {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
 399         {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
 400         {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
 401         {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
 402         {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
 403         {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
 404         {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
 405         {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
 406         {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
 407         {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
 408         {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
 409         {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
 410         {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
 411         {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
 412         {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
 413         {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
 414         {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
 415         {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
 416         {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
 417         {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
 418         {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
 419         {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
 420         {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
 421         {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
 422         {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
 423         {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
 424         {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
 425         {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
 426         {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
 427         {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
 428         {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
 429         {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
 430         {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
 431         {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
 432         {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
 433         {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
 434         {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
 435         {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
 436         {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
 437         {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
 438         {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
 439         {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
 440         {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
 441         {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
 442         {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
 443         {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
 444         {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
 445         {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
 446         {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
 447         {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
 448         {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
 449         {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
 450         {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
 451         {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
 452         {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
 453         {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
 454         {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
 455         {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
 456         {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
 457         {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
 458         {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
 459         {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
 460         {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
 461         {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
 462         {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
 463         {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
 464         {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
 465         {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
 466         {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
 467         {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
 468         {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
 469         {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
 470         {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
 471         {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
 472         {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
 473         {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
 474         {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
 475         {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
 476         {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
 477         {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
 478         {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
 479         {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
 480         {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
 481         {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
 482         {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
 483         {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
 484         {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
 485         {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
 486         {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
 487         {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
 488         {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
 489         {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
 490         {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
 491         {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
 492         {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
 493         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 494 };
 495
 496 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
 497         .initregs               = yl9200_s1dfb_initregs,
 498         .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
 499         .platform_init_video    = yl9200_init_video,
 500 };
 501
 502 #define YL9200_FB_REG_BASE      AT91_CHIPSELECT_7
 503 #define YL9200_FB_VMEM_BASE     YL9200_FB_REG_BASE + SZ_2M
 504 #define YL9200_FB_VMEM_SIZE     SZ_2M
 505
 506 static struct resource yl9200_s1dfb_resource[] = {
 507         [0] = { /* video mem */
 508                 .name   = "s1d13xxxfb memory",
 509                 .start  = YL9200_FB_VMEM_BASE,
 510                 .end    = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
 511                 .flags  = IORESOURCE_MEM,
 512         },
 513         [1] = { /* video registers */
 514                 .name   = "s1d13xxxfb registers",
 515                 .start  = YL9200_FB_REG_BASE,
 516                 .end    = YL9200_FB_REG_BASE + SZ_512 -1,
 517                 .flags  = IORESOURCE_MEM,
 518         },
 519 };
 520
 521 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
 522
 523 static struct platform_device yl9200_s1dfb_device = {
 524         .name           = "s1d13806fb",
 525         .id             = -1,
 526         .dev    = {
 527                 .dma_mask               = &s1dfb_dmamask,
 528                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 529                 .platform_data          = &yl9200_s1dfb_pdata,
 530         },
 531         .resource       = yl9200_s1dfb_resource,
 532         .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
 533 };
 534
 535 void __init yl9200_add_device_video(void)
 536 {
 537         platform_device_register(&yl9200_s1dfb_device);
 538 }
 539 #else
 540 void __init yl9200_add_device_video(void) {}
 541 #endif
 542
 543
 544 static void __init yl9200_board_init(void)
 545 {
 546         /* Serial */
 547         /* DBGU on ttyS0. (Rx & Tx only) */
 548         at91_register_uart(0, 0, 0);
 549
 550         /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
 551         at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
 552                         | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
 553                         | ATMEL_UART_RI);
 554
 555         /* USART0 on ttyS2. (Rx & Tx only to JP3) */
 556         at91_register_uart(AT91RM9200_ID_US0, 2, 0);
 557
 558         /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
 559         at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
 560         at91_add_device_serial();
 561         /* Ethernet */
 562         at91_add_device_eth(&yl9200_eth_data);
 563         /* USB Host */
 564         at91_add_device_usbh(&yl9200_usbh_data);
 565         /* USB Device */
 566         at91_add_device_udc(&yl9200_udc_data);
 567         /* I2C */
 568         at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
 569         /* MMC */
 570         at91_add_device_mci(0, &yl9200_mci0_data);
 571         /* NAND */
 572         at91_add_device_nand(&yl9200_nand_data);
 573         /* NOR Flash */
 574         platform_device_register(&yl9200_flash);
 575 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 576         /* SPI */
 577         at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
 578         /* Touchscreen */
 579         yl9200_add_device_ts();
 580 #endif
 581         /* LEDs. */
 582         at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
 583         /* Push Buttons */
 584         yl9200_add_device_buttons();
 585         /* VGA */
 586         yl9200_add_device_video();
 587 }
 588
 589 MACHINE_START(YL9200, "uCdragon YL-9200")
 590         /* Maintainer: S.Birtles */
 591         .init_time      = at91rm9200_timer_init,
 592         .map_io         = at91_map_io,
 593         .handle_irq     = at91_aic_handle_irq,
 594         .init_early     = yl9200_init_early,
 595         .init_irq       = at91_init_irq_default,
 596         .init_machine   = yl9200_board_init,
 597 MACHINE_END