arch/arm/mach-at91/include/mach/at91_adc.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91_adc.h
   3  *
   4  * Copyright (C) SAN People
   5  *
   6  * Analog-to-Digital Converter (ADC) registers.
   7  * Based on AT91SAM9260 datasheet revision D.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #ifndef AT91_ADC_H
  16 #define AT91_ADC_H
  17
  18 #define AT91_ADC_CR             0x00            /* Control Register */
  19 #define         AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
  20 #define         AT91_ADC_START          (1 << 1)        /* Start Conversion */
  21
  22 #define AT91_ADC_MR             0x04            /* Mode Register */
  23 #define         AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
  24 #define         AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
  25 #define                 AT91_ADC_TRGSEL_TC0             (0 << 1)
  26 #define                 AT91_ADC_TRGSEL_TC1             (1 << 1)
  27 #define                 AT91_ADC_TRGSEL_TC2             (2 << 1)
  28 #define                 AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
  29 #define         AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
  30 #define         AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
  31 #define         AT91_ADC_PRESCAL_9260   (0x3f << 8)     /* Prescalar Rate Selection */
  32 #define         AT91_ADC_PRESCAL_9G45   (0xff << 8)
  33 #define                 AT91_ADC_PRESCAL_(x)    ((x) << 8)
  34 #define         AT91_ADC_STARTUP_9260   (0x1f << 16)    /* Startup Up Time */
  35 #define         AT91_ADC_STARTUP_9G45   (0x7f << 16)
  36 #define         AT91_ADC_STARTUP_9X5    (0xf << 16)
  37 #define                 AT91_ADC_STARTUP_(x)    ((x) << 16)
  38 #define         AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
  39 #define                 AT91_ADC_SHTIM_(x)      ((x) << 24)
  40
  41 #define AT91_ADC_CHER           0x10            /* Channel Enable Register */
  42 #define AT91_ADC_CHDR           0x14            /* Channel Disable Register */
  43 #define AT91_ADC_CHSR           0x18            /* Channel Status Register */
  44 #define         AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
  45
  46 #define AT91_ADC_SR             0x1C            /* Status Register */
  47 #define         AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
  48 #define         AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
  49 #define         AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
  50 #define         AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
  51 #define         AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
  52 #define         AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
  53
  54 #define AT91_ADC_SR_9X5         0x30            /* Status Register for 9x5 */
  55 #define         AT91_ADC_SR_DRDY_9X5    (1 << 24)       /* Data Ready */
  56
  57 #define AT91_ADC_LCDR           0x20            /* Last Converted Data Register */
  58 #define         AT91_ADC_LDATA          (0x3ff)
  59
  60 #define AT91_ADC_IER            0x24            /* Interrupt Enable Register */
  61 #define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
  62 #define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
  63
  64 #define AT91_ADC_CHR(n)         (0x30 + ((n) * 4))      /* Channel Data Register N */
  65 #define         AT91_ADC_DATA           (0x3ff)
  66
  67 #define AT91_ADC_CDR0_9X5       (0x50)                  /* Channel Data Register 0 for 9X5 */
  68
  69 #define AT91_ADC_TRGR_9260      AT91_ADC_MR
  70 #define AT91_ADC_TRGR_9G45      0x08
  71 #define AT91_ADC_TRGR_9X5       0xC0
  72
  73 #endif