arch/arm/mach-clps711x/include/mach/hardware.h

   1 /*
   2  *  arch/arm/mach-clps711x/include/mach/hardware.h
   3  *
   4  *  This file contains the hardware definitions of the Prospector P720T.
   5  *
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 #ifndef __MACH_HARDWARE_H
  23 #define __MACH_HARDWARE_H
  24
  25 #include <mach/clps711x.h>
  26
  27 #define CLPS711X_VIRT_BASE      IOMEM(0xff000000)
  28
  29 #ifndef __ASSEMBLY__
  30 #define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
  31 #define clps_readw(off)         readw(CLPS711X_VIRT_BASE + (off))
  32 #define clps_readl(off)         readl(CLPS711X_VIRT_BASE + (off))
  33 #define clps_writeb(val,off)    writeb(val, CLPS711X_VIRT_BASE + (off))
  34 #define clps_writew(val,off)    writew(val, CLPS711X_VIRT_BASE + (off))
  35 #define clps_writel(val,off)    writel(val, CLPS711X_VIRT_BASE + (off))
  36 #endif
  37
  38 /*
  39  * The physical addresses that the external chip select signals map to is
  40  * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
  41  * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
  42  * processors are in use.
  43  */
  44 #ifndef CONFIG_EP72XX_ROM_BOOT
  45 #define CS0_PHYS_BASE           (0x00000000)
  46 #define CS1_PHYS_BASE           (0x10000000)
  47 #define CS2_PHYS_BASE           (0x20000000)
  48 #define CS3_PHYS_BASE           (0x30000000)
  49 #define CS4_PHYS_BASE           (0x40000000)
  50 #define CS5_PHYS_BASE           (0x50000000)
  51 #define CS6_PHYS_BASE           (0x60000000)
  52 #define CS7_PHYS_BASE           (0x70000000)
  53 #else
  54 #define CS0_PHYS_BASE           (0x70000000)
  55 #define CS1_PHYS_BASE           (0x60000000)
  56 #define CS2_PHYS_BASE           (0x50000000)
  57 #define CS3_PHYS_BASE           (0x40000000)
  58 #define CS4_PHYS_BASE           (0x30000000)
  59 #define CS5_PHYS_BASE           (0x20000000)
  60 #define CS6_PHYS_BASE           (0x10000000)
  61 #define CS7_PHYS_BASE           (0x00000000)
  62 #endif
  63
  64 #define SYSPLD_VIRT_BASE        0xfe000000
  65 #define SYSPLD_BASE             SYSPLD_VIRT_BASE
  66
  67 #if defined (CONFIG_ARCH_CDB89712)
  68
  69 #define ETHER_START      0x20000000
  70 #define ETHER_SIZE       0x1000
  71 #define ETHER_BASE       0xfe000000
  72
  73 #endif
  74
  75
  76 #if defined (CONFIG_ARCH_EDB7211)
  77
  78 /*
  79  * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
  80  * and repeat across it. This is the mapping for it.
  81  *
  82  * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
  83  * was cause for much consternation and headscratching. This should probably
  84  * be made a compile/run time kernel option.
  85  */
  86 #define EP7211_PHYS_EXTKBD              CS3_PHYS_BASE   /* physical */
  87
  88 #define EP7211_VIRT_EXTKBD              (0xfd000000)    /* virtual */
  89
  90
  91 /*
  92  * The CS8900A ethernet chip has its I/O registers wired to chip select 2
  93  * (nCS2). This is the mapping for it.
  94  *
  95  * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
  96  * was cause for much consternation and headscratching. This should probably
  97  * be made a compile/run time kernel option.
  98  */
  99 #define EP7211_PHYS_CS8900A             CS2_PHYS_BASE   /* physical */
 100
 101 #define EP7211_VIRT_CS8900A             (0xfc000000)    /* virtual */
 102
 103
 104 /*
 105  * The two flash banks are wired to chip selects 0 and 1. This is the mapping
 106  * for them.
 107  *
 108  * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
 109  * in jumpered boot mode.
 110  */
 111 #define EP7211_PHYS_FLASH1              CS0_PHYS_BASE   /* physical */
 112 #define EP7211_PHYS_FLASH2              CS1_PHYS_BASE   /* physical */
 113
 114 #define EP7211_VIRT_FLASH1              (0xfa000000)    /* virtual */
 115 #define EP7211_VIRT_FLASH2              (0xfb000000)    /* virtual */
 116
 117 #endif /* CONFIG_ARCH_EDB7211 */
 118
 119
 120 /*
 121  * Relevant bits in port D, which controls power to the various parts of
 122  * the LCD on the EDB7211.
 123  */
 124 #define EDB_PD1_LCD_DC_DC_EN    (1<<1)
 125 #define EDB_PD2_LCDEN           (1<<2)
 126 #define EDB_PD3_LCDBL           (1<<3)
 127
 128
 129 #if defined (CONFIG_ARCH_CEIVA)
 130
 131 /*
 132  * The two flash banks are wired to chip selects 0 and 1. This is the mapping
 133  * for them.
 134  *
 135  * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
 136  * in jumpered boot mode.
 137  */
 138 #define CEIVA_PHYS_FLASH1       CS0_PHYS_BASE   /* physical */
 139 #define CEIVA_PHYS_FLASH2       CS1_PHYS_BASE   /* physical */
 140
 141 #define CEIVA_VIRT_FLASH1       (0xfa000000)    /* virtual */
 142 #define CEIVA_VIRT_FLASH2       (0xfb000000)    /* virtual */
 143
 144 #define CEIVA_FLASH_SIZE        0x100000
 145 #define CEIVA_FLASH_WIDTH       2
 146
 147 /*
 148  * SED1355 LCD controller
 149  */
 150 #define CEIVA_PHYS_SED1355      CS2_PHYS_BASE
 151 #define CEIVA_VIRT_SED1355      (0xfc000000)
 152
 153 /*
 154  * Relevant bits in port D, which controls power to the various parts of
 155  * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
 156  */
 157
 158 // Reset line to SED1355 (must be high to operate)
 159 #define CEIVA_PD1_LCDRST        (1<<1)
 160 // LCD panel enable (set to one, to enable LCD)
 161 #define CEIVA_PD4_LCDEN         (1<<4)
 162 // Backlight (set to one, to turn on backlight
 163 #define CEIVA_PD5_LCDBL         (1<<5)
 164
 165 /*
 166  * Relevant bits in port B, which report the status of the buttons.
 167  */
 168
 169 // White button
 170 #define CEIVA_PB4_WHT_BTN       (1<<4)
 171 // Black button
 172 #define CEIVA_PB0_BLK_BTN       (1<<0)
 173 #endif // #if defined (CONFIG_ARCH_CEIVA)
 174
 175 #endif