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[deliverable/linux.git] / arch / arm / mach-davinci / board-dm365-evm.c
1 /*
2 * TI DaVinci DM365 EVM board support
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
19 #include <linux/io.h>
20 #include <linux/clk.h>
21 #include <linux/i2c/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/input.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/eeprom.h>
30 #include <linux/v4l2-dv-timings.h>
31
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
34
35 #include <mach/mux.h>
36 #include <mach/common.h>
37 #include <linux/platform_data/i2c-davinci.h>
38 #include <mach/serial.h>
39 #include <linux/platform_data/mmc-davinci.h>
40 #include <linux/platform_data/mtd-davinci.h>
41 #include <linux/platform_data/keyscan-davinci.h>
42
43 #include <media/ths7303.h>
44 #include <media/tvp514x.h>
45
46 #include "davinci.h"
47
48 static inline int have_imager(void)
49 {
50 /* REVISIT when it's supported, trigger via Kconfig */
51 return 0;
52 }
53
54 static inline int have_tvp7002(void)
55 {
56 /* REVISIT when it's supported, trigger via Kconfig */
57 return 0;
58 }
59
60 #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
61 /*
62 * A MAX-II CPLD is used for various board control functions.
63 */
64 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
65
66 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
67 #define CPLD_TEST CPLD_OFFSET(0,1)
68 #define CPLD_LEDS CPLD_OFFSET(0,2)
69 #define CPLD_MUX CPLD_OFFSET(0,3)
70 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
71 #define CPLD_POWER CPLD_OFFSET(1,1)
72 #define CPLD_VIDEO CPLD_OFFSET(1,2)
73 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
74
75 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
76 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
77
78 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
79 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
80 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
81 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
82 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
83 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
84 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
85 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
86 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
87
88 #define CPLD_RESETS CPLD_OFFSET(4,3)
89
90 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
91 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
92 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
93 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
94 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
95 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
96
97 static void __iomem *cpld;
98
99
100 /* NOTE: this is geared for the standard config, with a socketed
101 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
102 * swap chips with a different block size, partitioning will
103 * need to be changed. This NAND chip MT29F16G08FAA is the default
104 * NAND shipped with the Spectrum Digital DM365 EVM
105 */
106 #define NAND_BLOCK_SIZE SZ_128K
107
108 static struct mtd_partition davinci_nand_partitions[] = {
109 {
110 /* UBL (a few copies) plus U-Boot */
111 .name = "bootloader",
112 .offset = 0,
113 .size = 30 * NAND_BLOCK_SIZE,
114 .mask_flags = MTD_WRITEABLE, /* force read-only */
115 }, {
116 /* U-Boot environment */
117 .name = "params",
118 .offset = MTDPART_OFS_APPEND,
119 .size = 2 * NAND_BLOCK_SIZE,
120 .mask_flags = 0,
121 }, {
122 .name = "kernel",
123 .offset = MTDPART_OFS_APPEND,
124 .size = SZ_4M,
125 .mask_flags = 0,
126 }, {
127 .name = "filesystem1",
128 .offset = MTDPART_OFS_APPEND,
129 .size = SZ_512M,
130 .mask_flags = 0,
131 }, {
132 .name = "filesystem2",
133 .offset = MTDPART_OFS_APPEND,
134 .size = MTDPART_SIZ_FULL,
135 .mask_flags = 0,
136 }
137 /* two blocks with bad block table (and mirror) at the end */
138 };
139
140 static struct davinci_nand_pdata davinci_nand_data = {
141 .mask_chipsel = BIT(14),
142 .parts = davinci_nand_partitions,
143 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
144 .ecc_mode = NAND_ECC_HW,
145 .bbt_options = NAND_BBT_USE_FLASH,
146 .ecc_bits = 4,
147 };
148
149 static struct resource davinci_nand_resources[] = {
150 {
151 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
152 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
153 .flags = IORESOURCE_MEM,
154 }, {
155 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
156 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
157 .flags = IORESOURCE_MEM,
158 },
159 };
160
161 static struct platform_device davinci_nand_device = {
162 .name = "davinci_nand",
163 .id = 0,
164 .num_resources = ARRAY_SIZE(davinci_nand_resources),
165 .resource = davinci_nand_resources,
166 .dev = {
167 .platform_data = &davinci_nand_data,
168 },
169 };
170
171 static struct at24_platform_data eeprom_info = {
172 .byte_len = (256*1024) / 8,
173 .page_size = 64,
174 .flags = AT24_FLAG_ADDR16,
175 .setup = davinci_get_mac_addr,
176 .context = (void *)0x7f00,
177 };
178
179 static struct snd_platform_data dm365_evm_snd_data = {
180 .asp_chan_q = EVENTQ_3,
181 };
182
183 static struct i2c_board_info i2c_info[] = {
184 {
185 I2C_BOARD_INFO("24c256", 0x50),
186 .platform_data = &eeprom_info,
187 },
188 {
189 I2C_BOARD_INFO("tlv320aic3x", 0x18),
190 },
191 };
192
193 static struct davinci_i2c_platform_data i2c_pdata = {
194 .bus_freq = 400 /* kHz */,
195 .bus_delay = 0 /* usec */,
196 };
197
198 static int dm365evm_keyscan_enable(struct device *dev)
199 {
200 return davinci_cfg_reg(DM365_KEYSCAN);
201 }
202
203 static unsigned short dm365evm_keymap[] = {
204 KEY_KP2,
205 KEY_LEFT,
206 KEY_EXIT,
207 KEY_DOWN,
208 KEY_ENTER,
209 KEY_UP,
210 KEY_KP1,
211 KEY_RIGHT,
212 KEY_MENU,
213 KEY_RECORD,
214 KEY_REWIND,
215 KEY_KPMINUS,
216 KEY_STOP,
217 KEY_FASTFORWARD,
218 KEY_KPPLUS,
219 KEY_PLAYPAUSE,
220 0
221 };
222
223 static struct davinci_ks_platform_data dm365evm_ks_data = {
224 .device_enable = dm365evm_keyscan_enable,
225 .keymap = dm365evm_keymap,
226 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
227 .rep = 1,
228 /* Scan period = strobe + interval */
229 .strobe = 0x5,
230 .interval = 0x2,
231 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
232 };
233
234 static int cpld_mmc_get_cd(int module)
235 {
236 if (!cpld)
237 return -ENXIO;
238
239 /* low == card present */
240 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
241 }
242
243 static int cpld_mmc_get_ro(int module)
244 {
245 if (!cpld)
246 return -ENXIO;
247
248 /* high == card's write protect switch active */
249 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
250 }
251
252 static struct davinci_mmc_config dm365evm_mmc_config = {
253 .get_cd = cpld_mmc_get_cd,
254 .get_ro = cpld_mmc_get_ro,
255 .wires = 4,
256 .max_freq = 50000000,
257 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
258 .version = MMC_CTLR_VERSION_2,
259 };
260
261 static void dm365evm_emac_configure(void)
262 {
263 /*
264 * EMAC pins are multiplexed with GPIO and UART
265 * Further details are available at the DM365 ARM
266 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
267 */
268 davinci_cfg_reg(DM365_EMAC_TX_EN);
269 davinci_cfg_reg(DM365_EMAC_TX_CLK);
270 davinci_cfg_reg(DM365_EMAC_COL);
271 davinci_cfg_reg(DM365_EMAC_TXD3);
272 davinci_cfg_reg(DM365_EMAC_TXD2);
273 davinci_cfg_reg(DM365_EMAC_TXD1);
274 davinci_cfg_reg(DM365_EMAC_TXD0);
275 davinci_cfg_reg(DM365_EMAC_RXD3);
276 davinci_cfg_reg(DM365_EMAC_RXD2);
277 davinci_cfg_reg(DM365_EMAC_RXD1);
278 davinci_cfg_reg(DM365_EMAC_RXD0);
279 davinci_cfg_reg(DM365_EMAC_RX_CLK);
280 davinci_cfg_reg(DM365_EMAC_RX_DV);
281 davinci_cfg_reg(DM365_EMAC_RX_ER);
282 davinci_cfg_reg(DM365_EMAC_CRS);
283 davinci_cfg_reg(DM365_EMAC_MDIO);
284 davinci_cfg_reg(DM365_EMAC_MDCLK);
285
286 /*
287 * EMAC interrupts are multiplexed with GPIO interrupts
288 * Details are available at the DM365 ARM
289 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
290 */
291 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
292 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
293 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
294 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
295 }
296
297 static void dm365evm_mmc_configure(void)
298 {
299 /*
300 * MMC/SD pins are multiplexed with GPIO and EMIF
301 * Further details are available at the DM365 ARM
302 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
303 */
304 davinci_cfg_reg(DM365_SD1_CLK);
305 davinci_cfg_reg(DM365_SD1_CMD);
306 davinci_cfg_reg(DM365_SD1_DATA3);
307 davinci_cfg_reg(DM365_SD1_DATA2);
308 davinci_cfg_reg(DM365_SD1_DATA1);
309 davinci_cfg_reg(DM365_SD1_DATA0);
310 }
311
312 static struct tvp514x_platform_data tvp5146_pdata = {
313 .clk_polarity = 0,
314 .hs_polarity = 1,
315 .vs_polarity = 1
316 };
317
318 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
319 /* Inputs available at the TVP5146 */
320 static struct v4l2_input tvp5146_inputs[] = {
321 {
322 .index = 0,
323 .name = "Composite",
324 .type = V4L2_INPUT_TYPE_CAMERA,
325 .std = TVP514X_STD_ALL,
326 },
327 {
328 .index = 1,
329 .name = "S-Video",
330 .type = V4L2_INPUT_TYPE_CAMERA,
331 .std = TVP514X_STD_ALL,
332 },
333 };
334
335 /*
336 * this is the route info for connecting each input to decoder
337 * ouput that goes to vpfe. There is a one to one correspondence
338 * with tvp5146_inputs
339 */
340 static struct vpfe_route tvp5146_routes[] = {
341 {
342 .input = INPUT_CVBS_VI2B,
343 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
344 },
345 {
346 .input = INPUT_SVIDEO_VI2C_VI1C,
347 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
348 },
349 };
350
351 static struct vpfe_subdev_info vpfe_sub_devs[] = {
352 {
353 .name = "tvp5146",
354 .grp_id = 0,
355 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
356 .inputs = tvp5146_inputs,
357 .routes = tvp5146_routes,
358 .can_route = 1,
359 .ccdc_if_params = {
360 .if_type = VPFE_BT656,
361 .hdpol = VPFE_PINPOL_POSITIVE,
362 .vdpol = VPFE_PINPOL_POSITIVE,
363 },
364 .board_info = {
365 I2C_BOARD_INFO("tvp5146", 0x5d),
366 .platform_data = &tvp5146_pdata,
367 },
368 },
369 };
370
371 static struct vpfe_config vpfe_cfg = {
372 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
373 .sub_devs = vpfe_sub_devs,
374 .i2c_adapter_id = 1,
375 .card_name = "DM365 EVM",
376 .ccdc = "ISIF",
377 };
378
379 /* venc standards timings */
380 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
381 {
382 .name = "ntsc",
383 .timings_type = VPBE_ENC_STD,
384 .std_id = V4L2_STD_525_60,
385 .interlaced = 1,
386 .xres = 720,
387 .yres = 480,
388 .aspect = {11, 10},
389 .fps = {30000, 1001},
390 .left_margin = 0x79,
391 .upper_margin = 0x10,
392 },
393 {
394 .name = "pal",
395 .timings_type = VPBE_ENC_STD,
396 .std_id = V4L2_STD_625_50,
397 .interlaced = 1,
398 .xres = 720,
399 .yres = 576,
400 .aspect = {54, 59},
401 .fps = {25, 1},
402 .left_margin = 0x7E,
403 .upper_margin = 0x16,
404 },
405 };
406
407 /* venc dv timings */
408 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
409 {
410 .name = "480p59_94",
411 .timings_type = VPBE_ENC_DV_TIMINGS,
412 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
413 .interlaced = 0,
414 .xres = 720,
415 .yres = 480,
416 .aspect = {1, 1},
417 .fps = {5994, 100},
418 .left_margin = 0x8F,
419 .upper_margin = 0x2D,
420 },
421 {
422 .name = "576p50",
423 .timings_type = VPBE_ENC_DV_TIMINGS,
424 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
425 .interlaced = 0,
426 .xres = 720,
427 .yres = 576,
428 .aspect = {1, 1},
429 .fps = {50, 1},
430 .left_margin = 0x8C,
431 .upper_margin = 0x36,
432 },
433 {
434 .name = "720p60",
435 .timings_type = VPBE_ENC_DV_TIMINGS,
436 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
437 .interlaced = 0,
438 .xres = 1280,
439 .yres = 720,
440 .aspect = {1, 1},
441 .fps = {60, 1},
442 .left_margin = 0x117,
443 .right_margin = 70,
444 .upper_margin = 38,
445 .lower_margin = 3,
446 .hsync_len = 80,
447 .vsync_len = 5,
448 },
449 {
450 .name = "1080i60",
451 .timings_type = VPBE_ENC_DV_TIMINGS,
452 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
453 .interlaced = 1,
454 .xres = 1920,
455 .yres = 1080,
456 .aspect = {1, 1},
457 .fps = {30, 1},
458 .left_margin = 0xc9,
459 .right_margin = 80,
460 .upper_margin = 30,
461 .lower_margin = 3,
462 .hsync_len = 88,
463 .vsync_len = 5,
464 },
465 };
466
467 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
468
469 /*
470 * The outputs available from VPBE + ecnoders. Keep the
471 * the order same as that of encoders. First those from venc followed by that
472 * from encoders. Index in the output refers to index on a particular
473 * encoder.Driver uses this index to pass it to encoder when it supports more
474 * than one output. Application uses index of the array to set an output.
475 */
476 static struct vpbe_output dm365evm_vpbe_outputs[] = {
477 {
478 .output = {
479 .index = 0,
480 .name = "Composite",
481 .type = V4L2_OUTPUT_TYPE_ANALOG,
482 .std = VENC_STD_ALL,
483 .capabilities = V4L2_OUT_CAP_STD,
484 },
485 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
486 .default_mode = "ntsc",
487 .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
488 .modes = dm365evm_enc_std_timing,
489 .if_params = V4L2_MBUS_FMT_FIXED,
490 },
491 {
492 .output = {
493 .index = 1,
494 .name = "Component",
495 .type = V4L2_OUTPUT_TYPE_ANALOG,
496 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
497 },
498 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
499 .default_mode = "480p59_94",
500 .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
501 .modes = dm365evm_enc_preset_timing,
502 .if_params = V4L2_MBUS_FMT_FIXED,
503 },
504 };
505
506 /*
507 * Amplifiers on the board
508 */
509 struct ths7303_platform_data ths7303_pdata = {
510 .ch_1 = 3,
511 .ch_2 = 3,
512 .ch_3 = 3,
513 .init_enable = 1,
514 };
515
516 static struct amp_config_info vpbe_amp = {
517 .module_name = "ths7303",
518 .is_i2c = 1,
519 .board_info = {
520 I2C_BOARD_INFO("ths7303", 0x2c),
521 .platform_data = &ths7303_pdata,
522 }
523 };
524
525 static struct vpbe_config dm365evm_display_cfg = {
526 .module_name = "dm365-vpbe-display",
527 .i2c_adapter_id = 1,
528 .amp = &vpbe_amp,
529 .osd = {
530 .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
531 },
532 .venc = {
533 .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
534 },
535 .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
536 .outputs = dm365evm_vpbe_outputs,
537 };
538
539 static void __init evm_init_i2c(void)
540 {
541 davinci_init_i2c(&i2c_pdata);
542 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
543 }
544
545 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
546 &davinci_nand_device,
547 };
548
549 static inline int have_leds(void)
550 {
551 #ifdef CONFIG_LEDS_CLASS
552 return 1;
553 #else
554 return 0;
555 #endif
556 }
557
558 struct cpld_led {
559 struct led_classdev cdev;
560 u8 mask;
561 };
562
563 static const struct {
564 const char *name;
565 const char *trigger;
566 } cpld_leds[] = {
567 { "dm365evm::ds2", },
568 { "dm365evm::ds3", },
569 { "dm365evm::ds4", },
570 { "dm365evm::ds5", },
571 { "dm365evm::ds6", "nand-disk", },
572 { "dm365evm::ds7", "mmc1", },
573 { "dm365evm::ds8", "mmc0", },
574 { "dm365evm::ds9", "heartbeat", },
575 };
576
577 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
578 {
579 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
580 u8 reg = __raw_readb(cpld + CPLD_LEDS);
581
582 if (b != LED_OFF)
583 reg &= ~led->mask;
584 else
585 reg |= led->mask;
586 __raw_writeb(reg, cpld + CPLD_LEDS);
587 }
588
589 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
590 {
591 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
592 u8 reg = __raw_readb(cpld + CPLD_LEDS);
593
594 return (reg & led->mask) ? LED_OFF : LED_FULL;
595 }
596
597 static int __init cpld_leds_init(void)
598 {
599 int i;
600
601 if (!have_leds() || !cpld)
602 return 0;
603
604 /* setup LEDs */
605 __raw_writeb(0xff, cpld + CPLD_LEDS);
606 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
607 struct cpld_led *led;
608
609 led = kzalloc(sizeof(*led), GFP_KERNEL);
610 if (!led)
611 break;
612
613 led->cdev.name = cpld_leds[i].name;
614 led->cdev.brightness_set = cpld_led_set;
615 led->cdev.brightness_get = cpld_led_get;
616 led->cdev.default_trigger = cpld_leds[i].trigger;
617 led->mask = BIT(i);
618
619 if (led_classdev_register(NULL, &led->cdev) < 0) {
620 kfree(led);
621 break;
622 }
623 }
624
625 return 0;
626 }
627 /* run after subsys_initcall() for LEDs */
628 fs_initcall(cpld_leds_init);
629
630
631 static void __init evm_init_cpld(void)
632 {
633 u8 mux, resets;
634 const char *label;
635 struct clk *aemif_clk;
636
637 /* Make sure we can configure the CPLD through CS1. Then
638 * leave it on for later access to MMC and LED registers.
639 */
640 aemif_clk = clk_get(NULL, "aemif");
641 if (IS_ERR(aemif_clk))
642 return;
643 clk_prepare_enable(aemif_clk);
644
645 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
646 "cpld") == NULL)
647 goto fail;
648 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
649 if (!cpld) {
650 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
651 SECTION_SIZE);
652 fail:
653 pr_err("ERROR: can't map CPLD\n");
654 clk_disable_unprepare(aemif_clk);
655 return;
656 }
657
658 /* External muxing for some signals */
659 mux = 0;
660
661 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
662 * NOTE: SW4 bus width setting must match!
663 */
664 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
665 /* external keypad mux */
666 mux |= BIT(7);
667
668 platform_add_devices(dm365_evm_nand_devices,
669 ARRAY_SIZE(dm365_evm_nand_devices));
670 } else {
671 /* no OneNAND support yet */
672 }
673
674 /* Leave external chips in reset when unused. */
675 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
676
677 /* Static video input config with SN74CBT16214 1-of-3 mux:
678 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
679 * - port b2 == imager (mux lowbits == 2 or 7)
680 * - port b3 == tvp5146 (mux lowbits == 5)
681 *
682 * Runtime switching could work too, with limitations.
683 */
684 if (have_imager()) {
685 label = "HD imager";
686 mux |= 2;
687
688 /* externally mux MMC1/ENET/AIC33 to imager */
689 mux |= BIT(6) | BIT(5) | BIT(3);
690 } else {
691 struct davinci_soc_info *soc_info = &davinci_soc_info;
692
693 /* we can use MMC1 ... */
694 dm365evm_mmc_configure();
695 davinci_setup_mmc(1, &dm365evm_mmc_config);
696
697 /* ... and ENET ... */
698 dm365evm_emac_configure();
699 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
700 resets &= ~BIT(3);
701
702 /* ... and AIC33 */
703 resets &= ~BIT(1);
704
705 if (have_tvp7002()) {
706 mux |= 1;
707 resets &= ~BIT(2);
708 label = "tvp7002 HD";
709 } else {
710 /* default to tvp5146 */
711 mux |= 5;
712 resets &= ~BIT(0);
713 label = "tvp5146 SD";
714 }
715 }
716 __raw_writeb(mux, cpld + CPLD_MUX);
717 __raw_writeb(resets, cpld + CPLD_RESETS);
718 pr_info("EVM: %s video input\n", label);
719
720 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
721 }
722
723 static struct davinci_uart_config uart_config __initdata = {
724 .enabled_uarts = (1 << 0),
725 };
726
727 static void __init dm365_evm_map_io(void)
728 {
729 dm365_init();
730 }
731
732 static struct spi_eeprom at25640 = {
733 .byte_len = SZ_64K / 8,
734 .name = "at25640",
735 .page_size = 32,
736 .flags = EE_ADDR2,
737 };
738
739 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
740 {
741 .modalias = "at25",
742 .platform_data = &at25640,
743 .max_speed_hz = 10 * 1000 * 1000,
744 .bus_num = 0,
745 .chip_select = 0,
746 .mode = SPI_MODE_0,
747 },
748 };
749
750 static __init void dm365_evm_init(void)
751 {
752 evm_init_i2c();
753 davinci_serial_init(&uart_config);
754
755 dm365evm_emac_configure();
756 dm365evm_mmc_configure();
757
758 davinci_setup_mmc(0, &dm365evm_mmc_config);
759
760 dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
761
762 /* maybe setup mmc1/etc ... _after_ mmc0 */
763 evm_init_cpld();
764
765 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
766 dm365_init_asp(&dm365_evm_snd_data);
767 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
768 dm365_init_vc(&dm365_evm_snd_data);
769 #endif
770 dm365_init_rtc();
771 dm365_init_ks(&dm365evm_ks_data);
772
773 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
774 ARRAY_SIZE(dm365_evm_spi_info));
775 }
776
777 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
778 .atag_offset = 0x100,
779 .map_io = dm365_evm_map_io,
780 .init_irq = davinci_irq_init,
781 .init_time = davinci_timer_init,
782 .init_machine = dm365_evm_init,
783 .init_late = davinci_init_late,
784 .dma_zone_size = SZ_128M,
785 .restart = davinci_restart,
786 MACHINE_END
787
Linux kernel - Deliverables
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