2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/serial_8250.h>
18 #include <mach/cputype.h>
19 #include <mach/common.h>
20 #include <mach/time.h>
21 #include <mach/da8xx.h>
22 #include <mach/cpuidle.h>
26 #define DA8XX_TPCC_BASE 0x01c00000
27 #define DA850_MMCSD1_BASE 0x01e1b000
28 #define DA850_TPCC1_BASE 0x01e30000
29 #define DA8XX_TPTC0_BASE 0x01c08000
30 #define DA8XX_TPTC1_BASE 0x01c08400
31 #define DA850_TPTC2_BASE 0x01e38000
32 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
33 #define DA8XX_I2C0_BASE 0x01c22000
34 #define DA8XX_RTC_BASE 0x01C23000
35 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
36 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
37 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
38 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
39 #define DA8XX_GPIO_BASE 0x01e26000
40 #define DA8XX_I2C1_BASE 0x01e28000
41 #define DA8XX_SPI0_BASE 0x01c41000
42 #define DA830_SPI1_BASE 0x01e12000
43 #define DA850_SPI1_BASE 0x01f0e000
45 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
46 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
47 #define DA8XX_EMAC_RAM_OFFSET 0x0000
48 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
50 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
51 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
52 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
53 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
54 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
55 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
56 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
57 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
59 void __iomem
*da8xx_syscfg0_base
;
60 void __iomem
*da8xx_syscfg1_base
;
62 static struct plat_serial8250_port da8xx_serial_pdata
[] = {
64 .mapbase
= DA8XX_UART0_BASE
,
65 .irq
= IRQ_DA8XX_UARTINT0
,
66 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
72 .mapbase
= DA8XX_UART1_BASE
,
73 .irq
= IRQ_DA8XX_UARTINT1
,
74 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
80 .mapbase
= DA8XX_UART2_BASE
,
81 .irq
= IRQ_DA8XX_UARTINT2
,
82 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
92 struct platform_device da8xx_serial_device
= {
94 .id
= PLAT8250_DEV_PLATFORM
,
96 .platform_data
= da8xx_serial_pdata
,
100 static const s8 da8xx_queue_tc_mapping
[][2] = {
101 /* {event queue no, TC no} */
107 static const s8 da8xx_queue_priority_mapping
[][2] = {
108 /* {event queue no, Priority} */
114 static const s8 da850_queue_tc_mapping
[][2] = {
115 /* {event queue no, TC no} */
120 static const s8 da850_queue_priority_mapping
[][2] = {
121 /* {event queue no, Priority} */
126 static struct edma_soc_info da830_edma_cc0_info
= {
132 .queue_tc_mapping
= da8xx_queue_tc_mapping
,
133 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
136 static struct edma_soc_info
*da830_edma_info
[EDMA_MAX_CC
] = {
137 &da830_edma_cc0_info
,
140 static struct edma_soc_info da850_edma_cc_info
[] = {
147 .queue_tc_mapping
= da8xx_queue_tc_mapping
,
148 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
156 .queue_tc_mapping
= da850_queue_tc_mapping
,
157 .queue_priority_mapping
= da850_queue_priority_mapping
,
161 static struct edma_soc_info
*da850_edma_info
[EDMA_MAX_CC
] = {
162 &da850_edma_cc_info
[0],
163 &da850_edma_cc_info
[1],
166 static struct resource da830_edma_resources
[] = {
169 .start
= DA8XX_TPCC_BASE
,
170 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
171 .flags
= IORESOURCE_MEM
,
175 .start
= DA8XX_TPTC0_BASE
,
176 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
177 .flags
= IORESOURCE_MEM
,
181 .start
= DA8XX_TPTC1_BASE
,
182 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
183 .flags
= IORESOURCE_MEM
,
187 .start
= IRQ_DA8XX_CCINT0
,
188 .flags
= IORESOURCE_IRQ
,
192 .start
= IRQ_DA8XX_CCERRINT
,
193 .flags
= IORESOURCE_IRQ
,
197 static struct resource da850_edma_resources
[] = {
200 .start
= DA8XX_TPCC_BASE
,
201 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
202 .flags
= IORESOURCE_MEM
,
206 .start
= DA8XX_TPTC0_BASE
,
207 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
208 .flags
= IORESOURCE_MEM
,
212 .start
= DA8XX_TPTC1_BASE
,
213 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
214 .flags
= IORESOURCE_MEM
,
218 .start
= DA850_TPCC1_BASE
,
219 .end
= DA850_TPCC1_BASE
+ SZ_32K
- 1,
220 .flags
= IORESOURCE_MEM
,
224 .start
= DA850_TPTC2_BASE
,
225 .end
= DA850_TPTC2_BASE
+ SZ_1K
- 1,
226 .flags
= IORESOURCE_MEM
,
230 .start
= IRQ_DA8XX_CCINT0
,
231 .flags
= IORESOURCE_IRQ
,
235 .start
= IRQ_DA8XX_CCERRINT
,
236 .flags
= IORESOURCE_IRQ
,
240 .start
= IRQ_DA850_CCINT1
,
241 .flags
= IORESOURCE_IRQ
,
245 .start
= IRQ_DA850_CCERRINT1
,
246 .flags
= IORESOURCE_IRQ
,
250 static struct platform_device da830_edma_device
= {
254 .platform_data
= da830_edma_info
,
256 .num_resources
= ARRAY_SIZE(da830_edma_resources
),
257 .resource
= da830_edma_resources
,
260 static struct platform_device da850_edma_device
= {
264 .platform_data
= da850_edma_info
,
266 .num_resources
= ARRAY_SIZE(da850_edma_resources
),
267 .resource
= da850_edma_resources
,
270 int __init
da830_register_edma(struct edma_rsv_info
*rsv
)
272 da830_edma_cc0_info
.rsv
= rsv
;
274 return platform_device_register(&da830_edma_device
);
277 int __init
da850_register_edma(struct edma_rsv_info
*rsv
[2])
280 da850_edma_cc_info
[0].rsv
= rsv
[0];
281 da850_edma_cc_info
[1].rsv
= rsv
[1];
284 return platform_device_register(&da850_edma_device
);
287 static struct resource da8xx_i2c_resources0
[] = {
289 .start
= DA8XX_I2C0_BASE
,
290 .end
= DA8XX_I2C0_BASE
+ SZ_4K
- 1,
291 .flags
= IORESOURCE_MEM
,
294 .start
= IRQ_DA8XX_I2CINT0
,
295 .end
= IRQ_DA8XX_I2CINT0
,
296 .flags
= IORESOURCE_IRQ
,
300 static struct platform_device da8xx_i2c_device0
= {
301 .name
= "i2c_davinci",
303 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources0
),
304 .resource
= da8xx_i2c_resources0
,
307 static struct resource da8xx_i2c_resources1
[] = {
309 .start
= DA8XX_I2C1_BASE
,
310 .end
= DA8XX_I2C1_BASE
+ SZ_4K
- 1,
311 .flags
= IORESOURCE_MEM
,
314 .start
= IRQ_DA8XX_I2CINT1
,
315 .end
= IRQ_DA8XX_I2CINT1
,
316 .flags
= IORESOURCE_IRQ
,
320 static struct platform_device da8xx_i2c_device1
= {
321 .name
= "i2c_davinci",
323 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources1
),
324 .resource
= da8xx_i2c_resources1
,
327 int __init
da8xx_register_i2c(int instance
,
328 struct davinci_i2c_platform_data
*pdata
)
330 struct platform_device
*pdev
;
333 pdev
= &da8xx_i2c_device0
;
334 else if (instance
== 1)
335 pdev
= &da8xx_i2c_device1
;
339 pdev
->dev
.platform_data
= pdata
;
340 return platform_device_register(pdev
);
343 static struct resource da8xx_watchdog_resources
[] = {
345 .start
= DA8XX_WDOG_BASE
,
346 .end
= DA8XX_WDOG_BASE
+ SZ_4K
- 1,
347 .flags
= IORESOURCE_MEM
,
351 struct platform_device da8xx_wdt_device
= {
354 .num_resources
= ARRAY_SIZE(da8xx_watchdog_resources
),
355 .resource
= da8xx_watchdog_resources
,
358 int __init
da8xx_register_watchdog(void)
360 return platform_device_register(&da8xx_wdt_device
);
363 static struct resource da8xx_emac_resources
[] = {
365 .start
= DA8XX_EMAC_CPPI_PORT_BASE
,
366 .end
= DA8XX_EMAC_CPPI_PORT_BASE
+ SZ_16K
- 1,
367 .flags
= IORESOURCE_MEM
,
370 .start
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
371 .end
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
372 .flags
= IORESOURCE_IRQ
,
375 .start
= IRQ_DA8XX_C0_RX_PULSE
,
376 .end
= IRQ_DA8XX_C0_RX_PULSE
,
377 .flags
= IORESOURCE_IRQ
,
380 .start
= IRQ_DA8XX_C0_TX_PULSE
,
381 .end
= IRQ_DA8XX_C0_TX_PULSE
,
382 .flags
= IORESOURCE_IRQ
,
385 .start
= IRQ_DA8XX_C0_MISC_PULSE
,
386 .end
= IRQ_DA8XX_C0_MISC_PULSE
,
387 .flags
= IORESOURCE_IRQ
,
391 struct emac_platform_data da8xx_emac_pdata
= {
392 .ctrl_reg_offset
= DA8XX_EMAC_CTRL_REG_OFFSET
,
393 .ctrl_mod_reg_offset
= DA8XX_EMAC_MOD_REG_OFFSET
,
394 .ctrl_ram_offset
= DA8XX_EMAC_RAM_OFFSET
,
395 .ctrl_ram_size
= DA8XX_EMAC_CTRL_RAM_SIZE
,
396 .version
= EMAC_VERSION_2
,
399 static struct platform_device da8xx_emac_device
= {
400 .name
= "davinci_emac",
403 .platform_data
= &da8xx_emac_pdata
,
405 .num_resources
= ARRAY_SIZE(da8xx_emac_resources
),
406 .resource
= da8xx_emac_resources
,
409 static struct resource da8xx_mdio_resources
[] = {
411 .start
= DA8XX_EMAC_MDIO_BASE
,
412 .end
= DA8XX_EMAC_MDIO_BASE
+ SZ_4K
- 1,
413 .flags
= IORESOURCE_MEM
,
417 static struct platform_device da8xx_mdio_device
= {
418 .name
= "davinci_mdio",
420 .num_resources
= ARRAY_SIZE(da8xx_mdio_resources
),
421 .resource
= da8xx_mdio_resources
,
424 int __init
da8xx_register_emac(void)
428 ret
= platform_device_register(&da8xx_mdio_device
);
431 ret
= platform_device_register(&da8xx_emac_device
);
434 ret
= clk_add_alias(NULL
, dev_name(&da8xx_mdio_device
.dev
),
435 NULL
, &da8xx_emac_device
.dev
);
439 static struct resource da830_mcasp1_resources
[] = {
442 .start
= DAVINCI_DA830_MCASP1_REG_BASE
,
443 .end
= DAVINCI_DA830_MCASP1_REG_BASE
+ (SZ_1K
* 12) - 1,
444 .flags
= IORESOURCE_MEM
,
448 .start
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
449 .end
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
450 .flags
= IORESOURCE_DMA
,
454 .start
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
455 .end
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
456 .flags
= IORESOURCE_DMA
,
460 static struct platform_device da830_mcasp1_device
= {
461 .name
= "davinci-mcasp",
463 .num_resources
= ARRAY_SIZE(da830_mcasp1_resources
),
464 .resource
= da830_mcasp1_resources
,
467 static struct resource da850_mcasp_resources
[] = {
470 .start
= DAVINCI_DA8XX_MCASP0_REG_BASE
,
471 .end
= DAVINCI_DA8XX_MCASP0_REG_BASE
+ (SZ_1K
* 12) - 1,
472 .flags
= IORESOURCE_MEM
,
476 .start
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
477 .end
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
478 .flags
= IORESOURCE_DMA
,
482 .start
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
483 .end
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
484 .flags
= IORESOURCE_DMA
,
488 static struct platform_device da850_mcasp_device
= {
489 .name
= "davinci-mcasp",
491 .num_resources
= ARRAY_SIZE(da850_mcasp_resources
),
492 .resource
= da850_mcasp_resources
,
495 struct platform_device davinci_pcm_device
= {
496 .name
= "davinci-pcm-audio",
500 void __init
da8xx_register_mcasp(int id
, struct snd_platform_data
*pdata
)
502 platform_device_register(&davinci_pcm_device
);
504 /* DA830/OMAP-L137 has 3 instances of McASP */
505 if (cpu_is_davinci_da830() && id
== 1) {
506 da830_mcasp1_device
.dev
.platform_data
= pdata
;
507 platform_device_register(&da830_mcasp1_device
);
508 } else if (cpu_is_davinci_da850()) {
509 da850_mcasp_device
.dev
.platform_data
= pdata
;
510 platform_device_register(&da850_mcasp_device
);
514 static const struct display_panel disp_panel
= {
521 static struct lcd_ctrl_config lcd_cfg
= {
531 .invert_line_clock
= 1,
532 .invert_frm_clock
= 1,
538 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata
= {
539 .manu_name
= "sharp",
540 .controller_data
= &lcd_cfg
,
541 .type
= "Sharp_LCD035Q3DG01",
544 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata
= {
545 .manu_name
= "sharp",
546 .controller_data
= &lcd_cfg
,
547 .type
= "Sharp_LK043T1DG01",
550 static struct resource da8xx_lcdc_resources
[] = {
551 [0] = { /* registers */
552 .start
= DA8XX_LCD_CNTRL_BASE
,
553 .end
= DA8XX_LCD_CNTRL_BASE
+ SZ_4K
- 1,
554 .flags
= IORESOURCE_MEM
,
556 [1] = { /* interrupt */
557 .start
= IRQ_DA8XX_LCDINT
,
558 .end
= IRQ_DA8XX_LCDINT
,
559 .flags
= IORESOURCE_IRQ
,
563 static struct platform_device da8xx_lcdc_device
= {
564 .name
= "da8xx_lcdc",
566 .num_resources
= ARRAY_SIZE(da8xx_lcdc_resources
),
567 .resource
= da8xx_lcdc_resources
,
570 int __init
da8xx_register_lcdc(struct da8xx_lcdc_platform_data
*pdata
)
572 da8xx_lcdc_device
.dev
.platform_data
= pdata
;
573 return platform_device_register(&da8xx_lcdc_device
);
576 static struct resource da8xx_mmcsd0_resources
[] = {
578 .start
= DA8XX_MMCSD0_BASE
,
579 .end
= DA8XX_MMCSD0_BASE
+ SZ_4K
- 1,
580 .flags
= IORESOURCE_MEM
,
583 .start
= IRQ_DA8XX_MMCSDINT0
,
584 .end
= IRQ_DA8XX_MMCSDINT0
,
585 .flags
= IORESOURCE_IRQ
,
588 .start
= DA8XX_DMA_MMCSD0_RX
,
589 .end
= DA8XX_DMA_MMCSD0_RX
,
590 .flags
= IORESOURCE_DMA
,
593 .start
= DA8XX_DMA_MMCSD0_TX
,
594 .end
= DA8XX_DMA_MMCSD0_TX
,
595 .flags
= IORESOURCE_DMA
,
599 static struct platform_device da8xx_mmcsd0_device
= {
600 .name
= "davinci_mmc",
602 .num_resources
= ARRAY_SIZE(da8xx_mmcsd0_resources
),
603 .resource
= da8xx_mmcsd0_resources
,
606 int __init
da8xx_register_mmcsd0(struct davinci_mmc_config
*config
)
608 da8xx_mmcsd0_device
.dev
.platform_data
= config
;
609 return platform_device_register(&da8xx_mmcsd0_device
);
612 #ifdef CONFIG_ARCH_DAVINCI_DA850
613 static struct resource da850_mmcsd1_resources
[] = {
615 .start
= DA850_MMCSD1_BASE
,
616 .end
= DA850_MMCSD1_BASE
+ SZ_4K
- 1,
617 .flags
= IORESOURCE_MEM
,
620 .start
= IRQ_DA850_MMCSDINT0_1
,
621 .end
= IRQ_DA850_MMCSDINT0_1
,
622 .flags
= IORESOURCE_IRQ
,
625 .start
= DA850_DMA_MMCSD1_RX
,
626 .end
= DA850_DMA_MMCSD1_RX
,
627 .flags
= IORESOURCE_DMA
,
630 .start
= DA850_DMA_MMCSD1_TX
,
631 .end
= DA850_DMA_MMCSD1_TX
,
632 .flags
= IORESOURCE_DMA
,
636 static struct platform_device da850_mmcsd1_device
= {
637 .name
= "davinci_mmc",
639 .num_resources
= ARRAY_SIZE(da850_mmcsd1_resources
),
640 .resource
= da850_mmcsd1_resources
,
643 int __init
da850_register_mmcsd1(struct davinci_mmc_config
*config
)
645 da850_mmcsd1_device
.dev
.platform_data
= config
;
646 return platform_device_register(&da850_mmcsd1_device
);
650 static struct resource da8xx_rtc_resources
[] = {
652 .start
= DA8XX_RTC_BASE
,
653 .end
= DA8XX_RTC_BASE
+ SZ_4K
- 1,
654 .flags
= IORESOURCE_MEM
,
657 .start
= IRQ_DA8XX_RTC
,
658 .end
= IRQ_DA8XX_RTC
,
659 .flags
= IORESOURCE_IRQ
,
662 .start
= IRQ_DA8XX_RTC
,
663 .end
= IRQ_DA8XX_RTC
,
664 .flags
= IORESOURCE_IRQ
,
668 static struct platform_device da8xx_rtc_device
= {
671 .num_resources
= ARRAY_SIZE(da8xx_rtc_resources
),
672 .resource
= da8xx_rtc_resources
,
675 int da8xx_register_rtc(void)
680 base
= ioremap(DA8XX_RTC_BASE
, SZ_4K
);
684 /* Unlock the rtc's registers */
685 __raw_writel(0x83e70b13, base
+ 0x6c);
686 __raw_writel(0x95a4f1e0, base
+ 0x70);
690 ret
= platform_device_register(&da8xx_rtc_device
);
692 /* Atleast on DA850, RTC is a wakeup source */
693 device_init_wakeup(&da8xx_rtc_device
.dev
, true);
698 static void __iomem
*da8xx_ddr2_ctlr_base
;
699 void __iomem
* __init
da8xx_get_mem_ctlr(void)
701 if (da8xx_ddr2_ctlr_base
)
702 return da8xx_ddr2_ctlr_base
;
704 da8xx_ddr2_ctlr_base
= ioremap(DA8XX_DDR2_CTL_BASE
, SZ_32K
);
705 if (!da8xx_ddr2_ctlr_base
)
706 pr_warning("%s: Unable to map DDR2 controller", __func__
);
708 return da8xx_ddr2_ctlr_base
;
711 static struct resource da8xx_cpuidle_resources
[] = {
713 .start
= DA8XX_DDR2_CTL_BASE
,
714 .end
= DA8XX_DDR2_CTL_BASE
+ SZ_32K
- 1,
715 .flags
= IORESOURCE_MEM
,
719 /* DA8XX devices support DDR2 power down */
720 static struct davinci_cpuidle_config da8xx_cpuidle_pdata
= {
725 static struct platform_device da8xx_cpuidle_device
= {
726 .name
= "cpuidle-davinci",
727 .num_resources
= ARRAY_SIZE(da8xx_cpuidle_resources
),
728 .resource
= da8xx_cpuidle_resources
,
730 .platform_data
= &da8xx_cpuidle_pdata
,
734 int __init
da8xx_register_cpuidle(void)
736 da8xx_cpuidle_pdata
.ddr2_ctlr_base
= da8xx_get_mem_ctlr();
738 return platform_device_register(&da8xx_cpuidle_device
);
741 static struct resource da8xx_spi0_resources
[] = {
743 .start
= DA8XX_SPI0_BASE
,
744 .end
= DA8XX_SPI0_BASE
+ SZ_4K
- 1,
745 .flags
= IORESOURCE_MEM
,
748 .start
= IRQ_DA8XX_SPINT0
,
749 .end
= IRQ_DA8XX_SPINT0
,
750 .flags
= IORESOURCE_IRQ
,
753 .start
= DA8XX_DMA_SPI0_RX
,
754 .end
= DA8XX_DMA_SPI0_RX
,
755 .flags
= IORESOURCE_DMA
,
758 .start
= DA8XX_DMA_SPI0_TX
,
759 .end
= DA8XX_DMA_SPI0_TX
,
760 .flags
= IORESOURCE_DMA
,
764 static struct resource da8xx_spi1_resources
[] = {
766 .start
= DA830_SPI1_BASE
,
767 .end
= DA830_SPI1_BASE
+ SZ_4K
- 1,
768 .flags
= IORESOURCE_MEM
,
771 .start
= IRQ_DA8XX_SPINT1
,
772 .end
= IRQ_DA8XX_SPINT1
,
773 .flags
= IORESOURCE_IRQ
,
776 .start
= DA8XX_DMA_SPI1_RX
,
777 .end
= DA8XX_DMA_SPI1_RX
,
778 .flags
= IORESOURCE_DMA
,
781 .start
= DA8XX_DMA_SPI1_TX
,
782 .end
= DA8XX_DMA_SPI1_TX
,
783 .flags
= IORESOURCE_DMA
,
787 struct davinci_spi_platform_data da8xx_spi_pdata
[] = {
789 .version
= SPI_VERSION_2
,
791 .dma_event_q
= EVENTQ_0
,
794 .version
= SPI_VERSION_2
,
796 .dma_event_q
= EVENTQ_0
,
800 static struct platform_device da8xx_spi_device
[] = {
802 .name
= "spi_davinci",
804 .num_resources
= ARRAY_SIZE(da8xx_spi0_resources
),
805 .resource
= da8xx_spi0_resources
,
807 .platform_data
= &da8xx_spi_pdata
[0],
811 .name
= "spi_davinci",
813 .num_resources
= ARRAY_SIZE(da8xx_spi1_resources
),
814 .resource
= da8xx_spi1_resources
,
816 .platform_data
= &da8xx_spi_pdata
[1],
821 int __init
da8xx_register_spi(int instance
, struct spi_board_info
*info
,
826 if (instance
< 0 || instance
> 1)
829 ret
= spi_register_board_info(info
, len
);
831 pr_warning("%s: failed to register board info for spi %d :"
832 " %d\n", __func__
, instance
, ret
);
834 da8xx_spi_pdata
[instance
].num_chipselect
= len
;
836 if (instance
== 1 && cpu_is_davinci_da850()) {
837 da8xx_spi1_resources
[0].start
= DA850_SPI1_BASE
;
838 da8xx_spi1_resources
[0].end
= DA850_SPI1_BASE
+ SZ_4K
- 1;
841 return platform_device_register(&da8xx_spi_device
[instance
]);