arch/arm/mach-exynos/exynos.c

   1 /*
   2  * SAMSUNG EXYNOS Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/serial_s3c.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/memory.h>
  28
  29 #include <plat/cpu.h>
  30
  31 #include "common.h"
  32 #include "mfc.h"
  33 #include "regs-pmu.h"
  34
  35 static struct map_desc exynos4_iodesc[] __initdata = {
  36         {
  37                 .virtual        = (unsigned long)S3C_VA_SYS,
  38                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  39                 .length         = SZ_64K,
  40                 .type           = MT_DEVICE,
  41         }, {
  42                 .virtual        = (unsigned long)S3C_VA_TIMER,
  43                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
  44                 .length         = SZ_16K,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  48                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  49                 .length         = SZ_4K,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = (unsigned long)S5P_VA_SROMC,
  53                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  54                 .length         = SZ_4K,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  58                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  59                 .length         = SZ_4K,
  60                 .type           = MT_DEVICE,
  61         }, {
  62                 .virtual        = (unsigned long)S5P_VA_PMU,
  63                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  64                 .length         = SZ_64K,
  65                 .type           = MT_DEVICE,
  66         }, {
  67                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  68                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  69                 .length         = SZ_4K,
  70                 .type           = MT_DEVICE,
  71         }, {
  72                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
  73                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  74                 .length         = SZ_64K,
  75                 .type           = MT_DEVICE,
  76         }, {
  77                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
  78                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  79                 .length         = SZ_64K,
  80                 .type           = MT_DEVICE,
  81         }, {
  82                 .virtual        = (unsigned long)S5P_VA_CMU,
  83                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  84                 .length         = SZ_128K,
  85                 .type           = MT_DEVICE,
  86         }, {
  87                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  88                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  89                 .length         = SZ_8K,
  90                 .type           = MT_DEVICE,
  91         }, {
  92                 .virtual        = (unsigned long)S5P_VA_L2CC,
  93                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  94                 .length         = SZ_4K,
  95                 .type           = MT_DEVICE,
  96         }, {
  97                 .virtual        = (unsigned long)S5P_VA_DMC0,
  98                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  99                 .length         = SZ_64K,
 100                 .type           = MT_DEVICE,
 101         }, {
 102                 .virtual        = (unsigned long)S5P_VA_DMC1,
 103                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 104                 .length         = SZ_64K,
 105                 .type           = MT_DEVICE,
 106         }, {
 107                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 108                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 109                 .length         = SZ_4K,
 110                 .type           = MT_DEVICE,
 111         },
 112 };
 113
 114 static struct map_desc exynos4_iodesc0[] __initdata = {
 115         {
 116                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 117                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE,
 120         },
 121 };
 122
 123 static struct map_desc exynos4_iodesc1[] __initdata = {
 124         {
 125                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 126                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE,
 129         },
 130 };
 131
 132 static struct map_desc exynos4210_iodesc[] __initdata = {
 133         {
 134                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 135                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         },
 139 };
 140
 141 static struct map_desc exynos4x12_iodesc[] __initdata = {
 142         {
 143                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 144                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 145                 .length         = SZ_4K,
 146                 .type           = MT_DEVICE,
 147         },
 148 };
 149
 150 static struct map_desc exynos5250_iodesc[] __initdata = {
 151         {
 152                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 153                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 154                 .length         = SZ_4K,
 155                 .type           = MT_DEVICE,
 156         },
 157 };
 158
 159 static struct map_desc exynos5_iodesc[] __initdata = {
 160         {
 161                 .virtual        = (unsigned long)S3C_VA_SYS,
 162                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 163                 .length         = SZ_64K,
 164                 .type           = MT_DEVICE,
 165         }, {
 166                 .virtual        = (unsigned long)S3C_VA_TIMER,
 167                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 168                 .length         = SZ_16K,
 169                 .type           = MT_DEVICE,
 170         }, {
 171                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 172                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 173                 .length         = SZ_4K,
 174                 .type           = MT_DEVICE,
 175         }, {
 176                 .virtual        = (unsigned long)S5P_VA_SROMC,
 177                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 178                 .length         = SZ_4K,
 179                 .type           = MT_DEVICE,
 180         }, {
 181                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 182                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 183                 .length         = SZ_4K,
 184                 .type           = MT_DEVICE,
 185         }, {
 186                 .virtual        = (unsigned long)S5P_VA_CMU,
 187                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 188                 .length         = 144 * SZ_1K,
 189                 .type           = MT_DEVICE,
 190         }, {
 191                 .virtual        = (unsigned long)S5P_VA_PMU,
 192                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 193                 .length         = SZ_64K,
 194                 .type           = MT_DEVICE,
 195         },
 196 };
 197
 198 void exynos_restart(enum reboot_mode mode, const char *cmd)
 199 {
 200         struct device_node *np;
 201         u32 val = 0x1;
 202         void __iomem *addr = EXYNOS_SWRESET;
 203
 204         if (of_machine_is_compatible("samsung,exynos5440")) {
 205                 u32 status;
 206                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 207
 208                 addr = of_iomap(np, 0) + 0xbc;
 209                 status = __raw_readl(addr);
 210
 211                 addr = of_iomap(np, 0) + 0xcc;
 212                 val = __raw_readl(addr);
 213
 214                 val = (val & 0xffff0000) | (status & 0xffff);
 215         }
 216
 217         __raw_writel(val, addr);
 218 }
 219
 220 static struct platform_device exynos_cpuidle = {
 221         .name           = "exynos_cpuidle",
 222         .id             = -1,
 223 };
 224
 225 void __init exynos_cpuidle_init(void)
 226 {
 227         platform_device_register(&exynos_cpuidle);
 228 }
 229
 230 void __init exynos_cpufreq_init(void)
 231 {
 232         platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 233 }
 234
 235 void __init exynos_init_late(void)
 236 {
 237         if (of_machine_is_compatible("samsung,exynos5440"))
 238                 /* to be supported later */
 239                 return;
 240
 241         pm_genpd_poweroff_unused();
 242         exynos_pm_init();
 243 }
 244
 245 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 246                                         int depth, void *data)
 247 {
 248         struct map_desc iodesc;
 249         __be32 *reg;
 250         unsigned long len;
 251
 252         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 253                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 254                 return 0;
 255
 256         reg = of_get_flat_dt_prop(node, "reg", &len);
 257         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 258                 return 0;
 259
 260         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 261         iodesc.length = be32_to_cpu(reg[1]) - 1;
 262         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 263         iodesc.type = MT_DEVICE;
 264         iotable_init(&iodesc, 1);
 265         return 1;
 266 }
 267
 268 /*
 269  * exynos_map_io
 270  *
 271  * register the standard cpu IO areas
 272  */
 273 static void __init exynos_map_io(void)
 274 {
 275         if (soc_is_exynos4())
 276                 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 277
 278         if (soc_is_exynos5())
 279                 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 280
 281         if (soc_is_exynos4210()) {
 282                 if (samsung_rev() == EXYNOS4210_REV_0)
 283                         iotable_init(exynos4_iodesc0,
 284                                                 ARRAY_SIZE(exynos4_iodesc0));
 285                 else
 286                         iotable_init(exynos4_iodesc1,
 287                                                 ARRAY_SIZE(exynos4_iodesc1));
 288                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 289         }
 290         if (soc_is_exynos4212() || soc_is_exynos4412())
 291                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 292         if (soc_is_exynos5250())
 293                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 294 }
 295
 296 void __init exynos_init_io(void)
 297 {
 298         debug_ll_io_init();
 299
 300         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 301
 302         /* detect cpu id and rev. */
 303         s5p_init_cpu(S5P_VA_CHIPID);
 304
 305         exynos_map_io();
 306 }
 307
 308 struct bus_type exynos_subsys = {
 309         .name           = "exynos-core",
 310         .dev_name       = "exynos-core",
 311 };
 312
 313 static int __init exynos_core_init(void)
 314 {
 315         return subsys_system_register(&exynos_subsys, NULL);
 316 }
 317 core_initcall(exynos_core_init);
 318
 319 static int __init exynos4_l2x0_cache_init(void)
 320 {
 321         int ret;
 322
 323         ret = l2x0_of_init(0x3c400001, 0xc20fffff);
 324         if (ret)
 325                 return ret;
 326
 327         if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
 328                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 329                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 330         }
 331         return 0;
 332 }
 333 early_initcall(exynos4_l2x0_cache_init);
 334
 335 static void __init exynos_dt_machine_init(void)
 336 {
 337         struct device_node *i2c_np;
 338         const char *i2c_compat = "samsung,s3c2440-i2c";
 339         unsigned int tmp;
 340         int id;
 341
 342         /*
 343          * Exynos5's legacy i2c controller and new high speed i2c
 344          * controller have muxed interrupt sources. By default the
 345          * interrupts for 4-channel HS-I2C controller are enabled.
 346          * If node for first four channels of legacy i2c controller
 347          * are available then re-configure the interrupts via the
 348          * system register.
 349          */
 350         if (soc_is_exynos5()) {
 351                 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
 352                         if (of_device_is_available(i2c_np)) {
 353                                 id = of_alias_get_id(i2c_np, "i2c");
 354                                 if (id < 4) {
 355                                         tmp = readl(EXYNOS5_SYS_I2C_CFG);
 356                                         writel(tmp & ~(0x1 << id),
 357                                                         EXYNOS5_SYS_I2C_CFG);
 358                                 }
 359                         }
 360                 }
 361         }
 362
 363         exynos_cpuidle_init();
 364         exynos_cpufreq_init();
 365
 366         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 367 }
 368
 369 static char const *exynos_dt_compat[] __initconst = {
 370         "samsung,exynos4",
 371         "samsung,exynos4210",
 372         "samsung,exynos4212",
 373         "samsung,exynos4412",
 374         "samsung,exynos5",
 375         "samsung,exynos5250",
 376         "samsung,exynos5420",
 377         "samsung,exynos5440",
 378         NULL
 379 };
 380
 381 static void __init exynos_reserve(void)
 382 {
 383 #ifdef CONFIG_S5P_DEV_MFC
 384         int i;
 385         char *mfc_mem[] = {
 386                 "samsung,mfc-v5",
 387                 "samsung,mfc-v6",
 388                 "samsung,mfc-v7",
 389         };
 390
 391         for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
 392                 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
 393                         break;
 394 #endif
 395 }
 396
 397 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 398         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
 399         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 400         .smp            = smp_ops(exynos_smp_ops),
 401         .map_io         = exynos_init_io,
 402         .init_early     = exynos_firmware_init,
 403         .init_machine   = exynos_dt_machine_init,
 404         .init_late      = exynos_init_late,
 405         .dt_compat      = exynos_dt_compat,
 406         .restart        = exynos_restart,
 407         .reserve        = exynos_reserve,
 408 MACHINE_END