arch/arm/mach-exynos4/setup-sdhci.c

   1 /* linux/arch/arm/mach-exynos4/setup-sdhci.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18
  19 #include <linux/mmc/card.h>
  20 #include <linux/mmc/host.h>
  21
  22 #include <plat/regs-sdhci.h>
  23
  24 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
  25
  26 char *exynos4_hsmmc_clksrcs[4] = {
  27         [0] = NULL,
  28         [1] = NULL,
  29         [2] = "sclk_mmc",       /* mmc_bus */
  30         [3] = NULL,
  31 };
  32
  33 void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
  34                                   struct mmc_ios *ios, struct mmc_card *card)
  35 {
  36         u32 ctrl2, ctrl3;
  37
  38         /* don't need to alter anything acording to card-type */
  39
  40         ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
  41
  42         /* select base clock source to HCLK */
  43
  44         ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  45
  46         /*
  47          * clear async mode, enable conflict mask, rx feedback ctrl, SD
  48          * clk hold and no use debounce count
  49          */
  50
  51         ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
  52                   S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
  53                   S3C_SDHCI_CTRL2_ENFBCLKRX |
  54                   S3C_SDHCI_CTRL2_DFCNT_NONE |
  55                   S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
  56
  57         /* Tx and Rx feedback clock delay control */
  58
  59         if (ios->clock < 25 * 1000000)
  60                 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
  61                          S3C_SDHCI_CTRL3_FCSEL2 |
  62                          S3C_SDHCI_CTRL3_FCSEL1 |
  63                          S3C_SDHCI_CTRL3_FCSEL0);
  64         else
  65                 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
  66
  67         writel(ctrl2, r + S3C_SDHCI_CONTROL2);
  68         writel(ctrl3, r + S3C_SDHCI_CONTROL3);
  69 }