arch/arm/mach-imx/mach-cpuimx51sd.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/i2c/tsc2007.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/i2c-gpio.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/can/platform/mcp251x.h>
  28
  29 #include <asm/setup.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/time.h>
  33
  34 #include "common.h"
  35 #include "devices-imx51.h"
  36 #include "cpu_op-mx51.h"
  37 #include "eukrea-baseboards.h"
  38 #include "hardware.h"
  39 #include "iomux-mx51.h"
  40
  41 #define USBH1_RST               IMX_GPIO_NR(2, 28)
  42 #define ETH_RST                 IMX_GPIO_NR(2, 31)
  43 #define TSC2007_IRQGPIO_REV2    IMX_GPIO_NR(3, 12)
  44 #define TSC2007_IRQGPIO_REV3    IMX_GPIO_NR(4, 0)
  45 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
  46 #define CAN_RST                 IMX_GPIO_NR(4, 15)
  47 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
  48 #define CAN_RXOBF_REV2          IMX_GPIO_NR(1, 4)
  49 #define CAN_RXOBF_REV3          IMX_GPIO_NR(3, 12)
  50 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
  51 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
  52 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
  53 #define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
  54 #define I2C_SCL                 IMX_GPIO_NR(4, 16)
  55 #define I2C_SDA                 IMX_GPIO_NR(4, 17)
  56
  57 /* USB_CTRL_1 */
  58 #define MX51_USB_CTRL_1_OFFSET          0x10
  59 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  60
  61 #define MX51_USB_PLLDIV_12_MHZ          0x00
  62 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  63 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  64
  65 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
  66         /* UART1 */
  67         MX51_PAD_UART1_RXD__UART1_RXD,
  68         MX51_PAD_UART1_TXD__UART1_TXD,
  69         MX51_PAD_UART1_RTS__UART1_RTS,
  70         MX51_PAD_UART1_CTS__UART1_CTS,
  71
  72         /* USB HOST1 */
  73         MX51_PAD_USBH1_CLK__USBH1_CLK,
  74         MX51_PAD_USBH1_DIR__USBH1_DIR,
  75         MX51_PAD_USBH1_NXT__USBH1_NXT,
  76         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  77         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  78         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  79         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  80         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  81         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  82         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  83         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  84         MX51_PAD_USBH1_STP__USBH1_STP,
  85         MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
  86
  87         /* FEC */
  88         MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
  89
  90         /* HSI2C */
  91         MX51_PAD_I2C1_CLK__GPIO4_16,
  92         MX51_PAD_I2C1_DAT__GPIO4_17,
  93
  94         /* I2C1 */
  95         MX51_PAD_SD2_CMD__I2C1_SCL,
  96         MX51_PAD_SD2_CLK__I2C1_SDA,
  97
  98         /* CAN */
  99         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
 100         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
 101         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 102         MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
 103         MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
 104         MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
 105         MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
 106         MX51_PAD_GPIO1_6__GPIO1_6,
 107         MX51_PAD_GPIO1_7__GPIO1_7,
 108         MX51_PAD_GPIO1_8__GPIO1_8,
 109         MX51_PAD_GPIO1_9__GPIO1_9,
 110
 111         /* Touchscreen */
 112         /* IRQ */
 113         NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
 114                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 115                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 116         NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
 117                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 118                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 119 };
 120
 121 static const struct imxuart_platform_data uart_pdata __initconst = {
 122         .flags = IMXUART_HAVE_RTSCTS,
 123 };
 124
 125 static int tsc2007_get_pendown_state(void)
 126 {
 127         if (mx51_revision() < IMX_CHIP_REVISION_3_0)
 128                 return !gpio_get_value(TSC2007_IRQGPIO_REV2);
 129         else
 130                 return !gpio_get_value(TSC2007_IRQGPIO_REV3);
 131 }
 132
 133 static struct tsc2007_platform_data tsc2007_info = {
 134         .model                  = 2007,
 135         .x_plate_ohms           = 180,
 136         .get_pendown_state      = tsc2007_get_pendown_state,
 137 };
 138
 139 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 140         {
 141                 I2C_BOARD_INFO("pcf8563", 0x51),
 142         }, {
 143                 I2C_BOARD_INFO("tsc2007", 0x49),
 144                 .platform_data  = &tsc2007_info,
 145         },
 146 };
 147
 148 static const struct mxc_nand_platform_data
 149                 eukrea_cpuimx51sd_nand_board_info __initconst = {
 150         .width          = 1,
 151         .hw_ecc         = 1,
 152         .flash_bbt      = 1,
 153 };
 154
 155 /* This function is board specific as the bit mask for the plldiv will also
 156 be different for other Freescale SoCs, thus a common bitmask is not
 157 possible and cannot get place in /plat-mxc/ehci.c.*/
 158 static int initialize_otg_port(struct platform_device *pdev)
 159 {
 160         u32 v;
 161         void __iomem *usb_base;
 162         void __iomem *usbother_base;
 163
 164         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 165         if (!usb_base)
 166                 return -ENOMEM;
 167         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 168
 169         /* Set the PHY clock to 19.2MHz */
 170         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 171         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 172         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 173         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 174         iounmap(usb_base);
 175
 176         mdelay(10);
 177
 178         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 179 }
 180
 181 static int initialize_usbh1_port(struct platform_device *pdev)
 182 {
 183         u32 v;
 184         void __iomem *usb_base;
 185         void __iomem *usbother_base;
 186
 187         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 188         if (!usb_base)
 189                 return -ENOMEM;
 190         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 191
 192         /* The clock for the USBH1 ULPI port will come from the PHY. */
 193         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 194         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
 195                         usbother_base + MX51_USB_CTRL_1_OFFSET);
 196         iounmap(usb_base);
 197
 198         mdelay(10);
 199
 200         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 201                         MXC_EHCI_ITC_NO_THRESHOLD);
 202 }
 203
 204 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
 205         .init           = initialize_otg_port,
 206         .portsc = MXC_EHCI_UTMI_16BIT,
 207 };
 208
 209 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 210         .operating_mode = FSL_USB2_DR_DEVICE,
 211         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 212 };
 213
 214 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
 215         .init           = initialize_usbh1_port,
 216         .portsc = MXC_EHCI_MODE_ULPI,
 217 };
 218
 219 static bool otg_mode_host __initdata;
 220
 221 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 222 {
 223         if (!strcmp(options, "host"))
 224                 otg_mode_host = true;
 225         else if (!strcmp(options, "device"))
 226                 otg_mode_host = false;
 227         else
 228                 pr_info("otg_mode neither \"host\" nor \"device\". "
 229                         "Defaulting to device\n");
 230         return 1;
 231 }
 232 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 233
 234 static struct i2c_gpio_platform_data pdata = {
 235         .sda_pin                = I2C_SDA,
 236         .sda_is_open_drain      = 0,
 237         .scl_pin                = I2C_SCL,
 238         .scl_is_open_drain      = 0,
 239         .udelay                 = 2,
 240 };
 241
 242 static struct platform_device hsi2c_gpio_device = {
 243         .name                   = "i2c-gpio",
 244         .id                     = 0,
 245         .dev.platform_data      = &pdata,
 246 };
 247
 248 static struct mcp251x_platform_data mcp251x_info = {
 249         .oscillator_frequency = 24E6,
 250 };
 251
 252 static struct spi_board_info cpuimx51sd_spi_device[] = {
 253         {
 254                 .modalias        = "mcp2515",
 255                 .max_speed_hz    = 10000000,
 256                 .bus_num         = 0,
 257                 .mode           = SPI_MODE_0,
 258                 .chip_select     = 0,
 259                 .platform_data   = &mcp251x_info,
 260                 /* irq number is run-time assigned */
 261         },
 262 };
 263
 264 static int cpuimx51sd_spi1_cs[] = {
 265         CAN_NCS,
 266 };
 267
 268 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
 269         .chipselect     = cpuimx51sd_spi1_cs,
 270         .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 271 };
 272
 273 static struct platform_device *rev2_platform_devices[] __initdata = {
 274         &hsi2c_gpio_device,
 275 };
 276
 277 static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
 278         .bitrate = 100000,
 279 };
 280
 281 static void __init eukrea_cpuimx51sd_init(void)
 282 {
 283         imx51_soc_init();
 284
 285         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
 286                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 287
 288 #if defined(CONFIG_CPU_FREQ_IMX)
 289         get_cpu_op = mx51_get_cpu_op;
 290 #endif
 291
 292         imx51_add_imx_uart(0, &uart_pdata);
 293         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 294         imx51_add_imx2_wdt(0);
 295
 296         gpio_request(ETH_RST, "eth_rst");
 297         gpio_set_value(ETH_RST, 1);
 298         imx51_add_fec(NULL);
 299
 300         gpio_request(CAN_IRQGPIO, "can_irq");
 301         gpio_direction_input(CAN_IRQGPIO);
 302         gpio_free(CAN_IRQGPIO);
 303         gpio_request(CAN_NCS, "can_ncs");
 304         gpio_direction_output(CAN_NCS, 1);
 305         gpio_free(CAN_NCS);
 306         gpio_request(CAN_RST, "can_rst");
 307         gpio_direction_output(CAN_RST, 0);
 308         msleep(20);
 309         gpio_set_value(CAN_RST, 1);
 310         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
 311         cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
 312         spi_register_board_info(cpuimx51sd_spi_device,
 313                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 314
 315         if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
 316                 eukrea_cpuimx51sd_i2c_devices[1].irq =
 317                         gpio_to_irq(TSC2007_IRQGPIO_REV2),
 318                 platform_add_devices(rev2_platform_devices,
 319                         ARRAY_SIZE(rev2_platform_devices));
 320                 gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
 321                 gpio_direction_input(TSC2007_IRQGPIO_REV2);
 322                 gpio_free(TSC2007_IRQGPIO_REV2);
 323         } else {
 324                 eukrea_cpuimx51sd_i2c_devices[1].irq =
 325                         gpio_to_irq(TSC2007_IRQGPIO_REV3),
 326                 imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
 327                 gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
 328                 gpio_direction_input(TSC2007_IRQGPIO_REV3);
 329                 gpio_free(TSC2007_IRQGPIO_REV3);
 330         }
 331
 332         i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 333                         ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 334
 335         if (otg_mode_host)
 336                 imx51_add_mxc_ehci_otg(&dr_utmi_config);
 337         else {
 338                 initialize_otg_port(NULL);
 339                 imx51_add_fsl_usb2_udc(&usb_pdata);
 340         }
 341
 342         gpio_request(USBH1_RST, "usb_rst");
 343         gpio_direction_output(USBH1_RST, 0);
 344         msleep(20);
 345         gpio_set_value(USBH1_RST, 1);
 346         imx51_add_mxc_ehci_hs(1, &usbh1_config);
 347
 348 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
 349         eukrea_mbimxsd51_baseboard_init();
 350 #endif
 351 }
 352
 353 static void __init eukrea_cpuimx51sd_timer_init(void)
 354 {
 355         mx51_clocks_init(32768, 24000000, 22579200, 0);
 356 }
 357
 358 static struct sys_timer mxc_timer = {
 359         .init   = eukrea_cpuimx51sd_timer_init,
 360 };
 361
 362 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 363         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 364         .atag_offset = 0x100,
 365         .map_io = mx51_map_io,
 366         .init_early = imx51_init_early,
 367         .init_irq = mx51_init_irq,
 368         .handle_irq = imx51_handle_irq,
 369         .timer = &mxc_timer,
 370         .init_machine = eukrea_cpuimx51sd_init,
 371         .init_late      = imx51_init_late,
 372         .restart        = mxc_restart,
 373 MACHINE_END