arch/arm/mach-imx/mach-mx27ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/map.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/i2c.h>
  23 #include <linux/irq.h>
  24 #include <mach/common.h>
  25 #include <mach/hardware.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/time.h>
  29 #include <asm/mach/map.h>
  30 #include <mach/gpio.h>
  31 #include <mach/iomux-mx27.h>
  32
  33 #include "devices-imx27.h"
  34
  35 /*
  36  * Base address of PBC controller, CS4
  37  */
  38 #define PBC_BASE_ADDRESS        0xf4300000
  39 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
  40                 (PBC_BASE_ADDRESS + (offset))
  41
  42 /* When the PBC address connection is fixed in h/w, defined as 1 */
  43 #define PBC_ADDR_SH             0
  44
  45 /* Offsets for the PBC Controller register */
  46 /*
  47  * PBC Board version register offset
  48  */
  49 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
  50 /*
  51  * PBC Board control register 1 set address.
  52  */
  53 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
  54 /*
  55  * PBC Board control register 1 clear address.
  56  */
  57 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
  58
  59 /* PBC Board Control Register 1 bit definitions */
  60 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
  61
  62 /* to determine the correct external crystal reference */
  63 #define CKIH_27MHZ_BIT_SET      (1 << 3)
  64
  65 static const int mx27ads_pins[] __initconst = {
  66         /* UART0 */
  67         PE12_PF_UART1_TXD,
  68         PE13_PF_UART1_RXD,
  69         PE14_PF_UART1_CTS,
  70         PE15_PF_UART1_RTS,
  71         /* UART1 */
  72         PE3_PF_UART2_CTS,
  73         PE4_PF_UART2_RTS,
  74         PE6_PF_UART2_TXD,
  75         PE7_PF_UART2_RXD,
  76         /* UART2 */
  77         PE8_PF_UART3_TXD,
  78         PE9_PF_UART3_RXD,
  79         PE10_PF_UART3_CTS,
  80         PE11_PF_UART3_RTS,
  81         /* UART3 */
  82         PB26_AF_UART4_RTS,
  83         PB28_AF_UART4_TXD,
  84         PB29_AF_UART4_CTS,
  85         PB31_AF_UART4_RXD,
  86         /* UART4 */
  87         PB18_AF_UART5_TXD,
  88         PB19_AF_UART5_RXD,
  89         PB20_AF_UART5_CTS,
  90         PB21_AF_UART5_RTS,
  91         /* UART5 */
  92         PB10_AF_UART6_TXD,
  93         PB12_AF_UART6_CTS,
  94         PB11_AF_UART6_RXD,
  95         PB13_AF_UART6_RTS,
  96         /* FEC */
  97         PD0_AIN_FEC_TXD0,
  98         PD1_AIN_FEC_TXD1,
  99         PD2_AIN_FEC_TXD2,
 100         PD3_AIN_FEC_TXD3,
 101         PD4_AOUT_FEC_RX_ER,
 102         PD5_AOUT_FEC_RXD1,
 103         PD6_AOUT_FEC_RXD2,
 104         PD7_AOUT_FEC_RXD3,
 105         PD8_AF_FEC_MDIO,
 106         PD9_AIN_FEC_MDC,
 107         PD10_AOUT_FEC_CRS,
 108         PD11_AOUT_FEC_TX_CLK,
 109         PD12_AOUT_FEC_RXD0,
 110         PD13_AOUT_FEC_RX_DV,
 111         PD14_AOUT_FEC_RX_CLK,
 112         PD15_AOUT_FEC_COL,
 113         PD16_AIN_FEC_TX_ER,
 114         PF23_AIN_FEC_TX_EN,
 115         /* I2C2 */
 116         PC5_PF_I2C2_SDA,
 117         PC6_PF_I2C2_SCL,
 118         /* FB */
 119         PA5_PF_LSCLK,
 120         PA6_PF_LD0,
 121         PA7_PF_LD1,
 122         PA8_PF_LD2,
 123         PA9_PF_LD3,
 124         PA10_PF_LD4,
 125         PA11_PF_LD5,
 126         PA12_PF_LD6,
 127         PA13_PF_LD7,
 128         PA14_PF_LD8,
 129         PA15_PF_LD9,
 130         PA16_PF_LD10,
 131         PA17_PF_LD11,
 132         PA18_PF_LD12,
 133         PA19_PF_LD13,
 134         PA20_PF_LD14,
 135         PA21_PF_LD15,
 136         PA22_PF_LD16,
 137         PA23_PF_LD17,
 138         PA24_PF_REV,
 139         PA25_PF_CLS,
 140         PA26_PF_PS,
 141         PA27_PF_SPL_SPR,
 142         PA28_PF_HSYNC,
 143         PA29_PF_VSYNC,
 144         PA30_PF_CONTRAST,
 145         PA31_PF_OE_ACD,
 146         /* OWIRE */
 147         PE16_AF_OWIRE,
 148         /* SDHC1*/
 149         PE18_PF_SD1_D0,
 150         PE19_PF_SD1_D1,
 151         PE20_PF_SD1_D2,
 152         PE21_PF_SD1_D3,
 153         PE22_PF_SD1_CMD,
 154         PE23_PF_SD1_CLK,
 155         /* SDHC2*/
 156         PB4_PF_SD2_D0,
 157         PB5_PF_SD2_D1,
 158         PB6_PF_SD2_D2,
 159         PB7_PF_SD2_D3,
 160         PB8_PF_SD2_CMD,
 161         PB9_PF_SD2_CLK,
 162 };
 163
 164 static const struct mxc_nand_platform_data
 165 mx27ads_nand_board_info __initconst = {
 166         .width = 1,
 167         .hw_ecc = 1,
 168 };
 169
 170 /* ADS's NOR flash */
 171 static struct physmap_flash_data mx27ads_flash_data = {
 172         .width = 2,
 173 };
 174
 175 static struct resource mx27ads_flash_resource = {
 176         .start = 0xc0000000,
 177         .end = 0xc0000000 + 0x02000000 - 1,
 178         .flags = IORESOURCE_MEM,
 179
 180 };
 181
 182 static struct platform_device mx27ads_nor_mtd_device = {
 183         .name = "physmap-flash",
 184         .id = 0,
 185         .dev = {
 186                 .platform_data = &mx27ads_flash_data,
 187         },
 188         .num_resources = 1,
 189         .resource = &mx27ads_flash_resource,
 190 };
 191
 192 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
 193         .bitrate = 100000,
 194 };
 195
 196 static struct i2c_board_info mx27ads_i2c_devices[] = {
 197 };
 198
 199 void lcd_power(int on)
 200 {
 201         if (on)
 202                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
 203         else
 204                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 205 }
 206
 207 static struct imx_fb_videomode mx27ads_modes[] = {
 208         {
 209                 .mode = {
 210                         .name           = "Sharp-LQ035Q7",
 211                         .refresh        = 60,
 212                         .xres           = 240,
 213                         .yres           = 320,
 214                         .pixclock       = 188679, /* in ps (5.3MHz) */
 215                         .hsync_len      = 1,
 216                         .left_margin    = 9,
 217                         .right_margin   = 16,
 218                         .vsync_len      = 1,
 219                         .upper_margin   = 7,
 220                         .lower_margin   = 9,
 221                 },
 222                 .bpp            = 16,
 223                 .pcr            = 0xFB008BC0,
 224         },
 225 };
 226
 227 static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 228         .mode = mx27ads_modes,
 229         .num_modes = ARRAY_SIZE(mx27ads_modes),
 230
 231         /*
 232          * - HSYNC active high
 233          * - VSYNC active high
 234          * - clk notenabled while idle
 235          * - clock inverted
 236          * - data not inverted
 237          * - data enable low active
 238          * - enable sharp mode
 239          */
 240         .pwmr           = 0x00A903FF,
 241         .lscr1          = 0x00120300,
 242         .dmacr          = 0x00020010,
 243
 244         .lcd_power      = lcd_power,
 245 };
 246
 247 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 248                               void *data)
 249 {
 250         return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
 251                            "sdhc1-card-detect", data);
 252 }
 253
 254 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 255                               void *data)
 256 {
 257         return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
 258                            "sdhc2-card-detect", data);
 259 }
 260
 261 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 262 {
 263         free_irq(IRQ_GPIOE(21), data);
 264 }
 265
 266 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 267 {
 268         free_irq(IRQ_GPIOB(7), data);
 269 }
 270
 271 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
 272         .init = mx27ads_sdhc1_init,
 273         .exit = mx27ads_sdhc1_exit,
 274 };
 275
 276 static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
 277         .init = mx27ads_sdhc2_init,
 278         .exit = mx27ads_sdhc2_exit,
 279 };
 280
 281 static struct platform_device *platform_devices[] __initdata = {
 282         &mx27ads_nor_mtd_device,
 283 };
 284
 285 static const struct imxuart_platform_data uart_pdata __initconst = {
 286         .flags = IMXUART_HAVE_RTSCTS,
 287 };
 288
 289 static void __init mx27ads_board_init(void)
 290 {
 291         imx27_soc_init();
 292
 293         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 294                         "mx27ads");
 295
 296         imx27_add_imx_uart0(&uart_pdata);
 297         imx27_add_imx_uart1(&uart_pdata);
 298         imx27_add_imx_uart2(&uart_pdata);
 299         imx27_add_imx_uart3(&uart_pdata);
 300         imx27_add_imx_uart4(&uart_pdata);
 301         imx27_add_imx_uart5(&uart_pdata);
 302         imx27_add_mxc_nand(&mx27ads_nand_board_info);
 303
 304         /* only the i2c master 1 is used on this CPU card */
 305         i2c_register_board_info(1, mx27ads_i2c_devices,
 306                                 ARRAY_SIZE(mx27ads_i2c_devices));
 307         imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
 308         imx27_add_imx_fb(&mx27ads_fb_data);
 309         imx27_add_mxc_mmc(0, &sdhc1_pdata);
 310         imx27_add_mxc_mmc(1, &sdhc2_pdata);
 311
 312         imx27_add_fec(NULL);
 313         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 314         imx27_add_mxc_w1(NULL);
 315 }
 316
 317 static void __init mx27ads_timer_init(void)
 318 {
 319         unsigned long fref = 26000000;
 320
 321         if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
 322                 fref = 27000000;
 323
 324         mx27_clocks_init(fref);
 325 }
 326
 327 static struct sys_timer mx27ads_timer = {
 328         .init   = mx27ads_timer_init,
 329 };
 330
 331 static struct map_desc mx27ads_io_desc[] __initdata = {
 332         {
 333                 .virtual = PBC_BASE_ADDRESS,
 334                 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
 335                 .length = SZ_1M,
 336                 .type = MT_DEVICE,
 337         },
 338 };
 339
 340 static void __init mx27ads_map_io(void)
 341 {
 342         mx27_map_io();
 343         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
 344 }
 345
 346 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 347         /* maintainer: Freescale Semiconductor, Inc. */
 348         .atag_offset = 0x100,
 349         .map_io = mx27ads_map_io,
 350         .init_early = imx27_init_early,
 351         .init_irq = mx27_init_irq,
 352         .timer = &mx27ads_timer,
 353         .init_machine = mx27ads_board_init,
 354 MACHINE_END