2 * arch/arm/mach-ixp2000/ixdp2x01.c
4 * Code common to Intel IXDP2401 and IXDP2801 platforms
6 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9 * Copyright (C) 2002-2003 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/pci.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/serial.h>
30 #include <linux/tty.h>
31 #include <linux/serial_core.h>
32 #include <linux/platform_device.h>
36 #include <asm/pgtable.h>
38 #include <asm/system.h>
39 #include <asm/hardware.h>
40 #include <asm/mach-types.h>
42 #include <asm/mach/pci.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/arch.h>
47 #include <asm/mach/flash.h>
49 /*************************************************************************
50 * IXDP2x01 IRQ Handling
51 *************************************************************************/
52 static void ixdp2x01_irq_mask(unsigned int irq
)
54 ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG
,
55 IXP2000_BOARD_IRQ_MASK(irq
));
58 static void ixdp2x01_irq_unmask(unsigned int irq
)
60 ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG
,
61 IXP2000_BOARD_IRQ_MASK(irq
));
64 static u32 valid_irq_mask
;
66 static void ixdp2x01_irq_handler(unsigned int irq
, struct irqdesc
*desc
, struct pt_regs
*regs
)
71 desc
->chip
->mask(irq
);
73 ex_interrupt
= *IXDP2X01_INT_STAT_REG
& valid_irq_mask
;
76 printk(KERN_ERR
"Spurious IXDP2X01 CPLD interrupt!\n");
80 for (i
= 0; i
< IXP2000_BOARD_IRQS
; i
++) {
81 if (ex_interrupt
& (1 << i
)) {
82 struct irqdesc
*cpld_desc
;
83 int cpld_irq
= IXP2000_BOARD_IRQ(0) + i
;
84 cpld_desc
= irq_desc
+ cpld_irq
;
85 desc_handle_irq(cpld_irq
, cpld_desc
, regs
);
89 desc
->chip
->unmask(irq
);
92 static struct irqchip ixdp2x01_irq_chip
= {
93 .mask
= ixdp2x01_irq_mask
,
94 .ack
= ixdp2x01_irq_mask
,
95 .unmask
= ixdp2x01_irq_unmask
99 * We only do anything if we are the master NPU on the board.
100 * The slave NPU only has the ethernet chip going directly to
101 * the PCIB interrupt input.
103 void __init
ixdp2x01_init_irq(void)
107 /* initialize chip specific interrupts */
110 if (machine_is_ixdp2401())
111 valid_irq_mask
= IXDP2401_VALID_IRQ_MASK
;
113 valid_irq_mask
= IXDP2801_VALID_IRQ_MASK
;
115 /* Mask all interrupts from CPLD, disable simulation */
116 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG
, 0xffffffff);
117 ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG
, 0);
119 for (irq
= NR_IXP2000_IRQS
; irq
< NR_IXDP2X01_IRQS
; irq
++) {
120 if (irq
& valid_irq_mask
) {
121 set_irq_chip(irq
, &ixdp2x01_irq_chip
);
122 set_irq_handler(irq
, do_level_IRQ
);
123 set_irq_flags(irq
, IRQF_VALID
);
125 set_irq_flags(irq
, 0);
129 /* Hook into PCI interrupts */
130 set_irq_chained_handler(IRQ_IXP2000_PCIB
, &ixdp2x01_irq_handler
);
134 /*************************************************************************
135 * IXDP2x01 memory map and serial ports
136 *************************************************************************/
137 static struct map_desc ixdp2x01_io_desc __initdata
= {
138 .virtual = IXDP2X01_VIRT_CPLD_BASE
,
139 .pfn
= __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE
),
140 .length
= IXDP2X01_CPLD_REGION_SIZE
,
144 static struct uart_port ixdp2x01_serial_ports
[2] = {
146 .membase
= (char *)(IXDP2X01_UART1_VIRT_BASE
),
147 .mapbase
= (unsigned long)IXDP2X01_UART1_PHYS_BASE
,
148 .irq
= IRQ_IXDP2X01_UART1
,
149 .flags
= UPF_SKIP_TEST
,
150 .iotype
= UPIO_MEM32
,
152 .uartclk
= IXDP2X01_UART_CLK
,
157 .membase
= (char *)(IXDP2X01_UART2_VIRT_BASE
),
158 .mapbase
= (unsigned long)IXDP2X01_UART2_PHYS_BASE
,
159 .irq
= IRQ_IXDP2X01_UART2
,
160 .flags
= UPF_SKIP_TEST
,
161 .iotype
= UPIO_MEM32
,
163 .uartclk
= IXDP2X01_UART_CLK
,
170 static void __init
ixdp2x01_map_io(void)
174 iotable_init(&ixdp2x01_io_desc
, 1);
176 early_serial_setup(&ixdp2x01_serial_ports
[0]);
177 early_serial_setup(&ixdp2x01_serial_ports
[1]);
181 /*************************************************************************
182 * IXDP2x01 timer tick configuration
183 *************************************************************************/
184 static unsigned int ixdp2x01_clock
;
186 static int __init
ixdp2x01_clock_setup(char *str
)
188 ixdp2x01_clock
= simple_strtoul(str
, NULL
, 10);
193 __setup("ixdp2x01_clock=", ixdp2x01_clock_setup
);
195 static void __init
ixdp2x01_timer_init(void)
198 ixdp2x01_clock
= 50000000;
200 ixp2000_init_time(ixdp2x01_clock
);
203 static struct sys_timer ixdp2x01_timer
= {
204 .init
= ixdp2x01_timer_init
,
205 .offset
= ixp2000_gettimeoffset
,
208 /*************************************************************************
210 *************************************************************************/
211 void __init
ixdp2x01_pci_preinit(void)
213 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT
, 0x00000000);
214 ixp2000_pci_preinit();
215 pcibios_setup("firmware");
218 #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
220 static int __init
ixdp2x01_pci_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
222 u8 bus
= dev
->bus
->number
;
223 u32 devpin
= DEVPIN(PCI_SLOT(dev
->devfn
), pin
);
224 struct pci_bus
*tmp_bus
= dev
->bus
;
226 /* Primary bus, no interrupts here */
231 /* Lookup first leaf in bus tree */
232 while ((tmp_bus
->parent
!= NULL
) && (tmp_bus
->parent
->parent
!= NULL
)) {
233 tmp_bus
= tmp_bus
->parent
;
236 /* Select between known bridges */
237 switch (tmp_bus
->self
->devfn
| (tmp_bus
->self
->bus
->number
<< 8)) {
238 /* Device is located after first MB bridge */
240 if (tmp_bus
== dev
->bus
) {
241 /* Device is located directy after first MB bridge */
243 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
244 if (machine_is_ixdp2401())
245 return IRQ_IXDP2401_INTA_82546
;
247 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
248 if (machine_is_ixdp2401())
249 return IRQ_IXDP2401_INTB_82546
;
251 case DEVPIN(0, 1): /* PMC INTA# */
252 return IRQ_IXDP2X01_SPCI_PMC_INTA
;
253 case DEVPIN(0, 2): /* PMC INTB# */
254 return IRQ_IXDP2X01_SPCI_PMC_INTB
;
255 case DEVPIN(0, 3): /* PMC INTC# */
256 return IRQ_IXDP2X01_SPCI_PMC_INTC
;
257 case DEVPIN(0, 4): /* PMC INTD# */
258 return IRQ_IXDP2X01_SPCI_PMC_INTD
;
263 if (tmp_bus
== dev
->bus
) {
264 /* Device is located directy after second MB bridge */
265 /* Secondary bus of second bridge */
267 case DEVPIN(0, 1): /* DB#0 */
268 return IRQ_IXDP2X01_SPCI_DB_0
;
269 case DEVPIN(1, 1): /* DB#1 */
270 return IRQ_IXDP2X01_SPCI_DB_1
;
273 /* Device is located indirectly after second MB bridge */
274 /* Not supported now */
283 static int ixdp2x01_pci_setup(int nr
, struct pci_sys_data
*sys
)
285 sys
->mem_offset
= 0xe0000000;
287 if (machine_is_ixdp2801())
288 sys
->mem_offset
-= ((*IXP2000_PCI_ADDR_EXT
& 0xE000) << 16);
290 return ixp2000_pci_setup(nr
, sys
);
293 struct hw_pci ixdp2x01_pci __initdata
= {
295 .setup
= ixdp2x01_pci_setup
,
296 .preinit
= ixdp2x01_pci_preinit
,
297 .scan
= ixp2000_pci_scan_bus
,
298 .map_irq
= ixdp2x01_pci_map_irq
,
301 int __init
ixdp2x01_pci_init(void)
303 if (machine_is_ixdp2401() || machine_is_ixdp2801())
304 pci_common_init(&ixdp2x01_pci
);
309 subsys_initcall(ixdp2x01_pci_init
);
311 /*************************************************************************
312 * IXDP2x01 Machine Intialization
313 *************************************************************************/
314 static struct flash_platform_data ixdp2x01_flash_platform_data
= {
315 .map_name
= "cfi_probe",
319 static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs
)
321 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG
,
322 ((ofs
>> IXDP2X01_FLASH_WINDOW_BITS
) | IXDP2X01_CPLD_FLASH_INTERN
));
323 return (ofs
& IXDP2X01_FLASH_WINDOW_MASK
);
326 static struct ixp2000_flash_data ixdp2x01_flash_data
= {
327 .platform_data
= &ixdp2x01_flash_platform_data
,
328 .bank_setup
= ixdp2x01_flash_bank_setup
331 static struct resource ixdp2x01_flash_resource
= {
333 .end
= 0xc4000000 + 0x01ffffff,
334 .flags
= IORESOURCE_MEM
,
337 static struct platform_device ixdp2x01_flash
= {
338 .name
= "IXP2000-Flash",
341 .platform_data
= &ixdp2x01_flash_data
,
344 .resource
= &ixdp2x01_flash_resource
,
347 static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins
= {
348 .sda_pin
= IXDP2X01_GPIO_SDA
,
349 .scl_pin
= IXDP2X01_GPIO_SCL
,
352 static struct platform_device ixdp2x01_i2c_controller
= {
353 .name
= "IXP2000-I2C",
356 .platform_data
= &ixdp2x01_i2c_gpio_pins
,
361 static struct platform_device
*ixdp2x01_devices
[] __initdata
= {
363 &ixdp2x01_i2c_controller
366 static void __init
ixdp2x01_init_machine(void)
368 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG
,
369 (IXDP2X01_CPLD_FLASH_BANK_MASK
| IXDP2X01_CPLD_FLASH_INTERN
));
371 ixdp2x01_flash_data
.nr_banks
=
372 ((*IXDP2X01_CPLD_FLASH_REG
& IXDP2X01_CPLD_FLASH_BANK_MASK
) + 1);
374 platform_add_devices(ixdp2x01_devices
, ARRAY_SIZE(ixdp2x01_devices
));
379 #ifdef CONFIG_ARCH_IXDP2401
380 MACHINE_START(IXDP2401
, "Intel IXDP2401 Development Platform")
381 /* Maintainer: MontaVista Software, Inc. */
382 .phys_io
= IXP2000_UART_PHYS_BASE
,
383 .io_pg_offst
= ((IXP2000_UART_VIRT_BASE
) >> 18) & 0xfffc,
384 .boot_params
= 0x00000100,
385 .map_io
= ixdp2x01_map_io
,
386 .init_irq
= ixdp2x01_init_irq
,
387 .timer
= &ixdp2x01_timer
,
388 .init_machine
= ixdp2x01_init_machine
,
392 #ifdef CONFIG_ARCH_IXDP2801
393 MACHINE_START(IXDP2801
, "Intel IXDP2801 Development Platform")
394 /* Maintainer: MontaVista Software, Inc. */
395 .phys_io
= IXP2000_UART_PHYS_BASE
,
396 .io_pg_offst
= ((IXP2000_UART_VIRT_BASE
) >> 18) & 0xfffc,
397 .boot_params
= 0x00000100,
398 .map_io
= ixdp2x01_map_io
,
399 .init_irq
= ixdp2x01_init_irq
,
400 .timer
= &ixdp2x01_timer
,
401 .init_machine
= ixdp2x01_init_machine
,