2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/sched.h>
21 #include <linux/tty.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_core.h>
24 #include <linux/bootmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
29 #include <linux/clocksource.h>
31 #include <asm/arch/udc.h>
32 #include <asm/hardware.h>
33 #include <asm/uaccess.h>
35 #include <asm/pgtable.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/time.h>
43 static int __init
ixp4xx_clocksource_init(void);
45 /*************************************************************************
46 * IXP4xx chipset I/O mapping
47 *************************************************************************/
48 static struct map_desc ixp4xx_io_desc
[] __initdata
= {
49 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
50 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT
,
51 .pfn
= __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS
),
52 .length
= IXP4XX_PERIPHERAL_REGION_SIZE
,
54 }, { /* Expansion Bus Config Registers */
55 .virtual = IXP4XX_EXP_CFG_BASE_VIRT
,
56 .pfn
= __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS
),
57 .length
= IXP4XX_EXP_CFG_REGION_SIZE
,
59 }, { /* PCI Registers */
60 .virtual = IXP4XX_PCI_CFG_BASE_VIRT
,
61 .pfn
= __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS
),
62 .length
= IXP4XX_PCI_CFG_REGION_SIZE
,
65 #ifdef CONFIG_DEBUG_LL
66 { /* Debug UART mapping */
67 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT
,
68 .pfn
= __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS
),
69 .length
= IXP4XX_DEBUG_UART_REGION_SIZE
,
75 void __init
ixp4xx_map_io(void)
77 iotable_init(ixp4xx_io_desc
, ARRAY_SIZE(ixp4xx_io_desc
));
81 /*************************************************************************
82 * IXP4xx chipset IRQ handling
84 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
85 * (be it PCI or something else) configures that GPIO line
87 **************************************************************************/
88 enum ixp4xx_irq_type
{
89 IXP4XX_IRQ_LEVEL
, IXP4XX_IRQ_EDGE
92 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
93 static unsigned long long ixp4xx_irq_edge
= 0;
96 * IRQ -> GPIO mapping table
98 static signed char irq2gpio
[32] = {
99 -1, -1, -1, -1, -1, -1, 0, 1,
100 -1, -1, -1, -1, -1, -1, -1, -1,
101 -1, -1, -1, 2, 3, 4, 5, 6,
102 7, 8, 9, 10, 11, 12, -1, -1,
105 static int ixp4xx_set_irq_type(unsigned int irq
, unsigned int type
)
107 int line
= irq2gpio
[irq
];
109 enum ixp4xx_irq_type irq_type
;
110 volatile u32
*int_reg
;
120 int_style
= IXP4XX_GPIO_STYLE_TRANSITIONAL
;
121 irq_type
= IXP4XX_IRQ_EDGE
;
124 int_style
= IXP4XX_GPIO_STYLE_RISING_EDGE
;
125 irq_type
= IXP4XX_IRQ_EDGE
;
128 int_style
= IXP4XX_GPIO_STYLE_FALLING_EDGE
;
129 irq_type
= IXP4XX_IRQ_EDGE
;
132 int_style
= IXP4XX_GPIO_STYLE_ACTIVE_HIGH
;
133 irq_type
= IXP4XX_IRQ_LEVEL
;
136 int_style
= IXP4XX_GPIO_STYLE_ACTIVE_LOW
;
137 irq_type
= IXP4XX_IRQ_LEVEL
;
143 if (irq_type
== IXP4XX_IRQ_EDGE
)
144 ixp4xx_irq_edge
|= (1 << irq
);
146 ixp4xx_irq_edge
&= ~(1 << irq
);
148 if (line
>= 8) { /* pins 8-15 */
150 int_reg
= IXP4XX_GPIO_GPIT2R
;
151 } else { /* pins 0-7 */
152 int_reg
= IXP4XX_GPIO_GPIT1R
;
155 /* Clear the style for the appropriate pin */
156 *int_reg
&= ~(IXP4XX_GPIO_STYLE_CLEAR
<<
157 (line
* IXP4XX_GPIO_STYLE_SIZE
));
159 *IXP4XX_GPIO_GPISR
= (1 << line
);
161 /* Set the new style */
162 *int_reg
|= (int_style
<< (line
* IXP4XX_GPIO_STYLE_SIZE
));
164 /* Configure the line as an input */
165 gpio_line_config(line
, IXP4XX_GPIO_IN
);
170 static void ixp4xx_irq_mask(unsigned int irq
)
172 if (cpu_is_ixp46x() && irq
>= 32)
173 *IXP4XX_ICMR2
&= ~(1 << (irq
- 32));
175 *IXP4XX_ICMR
&= ~(1 << irq
);
178 static void ixp4xx_irq_ack(unsigned int irq
)
180 int line
= (irq
< 32) ? irq2gpio
[irq
] : -1;
183 *IXP4XX_GPIO_GPISR
= (1 << line
);
187 * Level triggered interrupts on GPIO lines can only be cleared when the
188 * interrupt condition disappears.
190 static void ixp4xx_irq_unmask(unsigned int irq
)
192 if (!(ixp4xx_irq_edge
& (1 << irq
)))
195 if (cpu_is_ixp46x() && irq
>= 32)
196 *IXP4XX_ICMR2
|= (1 << (irq
- 32));
198 *IXP4XX_ICMR
|= (1 << irq
);
201 static struct irq_chip ixp4xx_irq_chip
= {
203 .ack
= ixp4xx_irq_ack
,
204 .mask
= ixp4xx_irq_mask
,
205 .unmask
= ixp4xx_irq_unmask
,
206 .set_type
= ixp4xx_set_irq_type
,
209 void __init
ixp4xx_init_irq(void)
213 /* Route all sources to IRQ instead of FIQ */
216 /* Disable all interrupt */
219 if (cpu_is_ixp46x()) {
220 /* Route upper 32 sources to IRQ instead of FIQ */
221 *IXP4XX_ICLR2
= 0x00;
223 /* Disable upper 32 interrupts */
224 *IXP4XX_ICMR2
= 0x00;
227 /* Default to all level triggered */
228 for(i
= 0; i
< NR_IRQS
; i
++) {
229 set_irq_chip(i
, &ixp4xx_irq_chip
);
230 set_irq_handler(i
, handle_level_irq
);
231 set_irq_flags(i
, IRQF_VALID
);
236 /*************************************************************************
238 * We use OS timer1 on the CPU for the timer tick and the timestamp
239 * counter as a source of real clock ticks to account for missed jiffies.
240 *************************************************************************/
242 static unsigned volatile last_jiffy_time
;
244 #define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
246 static irqreturn_t
ixp4xx_timer_interrupt(int irq
, void *dev_id
)
248 write_seqlock(&xtime_lock
);
250 /* Clear Pending Interrupt by writing '1' to it */
251 *IXP4XX_OSST
= IXP4XX_OSST_TIMER_1_PEND
;
254 * Catch up with the real idea of time
256 while ((signed long)(*IXP4XX_OSTS
- last_jiffy_time
) >= LATCH
) {
258 last_jiffy_time
+= LATCH
;
261 write_sequnlock(&xtime_lock
);
266 static struct irqaction ixp4xx_timer_irq
= {
267 .name
= "IXP4xx Timer Tick",
268 .flags
= IRQF_DISABLED
| IRQF_TIMER
,
269 .handler
= ixp4xx_timer_interrupt
,
272 static void __init
ixp4xx_timer_init(void)
274 /* Clear Pending Interrupt by writing '1' to it */
275 *IXP4XX_OSST
= IXP4XX_OSST_TIMER_1_PEND
;
277 /* Setup the Timer counter value */
278 *IXP4XX_OSRT1
= (LATCH
& ~IXP4XX_OST_RELOAD_MASK
) | IXP4XX_OST_ENABLE
;
280 /* Reset time-stamp counter */
284 /* Connect the interrupt handler and enable the interrupt */
285 setup_irq(IRQ_IXP4XX_TIMER1
, &ixp4xx_timer_irq
);
287 ixp4xx_clocksource_init();
290 struct sys_timer ixp4xx_timer
= {
291 .init
= ixp4xx_timer_init
,
294 static struct pxa2xx_udc_mach_info ixp4xx_udc_info
;
296 void __init
ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info
*info
)
298 memcpy(&ixp4xx_udc_info
, info
, sizeof *info
);
301 static struct resource ixp4xx_udc_resources
[] = {
305 .flags
= IORESOURCE_MEM
,
308 .start
= IRQ_IXP4XX_USB
,
309 .end
= IRQ_IXP4XX_USB
,
310 .flags
= IORESOURCE_IRQ
,
315 * USB device controller. The IXP4xx uses the same controller as PXA2XX,
316 * so we just use the same device.
318 static struct platform_device ixp4xx_udc_device
= {
319 .name
= "pxa2xx-udc",
322 .resource
= ixp4xx_udc_resources
,
324 .platform_data
= &ixp4xx_udc_info
,
328 static struct platform_device
*ixp4xx_devices
[] __initdata
= {
332 static struct resource ixp46x_i2c_resources
[] = {
336 .flags
= IORESOURCE_MEM
,
339 .start
= IRQ_IXP4XX_I2C
,
340 .end
= IRQ_IXP4XX_I2C
,
341 .flags
= IORESOURCE_IRQ
346 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
347 * we just use the same device name.
349 static struct platform_device ixp46x_i2c_controller
= {
350 .name
= "IOP3xx-I2C",
353 .resource
= ixp46x_i2c_resources
356 static struct platform_device
*ixp46x_devices
[] __initdata
= {
357 &ixp46x_i2c_controller
360 unsigned long ixp4xx_exp_bus_size
;
361 EXPORT_SYMBOL(ixp4xx_exp_bus_size
);
363 void __init
ixp4xx_sys_init(void)
365 ixp4xx_exp_bus_size
= SZ_16M
;
367 platform_add_devices(ixp4xx_devices
, ARRAY_SIZE(ixp4xx_devices
));
369 if (cpu_is_ixp46x()) {
372 platform_add_devices(ixp46x_devices
,
373 ARRAY_SIZE(ixp46x_devices
));
375 for (region
= 0; region
< 7; region
++) {
376 if((*(IXP4XX_EXP_REG(0x4 * region
)) & 0x200)) {
377 ixp4xx_exp_bus_size
= SZ_32M
;
383 printk("IXP4xx: Using %luMiB expansion bus window size\n",
384 ixp4xx_exp_bus_size
>> 20);
387 cycle_t
ixp4xx_get_cycles(void)
392 static struct clocksource clocksource_ixp4xx
= {
395 .read
= ixp4xx_get_cycles
,
396 .mask
= CLOCKSOURCE_MASK(32),
401 unsigned long ixp4xx_timer_freq
= FREQ
;
402 static int __init
ixp4xx_clocksource_init(void)
404 clocksource_ixp4xx
.mult
=
405 clocksource_hz2mult(ixp4xx_timer_freq
,
406 clocksource_ixp4xx
.shift
);
407 clocksource_register(&clocksource_ixp4xx
);