arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/tty.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bitops.h>
  25 #include <linux/time.h>
  26 #include <linux/timex.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clockchips.h>
  29 #include <linux/io.h>
  30 #include <linux/export.h>
  31 #include <linux/gpio.h>
  32 #include <linux/cpu.h>
  33 #include <linux/sched_clock.h>
  34
  35 #include <mach/udc.h>
  36 #include <mach/hardware.h>
  37 #include <mach/io.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41 #include <asm/irq.h>
  42 #include <asm/system_misc.h>
  43
  44 #include <asm/mach/map.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/time.h>
  47
  48 static void __init ixp4xx_clocksource_init(void);
  49 static void __init ixp4xx_clockevent_init(void);
  50 static struct clock_event_device clockevent_ixp4xx;
  51
  52 /*************************************************************************
  53  * IXP4xx chipset I/O mapping
  54  *************************************************************************/
  55 static struct map_desc ixp4xx_io_desc[] __initdata = {
  56         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  57                 .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
  58                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  59                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  60                 .type           = MT_DEVICE
  61         }, {    /* Expansion Bus Config Registers */
  62                 .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
  63                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  64                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  65                 .type           = MT_DEVICE
  66         }, {    /* PCI Registers */
  67                 .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
  68                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  69                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  70                 .type           = MT_DEVICE
  71         }, {    /* Queue Manager */
  72                 .virtual        = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
  73                 .pfn            = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
  74                 .length         = IXP4XX_QMGR_REGION_SIZE,
  75                 .type           = MT_DEVICE
  76         },
  77 };
  78
  79 void __init ixp4xx_map_io(void)
  80 {
  81         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  82 }
  83
  84 /*
  85  * GPIO-functions
  86  */
  87 /*
  88  * The following converted to the real HW bits the gpio_line_config
  89  */
  90 /* GPIO pin types */
  91 #define IXP4XX_GPIO_OUT                 0x1
  92 #define IXP4XX_GPIO_IN                  0x2
  93
  94 /* GPIO signal types */
  95 #define IXP4XX_GPIO_LOW                 0
  96 #define IXP4XX_GPIO_HIGH                1
  97
  98 /* GPIO Clocks */
  99 #define IXP4XX_GPIO_CLK_0               14
 100 #define IXP4XX_GPIO_CLK_1               15
 101
 102 static void gpio_line_config(u8 line, u32 direction)
 103 {
 104         if (direction == IXP4XX_GPIO_IN)
 105                 *IXP4XX_GPIO_GPOER |= (1 << line);
 106         else
 107                 *IXP4XX_GPIO_GPOER &= ~(1 << line);
 108 }
 109
 110 static void gpio_line_get(u8 line, int *value)
 111 {
 112         *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
 113 }
 114
 115 static void gpio_line_set(u8 line, int value)
 116 {
 117         if (value == IXP4XX_GPIO_HIGH)
 118             *IXP4XX_GPIO_GPOUTR |= (1 << line);
 119         else if (value == IXP4XX_GPIO_LOW)
 120             *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
 121 }
 122
 123 /*************************************************************************
 124  * IXP4xx chipset IRQ handling
 125  *
 126  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
 127  *       (be it PCI or something else) configures that GPIO line
 128  *       as an IRQ.
 129  **************************************************************************/
 130 enum ixp4xx_irq_type {
 131         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
 132 };
 133
 134 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
 135 static unsigned long long ixp4xx_irq_edge = 0;
 136
 137 /*
 138  * IRQ -> GPIO mapping table
 139  */
 140 static signed char irq2gpio[32] = {
 141         -1, -1, -1, -1, -1, -1,  0,  1,
 142         -1, -1, -1, -1, -1, -1, -1, -1,
 143         -1, -1, -1,  2,  3,  4,  5,  6,
 144          7,  8,  9, 10, 11, 12, -1, -1,
 145 };
 146
 147 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 148 {
 149         int irq;
 150
 151         for (irq = 0; irq < 32; irq++) {
 152                 if (irq2gpio[irq] == gpio)
 153                         return irq;
 154         }
 155         return -EINVAL;
 156 }
 157
 158 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
 159 {
 160         int line = irq2gpio[d->irq];
 161         u32 int_style;
 162         enum ixp4xx_irq_type irq_type;
 163         volatile u32 *int_reg;
 164
 165         /*
 166          * Only for GPIO IRQs
 167          */
 168         if (line < 0)
 169                 return -EINVAL;
 170
 171         switch (type){
 172         case IRQ_TYPE_EDGE_BOTH:
 173                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 174                 irq_type = IXP4XX_IRQ_EDGE;
 175                 break;
 176         case IRQ_TYPE_EDGE_RISING:
 177                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 178                 irq_type = IXP4XX_IRQ_EDGE;
 179                 break;
 180         case IRQ_TYPE_EDGE_FALLING:
 181                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 182                 irq_type = IXP4XX_IRQ_EDGE;
 183                 break;
 184         case IRQ_TYPE_LEVEL_HIGH:
 185                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 186                 irq_type = IXP4XX_IRQ_LEVEL;
 187                 break;
 188         case IRQ_TYPE_LEVEL_LOW:
 189                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 190                 irq_type = IXP4XX_IRQ_LEVEL;
 191                 break;
 192         default:
 193                 return -EINVAL;
 194         }
 195
 196         if (irq_type == IXP4XX_IRQ_EDGE)
 197                 ixp4xx_irq_edge |= (1 << d->irq);
 198         else
 199                 ixp4xx_irq_edge &= ~(1 << d->irq);
 200
 201         if (line >= 8) {        /* pins 8-15 */
 202                 line -= 8;
 203                 int_reg = IXP4XX_GPIO_GPIT2R;
 204         } else {                /* pins 0-7 */
 205                 int_reg = IXP4XX_GPIO_GPIT1R;
 206         }
 207
 208         /* Clear the style for the appropriate pin */
 209         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 210                         (line * IXP4XX_GPIO_STYLE_SIZE));
 211
 212         *IXP4XX_GPIO_GPISR = (1 << line);
 213
 214         /* Set the new style */
 215         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 216
 217         /* Configure the line as an input */
 218         gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
 219
 220         return 0;
 221 }
 222
 223 static void ixp4xx_irq_mask(struct irq_data *d)
 224 {
 225         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 226                 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
 227         else
 228                 *IXP4XX_ICMR &= ~(1 << d->irq);
 229 }
 230
 231 static void ixp4xx_irq_ack(struct irq_data *d)
 232 {
 233         int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
 234
 235         if (line >= 0)
 236                 *IXP4XX_GPIO_GPISR = (1 << line);
 237 }
 238
 239 /*
 240  * Level triggered interrupts on GPIO lines can only be cleared when the
 241  * interrupt condition disappears.
 242  */
 243 static void ixp4xx_irq_unmask(struct irq_data *d)
 244 {
 245         if (!(ixp4xx_irq_edge & (1 << d->irq)))
 246                 ixp4xx_irq_ack(d);
 247
 248         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 249                 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
 250         else
 251                 *IXP4XX_ICMR |= (1 << d->irq);
 252 }
 253
 254 static struct irq_chip ixp4xx_irq_chip = {
 255         .name           = "IXP4xx",
 256         .irq_ack        = ixp4xx_irq_ack,
 257         .irq_mask       = ixp4xx_irq_mask,
 258         .irq_unmask     = ixp4xx_irq_unmask,
 259         .irq_set_type   = ixp4xx_set_irq_type,
 260 };
 261
 262 void __init ixp4xx_init_irq(void)
 263 {
 264         int i = 0;
 265
 266         /*
 267          * ixp4xx does not implement the XScale PWRMODE register
 268          * so it must not call cpu_do_idle().
 269          */
 270         cpu_idle_poll_ctrl(true);
 271
 272         /* Route all sources to IRQ instead of FIQ */
 273         *IXP4XX_ICLR = 0x0;
 274
 275         /* Disable all interrupt */
 276         *IXP4XX_ICMR = 0x0;
 277
 278         if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
 279                 /* Route upper 32 sources to IRQ instead of FIQ */
 280                 *IXP4XX_ICLR2 = 0x00;
 281
 282                 /* Disable upper 32 interrupts */
 283                 *IXP4XX_ICMR2 = 0x00;
 284         }
 285
 286         /* Default to all level triggered */
 287         for(i = 0; i < NR_IRQS; i++) {
 288                 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
 289                                          handle_level_irq);
 290                 set_irq_flags(i, IRQF_VALID);
 291         }
 292 }
 293
 294
 295 /*************************************************************************
 296  * IXP4xx timer tick
 297  * We use OS timer1 on the CPU for the timer tick and the timestamp
 298  * counter as a source of real clock ticks to account for missed jiffies.
 299  *************************************************************************/
 300
 301 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 302 {
 303         struct clock_event_device *evt = dev_id;
 304
 305         /* Clear Pending Interrupt by writing '1' to it */
 306         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 307
 308         evt->event_handler(evt);
 309
 310         return IRQ_HANDLED;
 311 }
 312
 313 static struct irqaction ixp4xx_timer_irq = {
 314         .name           = "timer1",
 315         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 316         .handler        = ixp4xx_timer_interrupt,
 317         .dev_id         = &clockevent_ixp4xx,
 318 };
 319
 320 void __init ixp4xx_timer_init(void)
 321 {
 322         /* Reset/disable counter */
 323         *IXP4XX_OSRT1 = 0;
 324
 325         /* Clear Pending Interrupt by writing '1' to it */
 326         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 327
 328         /* Reset time-stamp counter */
 329         *IXP4XX_OSTS = 0;
 330
 331         /* Connect the interrupt handler and enable the interrupt */
 332         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 333
 334         ixp4xx_clocksource_init();
 335         ixp4xx_clockevent_init();
 336 }
 337
 338 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 339
 340 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 341 {
 342         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 343 }
 344
 345 static struct resource ixp4xx_udc_resources[] = {
 346         [0] = {
 347                 .start  = 0xc800b000,
 348                 .end    = 0xc800bfff,
 349                 .flags  = IORESOURCE_MEM,
 350         },
 351         [1] = {
 352                 .start  = IRQ_IXP4XX_USB,
 353                 .end    = IRQ_IXP4XX_USB,
 354                 .flags  = IORESOURCE_IRQ,
 355         },
 356 };
 357
 358 /*
 359  * USB device controller. The IXP4xx uses the same controller as PXA25X,
 360  * so we just use the same device.
 361  */
 362 static struct platform_device ixp4xx_udc_device = {
 363         .name           = "pxa25x-udc",
 364         .id             = -1,
 365         .num_resources  = 2,
 366         .resource       = ixp4xx_udc_resources,
 367         .dev            = {
 368                 .platform_data = &ixp4xx_udc_info,
 369         },
 370 };
 371
 372 static struct platform_device *ixp4xx_devices[] __initdata = {
 373         &ixp4xx_udc_device,
 374 };
 375
 376 static struct resource ixp46x_i2c_resources[] = {
 377         [0] = {
 378                 .start  = 0xc8011000,
 379                 .end    = 0xc801101c,
 380                 .flags  = IORESOURCE_MEM,
 381         },
 382         [1] = {
 383                 .start  = IRQ_IXP4XX_I2C,
 384                 .end    = IRQ_IXP4XX_I2C,
 385                 .flags  = IORESOURCE_IRQ
 386         }
 387 };
 388
 389 /*
 390  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 391  * we just use the same device name.
 392  */
 393 static struct platform_device ixp46x_i2c_controller = {
 394         .name           = "IOP3xx-I2C",
 395         .id             = 0,
 396         .num_resources  = 2,
 397         .resource       = ixp46x_i2c_resources
 398 };
 399
 400 static struct platform_device *ixp46x_devices[] __initdata = {
 401         &ixp46x_i2c_controller
 402 };
 403
 404 unsigned long ixp4xx_exp_bus_size;
 405 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 406
 407 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 408 {
 409         gpio_line_config(gpio, IXP4XX_GPIO_IN);
 410
 411         return 0;
 412 }
 413
 414 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
 415                                         int level)
 416 {
 417         gpio_line_set(gpio, level);
 418         gpio_line_config(gpio, IXP4XX_GPIO_OUT);
 419
 420         return 0;
 421 }
 422
 423 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
 424 {
 425         int value;
 426
 427         gpio_line_get(gpio, &value);
 428
 429         return value;
 430 }
 431
 432 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
 433                                   int value)
 434 {
 435         gpio_line_set(gpio, value);
 436 }
 437
 438 static struct gpio_chip ixp4xx_gpio_chip = {
 439         .label                  = "IXP4XX_GPIO_CHIP",
 440         .direction_input        = ixp4xx_gpio_direction_input,
 441         .direction_output       = ixp4xx_gpio_direction_output,
 442         .get                    = ixp4xx_gpio_get_value,
 443         .set                    = ixp4xx_gpio_set_value,
 444         .to_irq                 = ixp4xx_gpio_to_irq,
 445         .base                   = 0,
 446         .ngpio                  = 16,
 447 };
 448
 449 void __init ixp4xx_sys_init(void)
 450 {
 451         ixp4xx_exp_bus_size = SZ_16M;
 452
 453         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 454
 455         gpiochip_add(&ixp4xx_gpio_chip);
 456
 457         if (cpu_is_ixp46x()) {
 458                 int region;
 459
 460                 platform_add_devices(ixp46x_devices,
 461                                 ARRAY_SIZE(ixp46x_devices));
 462
 463                 for (region = 0; region < 7; region++) {
 464                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 465                                 ixp4xx_exp_bus_size = SZ_32M;
 466                                 break;
 467                         }
 468                 }
 469         }
 470
 471         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 472                         ixp4xx_exp_bus_size >> 20);
 473 }
 474
 475 /*
 476  * sched_clock()
 477  */
 478 static u32 notrace ixp4xx_read_sched_clock(void)
 479 {
 480         return *IXP4XX_OSTS;
 481 }
 482
 483 /*
 484  * clocksource
 485  */
 486
 487 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
 488 {
 489         return *IXP4XX_OSTS;
 490 }
 491
 492 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 493 EXPORT_SYMBOL(ixp4xx_timer_freq);
 494 static void __init ixp4xx_clocksource_init(void)
 495 {
 496         setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
 497
 498         clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
 499                         ixp4xx_clocksource_read);
 500 }
 501
 502 /*
 503  * clockevents
 504  */
 505 static int ixp4xx_set_next_event(unsigned long evt,
 506                                  struct clock_event_device *unused)
 507 {
 508         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 509
 510         *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
 511
 512         return 0;
 513 }
 514
 515 static void ixp4xx_set_mode(enum clock_event_mode mode,
 516                             struct clock_event_device *evt)
 517 {
 518         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 519         unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
 520
 521         switch (mode) {
 522         case CLOCK_EVT_MODE_PERIODIC:
 523                 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
 524                 opts = IXP4XX_OST_ENABLE;
 525                 break;
 526         case CLOCK_EVT_MODE_ONESHOT:
 527                 /* period set by 'set next_event' */
 528                 osrt = 0;
 529                 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
 530                 break;
 531         case CLOCK_EVT_MODE_SHUTDOWN:
 532                 opts &= ~IXP4XX_OST_ENABLE;
 533                 break;
 534         case CLOCK_EVT_MODE_RESUME:
 535                 opts |= IXP4XX_OST_ENABLE;
 536                 break;
 537         case CLOCK_EVT_MODE_UNUSED:
 538         default:
 539                 osrt = opts = 0;
 540                 break;
 541         }
 542
 543         *IXP4XX_OSRT1 = osrt | opts;
 544 }
 545
 546 static struct clock_event_device clockevent_ixp4xx = {
 547         .name           = "ixp4xx timer1",
 548         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 549         .rating         = 200,
 550         .set_mode       = ixp4xx_set_mode,
 551         .set_next_event = ixp4xx_set_next_event,
 552 };
 553
 554 static void __init ixp4xx_clockevent_init(void)
 555 {
 556         clockevent_ixp4xx.cpumask = cpumask_of(0);
 557         clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
 558                                         0xf, 0xfffffffe);
 559 }
 560
 561 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 562 {
 563         if ( 1 && mode == REBOOT_SOFT) {
 564                 /* Jump into ROM at address 0 */
 565                 soft_restart(0);
 566         } else {
 567                 /* Use on-chip reset capability */
 568
 569                 /* set the "key" register to enable access to
 570                  * "timer" and "enable" registers
 571                  */
 572                 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
 573
 574                 /* write 0 to the timer register for an immediate reset */
 575                 *IXP4XX_OSWT = 0;
 576
 577                 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
 578         }
 579 }
 580
 581 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
 582 /*
 583  * In the case of using indirect PCI, we simply return the actual PCI
 584  * address and our read/write implementation use that to drive the
 585  * access registers. If something outside of PCI is ioremap'd, we
 586  * fallback to the default.
 587  */
 588
 589 static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
 590                                            unsigned int mtype, void *caller)
 591 {
 592         if (!is_pci_memory(addr))
 593                 return __arm_ioremap_caller(addr, size, mtype, caller);
 594
 595         return (void __iomem *)addr;
 596 }
 597
 598 static void ixp4xx_iounmap(void __iomem *addr)
 599 {
 600         if (!is_pci_memory((__force u32)addr))
 601                 __iounmap(addr);
 602 }
 603
 604 void __init ixp4xx_init_early(void)
 605 {
 606         arch_ioremap_caller = ixp4xx_ioremap_caller;
 607         arch_iounmap = ixp4xx_iounmap;
 608 }
 609 #else
 610 void __init ixp4xx_init_early(void) {}
 611 #endif