arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mm.h>
  19 #include <linux/init.h>
  20 #include <linux/serial.h>
  21 #include <linux/sched.h>
  22 #include <linux/tty.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/bitops.h>
  28 #include <linux/time.h>
  29 #include <linux/timex.h>
  30
  31 #include <asm/hardware.h>
  32 #include <asm/uaccess.h>
  33 #include <asm/io.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/page.h>
  36 #include <asm/irq.h>
  37
  38 #include <asm/mach/map.h>
  39 #include <asm/mach/irq.h>
  40 #include <asm/mach/time.h>
  41
  42 /*************************************************************************
  43  * IXP4xx chipset I/O mapping
  44  *************************************************************************/
  45 static struct map_desc ixp4xx_io_desc[] __initdata = {
  46         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  47                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  48                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  49                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  50                 .type           = MT_DEVICE
  51         }, {    /* Expansion Bus Config Registers */
  52                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  53                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  54                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  55                 .type           = MT_DEVICE
  56         }, {    /* PCI Registers */
  57                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  58                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  59                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  60                 .type           = MT_DEVICE
  61         },
  62 #ifdef CONFIG_DEBUG_LL
  63         {       /* Debug UART mapping */
  64                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  65                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  66                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  67                 .type           = MT_DEVICE
  68         }
  69 #endif
  70 };
  71
  72 void __init ixp4xx_map_io(void)
  73 {
  74         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  75 }
  76
  77
  78 /*************************************************************************
  79  * IXP4xx chipset IRQ handling
  80  *
  81  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  82  *       (be it PCI or something else) configures that GPIO line
  83  *       as an IRQ.
  84  **************************************************************************/
  85 enum ixp4xx_irq_type {
  86         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  87 };
  88
  89 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
  90
  91 /*
  92  * IRQ -> GPIO mapping table
  93  */
  94 static int irq2gpio[32] = {
  95         -1, -1, -1, -1, -1, -1,  0,  1,
  96         -1, -1, -1, -1, -1, -1, -1, -1,
  97         -1, -1, -1,  2,  3,  4,  5,  6,
  98          7,  8,  9, 10, 11, 12, -1, -1,
  99 };
 100
 101 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 102 {
 103         int line = irq2gpio[irq];
 104         u32 int_style;
 105         enum ixp4xx_irq_type irq_type;
 106         volatile u32 *int_reg;
 107
 108         /*
 109          * Only for GPIO IRQs
 110          */
 111         if (line < 0)
 112                 return -EINVAL;
 113
 114         if (type & IRQT_BOTHEDGE) {
 115                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 116                 irq_type = IXP4XX_IRQ_EDGE;
 117         } else  if (type & IRQT_RISING) {
 118                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 119                 irq_type = IXP4XX_IRQ_EDGE;
 120         } else if (type & IRQT_FALLING) {
 121                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 122                 irq_type = IXP4XX_IRQ_EDGE;
 123         } else if (type & IRQT_HIGH) {
 124                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 125                 irq_type = IXP4XX_IRQ_LEVEL;
 126         } else if (type & IRQT_LOW) {
 127                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 128                 irq_type = IXP4XX_IRQ_LEVEL;
 129         } else
 130                 return -EINVAL;
 131
 132         ixp4xx_config_irq(irq, irq_type);
 133
 134         if (line >= 8) {        /* pins 8-15 */
 135                 line -= 8;
 136                 int_reg = IXP4XX_GPIO_GPIT2R;
 137         } else {                /* pins 0-7 */
 138                 int_reg = IXP4XX_GPIO_GPIT1R;
 139         }
 140
 141         /* Clear the style for the appropriate pin */
 142         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 143                         (line * IXP4XX_GPIO_STYLE_SIZE));
 144
 145         /* Set the new style */
 146         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 147
 148         return 0;
 149 }
 150
 151 static void ixp4xx_irq_mask(unsigned int irq)
 152 {
 153         if (cpu_is_ixp46x() && irq >= 32)
 154                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 155         else
 156                 *IXP4XX_ICMR &= ~(1 << irq);
 157 }
 158
 159 static void ixp4xx_irq_unmask(unsigned int irq)
 160 {
 161         if (cpu_is_ixp46x() && irq >= 32)
 162                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 163         else
 164                 *IXP4XX_ICMR |= (1 << irq);
 165 }
 166
 167 static void ixp4xx_irq_ack(unsigned int irq)
 168 {
 169         int line = (irq < 32) ? irq2gpio[irq] : -1;
 170
 171         if (line >= 0)
 172                 gpio_line_isr_clear(line);
 173 }
 174
 175 /*
 176  * Level triggered interrupts on GPIO lines can only be cleared when the
 177  * interrupt condition disappears.
 178  */
 179 static void ixp4xx_irq_level_unmask(unsigned int irq)
 180 {
 181         ixp4xx_irq_ack(irq);
 182         ixp4xx_irq_unmask(irq);
 183 }
 184
 185 static struct irqchip ixp4xx_irq_level_chip = {
 186         .ack            = ixp4xx_irq_mask,
 187         .mask           = ixp4xx_irq_mask,
 188         .unmask         = ixp4xx_irq_level_unmask,
 189         .set_type       = ixp4xx_set_irq_type,
 190 };
 191
 192 static struct irqchip ixp4xx_irq_edge_chip = {
 193         .ack            = ixp4xx_irq_ack,
 194         .mask           = ixp4xx_irq_mask,
 195         .unmask         = ixp4xx_irq_unmask,
 196         .set_type       = ixp4xx_set_irq_type,
 197 };
 198
 199 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
 200 {
 201         switch (type) {
 202         case IXP4XX_IRQ_LEVEL:
 203                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
 204                 set_irq_handler(irq, do_level_IRQ);
 205                 break;
 206         case IXP4XX_IRQ_EDGE:
 207                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
 208                 set_irq_handler(irq, do_edge_IRQ);
 209                 break;
 210         }
 211         set_irq_flags(irq, IRQF_VALID);
 212 }
 213
 214 void __init ixp4xx_init_irq(void)
 215 {
 216         int i = 0;
 217
 218         /* Route all sources to IRQ instead of FIQ */
 219         *IXP4XX_ICLR = 0x0;
 220
 221         /* Disable all interrupt */
 222         *IXP4XX_ICMR = 0x0;
 223
 224         if (cpu_is_ixp46x()) {
 225                 /* Route upper 32 sources to IRQ instead of FIQ */
 226                 *IXP4XX_ICLR2 = 0x00;
 227
 228                 /* Disable upper 32 interrupts */
 229                 *IXP4XX_ICMR2 = 0x00;
 230         }
 231
 232         /* Default to all level triggered */
 233         for(i = 0; i < NR_IRQS; i++)
 234                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
 235 }
 236
 237
 238 /*************************************************************************
 239  * IXP4xx timer tick
 240  * We use OS timer1 on the CPU for the timer tick and the timestamp
 241  * counter as a source of real clock ticks to account for missed jiffies.
 242  *************************************************************************/
 243
 244 static unsigned volatile last_jiffy_time;
 245
 246 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 247
 248 /* IRQs are disabled before entering here from do_gettimeofday() */
 249 static unsigned long ixp4xx_gettimeoffset(void)
 250 {
 251         u32 elapsed;
 252
 253         elapsed = *IXP4XX_OSTS - last_jiffy_time;
 254
 255         return elapsed / CLOCK_TICKS_PER_USEC;
 256 }
 257
 258 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 259 {
 260         write_seqlock(&xtime_lock);
 261
 262         /* Clear Pending Interrupt by writing '1' to it */
 263         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 264
 265         /*
 266          * Catch up with the real idea of time
 267          */
 268         while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
 269                 timer_tick(regs);
 270                 last_jiffy_time += LATCH;
 271         }
 272
 273         write_sequnlock(&xtime_lock);
 274
 275         return IRQ_HANDLED;
 276 }
 277
 278 static struct irqaction ixp4xx_timer_irq = {
 279         .name           = "IXP4xx Timer Tick",
 280         .flags          = SA_INTERRUPT | SA_TIMER,
 281         .handler        = ixp4xx_timer_interrupt,
 282 };
 283
 284 static void __init ixp4xx_timer_init(void)
 285 {
 286         /* Clear Pending Interrupt by writing '1' to it */
 287         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 288
 289         /* Setup the Timer counter value */
 290         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
 291
 292         /* Reset time-stamp counter */
 293         *IXP4XX_OSTS = 0;
 294         last_jiffy_time = 0;
 295
 296         /* Connect the interrupt handler and enable the interrupt */
 297         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 298 }
 299
 300 struct sys_timer ixp4xx_timer = {
 301         .init           = ixp4xx_timer_init,
 302         .offset         = ixp4xx_gettimeoffset,
 303 };
 304
 305 static struct resource ixp46x_i2c_resources[] = {
 306         [0] = {
 307                 .start  = 0xc8011000,
 308                 .end    = 0xc801101c,
 309                 .flags  = IORESOURCE_MEM,
 310         },
 311         [1] = {
 312                 .start  = IRQ_IXP4XX_I2C,
 313                 .end    = IRQ_IXP4XX_I2C,
 314                 .flags  = IORESOURCE_IRQ
 315         }
 316 };
 317
 318 /*
 319  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 320  * we just use the same device name.
 321  */
 322 static struct platform_device ixp46x_i2c_controller = {
 323         .name           = "IOP3xx-I2C",
 324         .id             = 0,
 325         .num_resources  = 2,
 326         .resource       = ixp46x_i2c_resources
 327 };
 328
 329 static struct platform_device *ixp46x_devices[] __initdata = {
 330         &ixp46x_i2c_controller
 331 };
 332
 333 void __init ixp4xx_sys_init(void)
 334 {
 335         if (cpu_is_ixp46x()) {
 336                 platform_add_devices(ixp46x_devices,
 337                                 ARRAY_SIZE(ixp46x_devices));
 338         }
 339 }
 340