arch/arm/mach-kirkwood/include/mach/bridge-regs.h

   1 /*
   2  * arch/arm/mach-kirkwood/include/mach/bridge-regs.h
   3  *
   4  * Mbus-L to Mbus Bridge Registers
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #ifndef __ASM_ARCH_BRIDGE_REGS_H
  12 #define __ASM_ARCH_BRIDGE_REGS_H
  13
  14 #include <mach/kirkwood.h>
  15
  16 #define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
  17 #define CPU_CONFIG_ERROR_PROP   0x00000004
  18
  19 #define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
  20 #define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
  21 #define CPU_RESET               0x00000002
  22
  23 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
  24 #define SOFT_RESET_OUT_EN       0x00000004
  25
  26 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
  27 #define SOFT_RESET              0x00000001
  28
  29 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
  30
  31 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
  32
  33 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
  34 #define IRQ_CAUSE_LOW_OFF       0x0000
  35 #define IRQ_MASK_LOW_OFF        0x0004
  36 #define IRQ_CAUSE_HIGH_OFF      0x0010
  37 #define IRQ_MASK_HIGH_OFF       0x0014
  38
  39 #define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
  40 #define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
  41
  42 #define L2_CONFIG_REG           (BRIDGE_VIRT_BASE + 0x0128)
  43 #define L2_WRITETHROUGH         0x00000010
  44
  45 #define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE + 0x11c)
  46 #define CGC_BIT_GE0             (0)
  47 #define CGC_BIT_PEX0            (2)
  48 #define CGC_BIT_USB0            (3)
  49 #define CGC_BIT_SDIO            (4)
  50 #define CGC_BIT_TSU             (5)
  51 #define CGC_BIT_DUNIT           (6)
  52 #define CGC_BIT_RUNIT           (7)
  53 #define CGC_BIT_XOR0            (8)
  54 #define CGC_BIT_AUDIO           (9)
  55 #define CGC_BIT_SATA0           (14)
  56 #define CGC_BIT_SATA1           (15)
  57 #define CGC_BIT_XOR1            (16)
  58 #define CGC_BIT_CRYPTO          (17)
  59 #define CGC_BIT_PEX1            (18)
  60 #define CGC_BIT_GE1             (19)
  61 #define CGC_BIT_TDM             (20)
  62 #define CGC_GE0                 (1 << 0)
  63 #define CGC_PEX0                (1 << 2)
  64 #define CGC_USB0                (1 << 3)
  65 #define CGC_SDIO                (1 << 4)
  66 #define CGC_TSU                 (1 << 5)
  67 #define CGC_DUNIT               (1 << 6)
  68 #define CGC_RUNIT               (1 << 7)
  69 #define CGC_XOR0                (1 << 8)
  70 #define CGC_AUDIO               (1 << 9)
  71 #define CGC_POWERSAVE           (1 << 11)
  72 #define CGC_SATA0               (1 << 14)
  73 #define CGC_SATA1               (1 << 15)
  74 #define CGC_XOR1                (1 << 16)
  75 #define CGC_CRYPTO              (1 << 17)
  76 #define CGC_PEX1                (1 << 18)
  77 #define CGC_GE1                 (1 << 19)
  78 #define CGC_TDM                 (1 << 20)
  79 #define CGC_RESERVED            (0x6 << 21)
  80
  81 #define MEMORY_PM_CTRL          (BRIDGE_VIRT_BASE + 0x118)
  82
  83 #endif