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Merge branch 'next/devel-samsung-pd' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-lpc32xx / clock.c
1 /*
2 * arch/arm/mach-lpc32xx/clock.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * LPC32xx clock management driver overview
21 *
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
29 *
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
35 * disabled normally.
36 * 32KHz oscillator*
37 * / | \
38 * RTC* PLL397^ TOUCH
39 * /
40 * Main oscillator^ /
41 * | \ /
42 * | SYSCLK&
43 * | \
44 * | \
45 * USB_PLL HCLK_PLL&
46 * | | |
47 * USB host/device PCLK& |
48 * | |
49 * Peripherals
50 *
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
59 *
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
67 *
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
76 * to an external pin.
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
78 * this driver.
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/list.h>
87 #include <linux/errno.h>
88 #include <linux/device.h>
89 #include <linux/err.h>
90 #include <linux/clk.h>
91 #include <linux/amba/bus.h>
92 #include <linux/amba/clcd.h>
93 #include <linux/clkdev.h>
94
95 #include <mach/hardware.h>
96 #include <mach/platform.h>
97 #include "clock.h"
98 #include "common.h"
99
100 static struct clk clk_armpll;
101 static struct clk clk_usbpll;
102 static DEFINE_MUTEX(clkm_lock);
103
104 /*
105 * Post divider values for PLLs based on selected register value
106 */
107 static const u32 pll_postdivs[4] = {1, 2, 4, 8};
108
109 static unsigned long local_return_parent_rate(struct clk *clk)
110 {
111 /*
112 * If a clock has a rate of 0, then it inherits it's parent
113 * clock rate
114 */
115 while (clk->rate == 0)
116 clk = clk->parent;
117
118 return clk->rate;
119 }
120
121 /* 32KHz clock has a fixed rate and is not stoppable */
122 static struct clk osc_32KHz = {
123 .rate = LPC32XX_CLOCK_OSC_FREQ,
124 .get_rate = local_return_parent_rate,
125 };
126
127 static int local_pll397_enable(struct clk *clk, int enable)
128 {
129 u32 reg;
130 unsigned long timeout = 1 + msecs_to_jiffies(10);
131
132 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
133
134 if (enable == 0) {
135 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
136 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
137 } else {
138 /* Enable PLL397 */
139 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
140 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
141
142 /* Wait for PLL397 lock */
143 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
144 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
145 (timeout > jiffies))
146 cpu_relax();
147
148 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
149 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
150 return -ENODEV;
151 }
152
153 return 0;
154 }
155
156 static int local_oscmain_enable(struct clk *clk, int enable)
157 {
158 u32 reg;
159 unsigned long timeout = 1 + msecs_to_jiffies(10);
160
161 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
162
163 if (enable == 0) {
164 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
165 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
166 } else {
167 /* Enable main oscillator */
168 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
169 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
170
171 /* Wait for main oscillator to start */
172 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
173 LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
174 (timeout > jiffies))
175 cpu_relax();
176
177 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
178 LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
179 return -ENODEV;
180 }
181
182 return 0;
183 }
184
185 static struct clk osc_pll397 = {
186 .parent = &osc_32KHz,
187 .enable = local_pll397_enable,
188 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
189 .get_rate = local_return_parent_rate,
190 };
191
192 static struct clk osc_main = {
193 .enable = local_oscmain_enable,
194 .rate = LPC32XX_MAIN_OSC_FREQ,
195 .get_rate = local_return_parent_rate,
196 };
197
198 static struct clk clk_sys;
199
200 /*
201 * Convert a PLL register value to a PLL output frequency
202 */
203 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
204 {
205 struct clk_pll_setup pllcfg;
206
207 pllcfg.cco_bypass_b15 = 0;
208 pllcfg.direct_output_b14 = 0;
209 pllcfg.fdbk_div_ctrl_b13 = 0;
210 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
211 pllcfg.cco_bypass_b15 = 1;
212 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
213 pllcfg.direct_output_b14 = 1;
214 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
215 pllcfg.fdbk_div_ctrl_b13 = 1;
216 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
217 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
218 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
219
220 return clk_check_pll_setup(inputclk, &pllcfg);
221 }
222
223 /*
224 * Setup the HCLK PLL with a PLL structure
225 */
226 static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
227 {
228 u32 tv, tmp = 0;
229
230 if (PllSetup->analog_on != 0)
231 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
232 if (PllSetup->cco_bypass_b15 != 0)
233 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
234 if (PllSetup->direct_output_b14 != 0)
235 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
236 if (PllSetup->fdbk_div_ctrl_b13 != 0)
237 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
238
239 tv = ffs(PllSetup->pll_p) - 1;
240 if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
241 return 0;
242
243 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
244 tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
245 tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
246
247 return tmp;
248 }
249
250 /*
251 * Update the ARM core PLL frequency rate variable from the actual PLL setting
252 */
253 static void local_update_armpll_rate(void)
254 {
255 u32 clkin, pllreg;
256
257 clkin = clk_armpll.parent->rate;
258 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
259
260 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
261 }
262
263 /*
264 * Find a PLL configuration for the selected input frequency
265 */
266 static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
267 struct clk_pll_setup *pllsetup)
268 {
269 u32 ifreq, freqtol, m, n, p, fclkout;
270
271 /* Determine frequency tolerance limits */
272 freqtol = target_freq / 250;
273 ifreq = pllin_freq;
274
275 /* Is direct bypass mode possible? */
276 if (abs(pllin_freq - target_freq) <= freqtol) {
277 pllsetup->analog_on = 0;
278 pllsetup->cco_bypass_b15 = 1;
279 pllsetup->direct_output_b14 = 1;
280 pllsetup->fdbk_div_ctrl_b13 = 1;
281 pllsetup->pll_p = pll_postdivs[0];
282 pllsetup->pll_n = 1;
283 pllsetup->pll_m = 1;
284 return clk_check_pll_setup(ifreq, pllsetup);
285 } else if (target_freq <= ifreq) {
286 pllsetup->analog_on = 0;
287 pllsetup->cco_bypass_b15 = 1;
288 pllsetup->direct_output_b14 = 0;
289 pllsetup->fdbk_div_ctrl_b13 = 1;
290 pllsetup->pll_n = 1;
291 pllsetup->pll_m = 1;
292 for (p = 0; p <= 3; p++) {
293 pllsetup->pll_p = pll_postdivs[p];
294 fclkout = clk_check_pll_setup(ifreq, pllsetup);
295 if (abs(target_freq - fclkout) <= freqtol)
296 return fclkout;
297 }
298 }
299
300 /* Is direct mode possible? */
301 pllsetup->analog_on = 1;
302 pllsetup->cco_bypass_b15 = 0;
303 pllsetup->direct_output_b14 = 1;
304 pllsetup->fdbk_div_ctrl_b13 = 0;
305 pllsetup->pll_p = pll_postdivs[0];
306 for (m = 1; m <= 256; m++) {
307 for (n = 1; n <= 4; n++) {
308 /* Compute output frequency for this value */
309 pllsetup->pll_n = n;
310 pllsetup->pll_m = m;
311 fclkout = clk_check_pll_setup(ifreq,
312 pllsetup);
313 if (abs(target_freq - fclkout) <=
314 freqtol)
315 return fclkout;
316 }
317 }
318
319 /* Is integer mode possible? */
320 pllsetup->analog_on = 1;
321 pllsetup->cco_bypass_b15 = 0;
322 pllsetup->direct_output_b14 = 0;
323 pllsetup->fdbk_div_ctrl_b13 = 1;
324 for (m = 1; m <= 256; m++) {
325 for (n = 1; n <= 4; n++) {
326 for (p = 0; p < 4; p++) {
327 /* Compute output frequency */
328 pllsetup->pll_p = pll_postdivs[p];
329 pllsetup->pll_n = n;
330 pllsetup->pll_m = m;
331 fclkout = clk_check_pll_setup(
332 ifreq, pllsetup);
333 if (abs(target_freq - fclkout) <= freqtol)
334 return fclkout;
335 }
336 }
337 }
338
339 /* Try non-integer mode */
340 pllsetup->analog_on = 1;
341 pllsetup->cco_bypass_b15 = 0;
342 pllsetup->direct_output_b14 = 0;
343 pllsetup->fdbk_div_ctrl_b13 = 0;
344 for (m = 1; m <= 256; m++) {
345 for (n = 1; n <= 4; n++) {
346 for (p = 0; p < 4; p++) {
347 /* Compute output frequency */
348 pllsetup->pll_p = pll_postdivs[p];
349 pllsetup->pll_n = n;
350 pllsetup->pll_m = m;
351 fclkout = clk_check_pll_setup(
352 ifreq, pllsetup);
353 if (abs(target_freq - fclkout) <= freqtol)
354 return fclkout;
355 }
356 }
357 }
358
359 return 0;
360 }
361
362 static struct clk clk_armpll = {
363 .parent = &clk_sys,
364 .get_rate = local_return_parent_rate,
365 };
366
367 /*
368 * Setup the USB PLL with a PLL structure
369 */
370 static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
371 {
372 u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
373
374 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
375 reg |= tmp;
376 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
377
378 return clk_check_pll_setup(clk_usbpll.parent->rate,
379 pHCLKPllSetup);
380 }
381
382 static int local_usbpll_enable(struct clk *clk, int enable)
383 {
384 u32 reg;
385 int ret = -ENODEV;
386 unsigned long timeout = 1 + msecs_to_jiffies(10);
387
388 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
389
390 if (enable == 0) {
391 reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
392 LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
393 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
394 } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
395 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
396 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
397
398 /* Wait for PLL lock */
399 while ((timeout > jiffies) & (ret == -ENODEV)) {
400 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
401 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
402 ret = 0;
403 }
404
405 if (ret == 0) {
406 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
407 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
408 }
409 }
410
411 return ret;
412 }
413
414 static unsigned long local_usbpll_round_rate(struct clk *clk,
415 unsigned long rate)
416 {
417 u32 clkin, usbdiv;
418 struct clk_pll_setup pllsetup;
419
420 /*
421 * Unlike other clocks, this clock has a KHz input rate, so bump
422 * it up to work with the PLL function
423 */
424 rate = rate * 1000;
425
426 clkin = clk->parent->rate;
427 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
428 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
429 clkin = clkin / usbdiv;
430
431 /* Try to find a good rate setup */
432 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
433 return 0;
434
435 return clk_check_pll_setup(clkin, &pllsetup);
436 }
437
438 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
439 {
440 u32 clkin, reg, usbdiv;
441 struct clk_pll_setup pllsetup;
442
443 /*
444 * Unlike other clocks, this clock has a KHz input rate, so bump
445 * it up to work with the PLL function
446 */
447 rate = rate * 1000;
448
449 clkin = clk->get_rate(clk);
450 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
451 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
452 clkin = clkin / usbdiv;
453
454 /* Try to find a good rate setup */
455 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
456 return -EINVAL;
457
458 local_usbpll_enable(clk, 0);
459
460 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
461 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
462 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
463
464 pllsetup.analog_on = 1;
465 local_clk_usbpll_setup(&pllsetup);
466
467 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
468
469 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
470 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
471 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
472
473 return 0;
474 }
475
476 static struct clk clk_usbpll = {
477 .parent = &osc_main,
478 .set_rate = local_usbpll_set_rate,
479 .enable = local_usbpll_enable,
480 .rate = 48000, /* In KHz */
481 .get_rate = local_return_parent_rate,
482 .round_rate = local_usbpll_round_rate,
483 };
484
485 static u32 clk_get_hclk_div(void)
486 {
487 static const u32 hclkdivs[4] = {1, 2, 4, 4};
488 return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
489 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
490 }
491
492 static struct clk clk_hclk = {
493 .parent = &clk_armpll,
494 .get_rate = local_return_parent_rate,
495 };
496
497 static struct clk clk_pclk = {
498 .parent = &clk_armpll,
499 .get_rate = local_return_parent_rate,
500 };
501
502 static int local_onoff_enable(struct clk *clk, int enable)
503 {
504 u32 tmp;
505
506 tmp = __raw_readl(clk->enable_reg);
507
508 if (enable == 0)
509 tmp &= ~clk->enable_mask;
510 else
511 tmp |= clk->enable_mask;
512
513 __raw_writel(tmp, clk->enable_reg);
514
515 return 0;
516 }
517
518 /* Peripheral clock sources */
519 static struct clk clk_timer0 = {
520 .parent = &clk_pclk,
521 .enable = local_onoff_enable,
522 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
523 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
524 .get_rate = local_return_parent_rate,
525 };
526 static struct clk clk_timer1 = {
527 .parent = &clk_pclk,
528 .enable = local_onoff_enable,
529 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
530 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
531 .get_rate = local_return_parent_rate,
532 };
533 static struct clk clk_timer2 = {
534 .parent = &clk_pclk,
535 .enable = local_onoff_enable,
536 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
537 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
538 .get_rate = local_return_parent_rate,
539 };
540 static struct clk clk_timer3 = {
541 .parent = &clk_pclk,
542 .enable = local_onoff_enable,
543 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
544 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
545 .get_rate = local_return_parent_rate,
546 };
547 static struct clk clk_wdt = {
548 .parent = &clk_pclk,
549 .enable = local_onoff_enable,
550 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
551 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
552 .get_rate = local_return_parent_rate,
553 };
554 static struct clk clk_vfp9 = {
555 .parent = &clk_pclk,
556 .enable = local_onoff_enable,
557 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
558 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
559 .get_rate = local_return_parent_rate,
560 };
561 static struct clk clk_dma = {
562 .parent = &clk_hclk,
563 .enable = local_onoff_enable,
564 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
565 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
566 .get_rate = local_return_parent_rate,
567 };
568
569 static struct clk clk_uart3 = {
570 .parent = &clk_pclk,
571 .enable = local_onoff_enable,
572 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
573 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
574 .get_rate = local_return_parent_rate,
575 };
576
577 static struct clk clk_uart4 = {
578 .parent = &clk_pclk,
579 .enable = local_onoff_enable,
580 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
581 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
582 .get_rate = local_return_parent_rate,
583 };
584
585 static struct clk clk_uart5 = {
586 .parent = &clk_pclk,
587 .enable = local_onoff_enable,
588 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
589 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
590 .get_rate = local_return_parent_rate,
591 };
592
593 static struct clk clk_uart6 = {
594 .parent = &clk_pclk,
595 .enable = local_onoff_enable,
596 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
597 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
598 .get_rate = local_return_parent_rate,
599 };
600
601 static struct clk clk_i2c0 = {
602 .parent = &clk_hclk,
603 .enable = local_onoff_enable,
604 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
605 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
606 .get_rate = local_return_parent_rate,
607 };
608
609 static struct clk clk_i2c1 = {
610 .parent = &clk_hclk,
611 .enable = local_onoff_enable,
612 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
613 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
614 .get_rate = local_return_parent_rate,
615 };
616
617 static struct clk clk_i2c2 = {
618 .parent = &clk_pclk,
619 .enable = local_onoff_enable,
620 .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
621 .enable_mask = 0x4,
622 .get_rate = local_return_parent_rate,
623 };
624
625 static struct clk clk_ssp0 = {
626 .parent = &clk_hclk,
627 .enable = local_onoff_enable,
628 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
629 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
630 .get_rate = local_return_parent_rate,
631 };
632
633 static struct clk clk_ssp1 = {
634 .parent = &clk_hclk,
635 .enable = local_onoff_enable,
636 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
637 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
638 .get_rate = local_return_parent_rate,
639 };
640
641 static struct clk clk_kscan = {
642 .parent = &osc_32KHz,
643 .enable = local_onoff_enable,
644 .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
645 .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
646 .get_rate = local_return_parent_rate,
647 };
648
649 static struct clk clk_nand = {
650 .parent = &clk_hclk,
651 .enable = local_onoff_enable,
652 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
653 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
654 .get_rate = local_return_parent_rate,
655 };
656
657 static struct clk clk_i2s0 = {
658 .parent = &clk_hclk,
659 .enable = local_onoff_enable,
660 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
661 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
662 .get_rate = local_return_parent_rate,
663 };
664
665 static struct clk clk_i2s1 = {
666 .parent = &clk_hclk,
667 .enable = local_onoff_enable,
668 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
669 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
670 .get_rate = local_return_parent_rate,
671 };
672
673 static struct clk clk_net = {
674 .parent = &clk_hclk,
675 .enable = local_onoff_enable,
676 .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
677 .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
678 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
679 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
680 .get_rate = local_return_parent_rate,
681 };
682
683 static struct clk clk_rtc = {
684 .parent = &osc_32KHz,
685 .rate = 1, /* 1 Hz */
686 .get_rate = local_return_parent_rate,
687 };
688
689 static struct clk clk_usbd = {
690 .parent = &clk_usbpll,
691 .enable = local_onoff_enable,
692 .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
693 .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
694 .get_rate = local_return_parent_rate,
695 };
696
697 static int tsc_onoff_enable(struct clk *clk, int enable)
698 {
699 u32 tmp;
700
701 /* Make sure 32KHz clock is the selected clock */
702 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
703 tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
704 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
705
706 if (enable == 0)
707 __raw_writel(0, clk->enable_reg);
708 else
709 __raw_writel(clk->enable_mask, clk->enable_reg);
710
711 return 0;
712 }
713
714 static struct clk clk_tsc = {
715 .parent = &osc_32KHz,
716 .enable = tsc_onoff_enable,
717 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
718 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
719 .get_rate = local_return_parent_rate,
720 };
721
722 static int adc_onoff_enable(struct clk *clk, int enable)
723 {
724 u32 tmp;
725 u32 divider;
726
727 /* Use PERIPH_CLOCK */
728 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
729 tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
730 /*
731 * Set clock divider so that we have equal to or less than
732 * 4.5MHz clock at ADC
733 */
734 divider = clk->get_rate(clk) / 4500000 + 1;
735 tmp |= divider;
736 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
737
738 /* synchronize rate of this clock w/ actual HW setting */
739 clk->rate = clk->get_rate(clk->parent) / divider;
740
741 if (enable == 0)
742 __raw_writel(0, clk->enable_reg);
743 else
744 __raw_writel(clk->enable_mask, clk->enable_reg);
745
746 return 0;
747 }
748
749 static struct clk clk_adc = {
750 .parent = &clk_pclk,
751 .enable = adc_onoff_enable,
752 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
753 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
754 .get_rate = local_return_parent_rate,
755 };
756
757 static int mmc_onoff_enable(struct clk *clk, int enable)
758 {
759 u32 tmp;
760
761 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
762 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
763
764 /* If rate is 0, disable clock */
765 if (enable != 0)
766 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
767
768 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
769
770 return 0;
771 }
772
773 static unsigned long mmc_get_rate(struct clk *clk)
774 {
775 u32 div, rate, oldclk;
776
777 /* The MMC clock must be on when accessing an MMC register */
778 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
779 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
780 LPC32XX_CLKPWR_MS_CTRL);
781 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
782 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
783
784 /* Get the parent clock rate */
785 rate = clk->parent->get_rate(clk->parent);
786
787 /* Get the MMC controller clock divider value */
788 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
789
790 if (!div)
791 div = 1;
792
793 return rate / div;
794 }
795
796 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
797 {
798 unsigned long div, prate;
799
800 /* Get the parent clock rate */
801 prate = clk->parent->get_rate(clk->parent);
802
803 if (rate >= prate)
804 return prate;
805
806 div = prate / rate;
807 if (div > 0xf)
808 div = 0xf;
809
810 return prate / div;
811 }
812
813 static int mmc_set_rate(struct clk *clk, unsigned long rate)
814 {
815 u32 oldclk, tmp;
816 unsigned long prate, div, crate = mmc_round_rate(clk, rate);
817
818 prate = clk->parent->get_rate(clk->parent);
819
820 div = prate / crate;
821
822 /* The MMC clock must be on when accessing an MMC register */
823 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
824 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
825 LPC32XX_CLKPWR_MS_CTRL);
826 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
827 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
828 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
829 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
830
831 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
832
833 return 0;
834 }
835
836 static struct clk clk_mmc = {
837 .parent = &clk_armpll,
838 .set_rate = mmc_set_rate,
839 .get_rate = mmc_get_rate,
840 .round_rate = mmc_round_rate,
841 .enable = mmc_onoff_enable,
842 .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
843 .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
844 };
845
846 static unsigned long clcd_get_rate(struct clk *clk)
847 {
848 u32 tmp, div, rate, oldclk;
849
850 /* The LCD clock must be on when accessing an LCD register */
851 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
852 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
853 LPC32XX_CLKPWR_LCDCLK_CTRL);
854 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
855 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
856
857 rate = clk->parent->get_rate(clk->parent);
858
859 /* Only supports internal clocking */
860 if (tmp & TIM2_BCD)
861 return rate;
862
863 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
864 tmp = rate / (2 + div);
865
866 return tmp;
867 }
868
869 static int clcd_set_rate(struct clk *clk, unsigned long rate)
870 {
871 u32 tmp, prate, div, oldclk;
872
873 /* The LCD clock must be on when accessing an LCD register */
874 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
875 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
876 LPC32XX_CLKPWR_LCDCLK_CTRL);
877
878 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
879 prate = clk->parent->get_rate(clk->parent);
880
881 if (rate < prate) {
882 /* Find closest divider */
883 div = prate / rate;
884 if (div >= 2) {
885 div -= 2;
886 tmp &= ~TIM2_BCD;
887 }
888
889 tmp &= ~(0xF800001F);
890 tmp |= (div & 0x1F);
891 tmp |= (((div >> 5) & 0x1F) << 27);
892 }
893
894 __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
895 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
896
897 return 0;
898 }
899
900 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
901 {
902 u32 prate, div;
903
904 prate = clk->parent->get_rate(clk->parent);
905
906 if (rate >= prate)
907 rate = prate;
908 else {
909 div = prate / rate;
910 if (div > 0x3ff)
911 div = 0x3ff;
912
913 rate = prate / div;
914 }
915
916 return rate;
917 }
918
919 static struct clk clk_lcd = {
920 .parent = &clk_hclk,
921 .set_rate = clcd_set_rate,
922 .get_rate = clcd_get_rate,
923 .round_rate = clcd_round_rate,
924 .enable = local_onoff_enable,
925 .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
926 .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
927 };
928
929 static inline void clk_lock(void)
930 {
931 mutex_lock(&clkm_lock);
932 }
933
934 static inline void clk_unlock(void)
935 {
936 mutex_unlock(&clkm_lock);
937 }
938
939 static void local_clk_disable(struct clk *clk)
940 {
941 WARN_ON(clk->usecount == 0);
942
943 /* Don't attempt to disable clock if it has no users */
944 if (clk->usecount > 0) {
945 clk->usecount--;
946
947 /* Only disable clock when it has no more users */
948 if ((clk->usecount == 0) && (clk->enable))
949 clk->enable(clk, 0);
950
951 /* Check parent clocks, they may need to be disabled too */
952 if (clk->parent)
953 local_clk_disable(clk->parent);
954 }
955 }
956
957 static int local_clk_enable(struct clk *clk)
958 {
959 int ret = 0;
960
961 /* Enable parent clocks first and update use counts */
962 if (clk->parent)
963 ret = local_clk_enable(clk->parent);
964
965 if (!ret) {
966 /* Only enable clock if it's currently disabled */
967 if ((clk->usecount == 0) && (clk->enable))
968 ret = clk->enable(clk, 1);
969
970 if (!ret)
971 clk->usecount++;
972 else if (clk->parent)
973 local_clk_disable(clk->parent);
974 }
975
976 return ret;
977 }
978
979 /*
980 * clk_enable - inform the system when the clock source should be running.
981 */
982 int clk_enable(struct clk *clk)
983 {
984 int ret;
985
986 clk_lock();
987 ret = local_clk_enable(clk);
988 clk_unlock();
989
990 return ret;
991 }
992 EXPORT_SYMBOL(clk_enable);
993
994 /*
995 * clk_disable - inform the system when the clock source is no longer required
996 */
997 void clk_disable(struct clk *clk)
998 {
999 clk_lock();
1000 local_clk_disable(clk);
1001 clk_unlock();
1002 }
1003 EXPORT_SYMBOL(clk_disable);
1004
1005 /*
1006 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1007 */
1008 unsigned long clk_get_rate(struct clk *clk)
1009 {
1010 unsigned long rate;
1011
1012 clk_lock();
1013 rate = clk->get_rate(clk);
1014 clk_unlock();
1015
1016 return rate;
1017 }
1018 EXPORT_SYMBOL(clk_get_rate);
1019
1020 /*
1021 * clk_set_rate - set the clock rate for a clock source
1022 */
1023 int clk_set_rate(struct clk *clk, unsigned long rate)
1024 {
1025 int ret = -EINVAL;
1026
1027 /*
1028 * Most system clocks can only be enabled or disabled, with
1029 * the actual rate set as part of the peripheral dividers
1030 * instead of high level clock control
1031 */
1032 if (clk->set_rate) {
1033 clk_lock();
1034 ret = clk->set_rate(clk, rate);
1035 clk_unlock();
1036 }
1037
1038 return ret;
1039 }
1040 EXPORT_SYMBOL(clk_set_rate);
1041
1042 /*
1043 * clk_round_rate - adjust a rate to the exact rate a clock can provide
1044 */
1045 long clk_round_rate(struct clk *clk, unsigned long rate)
1046 {
1047 clk_lock();
1048
1049 if (clk->round_rate)
1050 rate = clk->round_rate(clk, rate);
1051 else
1052 rate = clk->get_rate(clk);
1053
1054 clk_unlock();
1055
1056 return rate;
1057 }
1058 EXPORT_SYMBOL(clk_round_rate);
1059
1060 /*
1061 * clk_set_parent - set the parent clock source for this clock
1062 */
1063 int clk_set_parent(struct clk *clk, struct clk *parent)
1064 {
1065 /* Clock re-parenting is not supported */
1066 return -EINVAL;
1067 }
1068 EXPORT_SYMBOL(clk_set_parent);
1069
1070 /*
1071 * clk_get_parent - get the parent clock source for this clock
1072 */
1073 struct clk *clk_get_parent(struct clk *clk)
1074 {
1075 return clk->parent;
1076 }
1077 EXPORT_SYMBOL(clk_get_parent);
1078
1079 #define _REGISTER_CLOCK(d, n, c) \
1080 { \
1081 .dev_id = (d), \
1082 .con_id = (n), \
1083 .clk = &(c), \
1084 },
1085
1086 static struct clk_lookup lookups[] = {
1087 _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
1088 _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
1089 _REGISTER_CLOCK(NULL, "osc_main", osc_main)
1090 _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
1091 _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
1092 _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
1093 _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
1094 _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
1095 _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
1096 _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
1097 _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
1098 _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
1099 _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
1100 _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
1101 _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
1102 _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
1103 _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
1104 _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
1105 _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
1106 _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
1107 _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
1108 _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
1109 _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
1110 _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
1111 _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
1112 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1113 _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
1114 _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
1115 _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
1116 _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
1117 _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
1118 _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
1119 _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
1120 _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
1121 _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
1122 };
1123
1124 static int __init clk_init(void)
1125 {
1126 int i;
1127
1128 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1129 clkdev_add(&lookups[i]);
1130
1131 /*
1132 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1133 * parent clock used for the ARM PLL and is used to derive
1134 * the many system clock rates in the device.
1135 */
1136 if (clk_is_sysclk_mainosc() != 0)
1137 clk_sys.parent = &osc_main;
1138 else
1139 clk_sys.parent = &osc_pll397;
1140
1141 clk_sys.rate = clk_sys.parent->rate;
1142
1143 /* Compute the current ARM PLL and USB PLL frequencies */
1144 local_update_armpll_rate();
1145
1146 /* Compute HCLK and PCLK bus rates */
1147 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1148 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1149
1150 /*
1151 * Enable system clocks - this step is somewhat formal, as the
1152 * clocks are already running, but it does get the clock data
1153 * inline with the actual system state. Never disable these
1154 * clocks as they will only stop if the system is going to sleep.
1155 * In that case, the chip/system power management functions will
1156 * handle clock gating.
1157 */
1158 if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1159 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1160
1161 /*
1162 * Timers 0 and 1 were enabled and are being used by the high
1163 * resolution tick function prior to this driver being initialized.
1164 * Tag them now as used.
1165 */
1166 if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1167 printk(KERN_ERR "Error enabling timer tick clocks\n");
1168
1169 return 0;
1170 }
1171 core_initcall(clk_init);
1172
Linux kernel - Deliverables
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