arch/arm/mach-lpc32xx/timer.c

   1 /*
   2  * arch/arm/mach-lpc32xx/timer.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2009 - 2010 NXP Semiconductors
   7  * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
   8  *                    Ed Schouten <e.schouten@fontys.nl>
   9  *                    Laurens Timmermans <l.timmermans@fontys.nl>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/time.h>
  25 #include <linux/err.h>
  26 #include <linux/clockchips.h>
  27
  28 #include <asm/mach/time.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/platform.h>
  32 #include "common.h"
  33
  34 static int lpc32xx_clkevt_next_event(unsigned long delta,
  35     struct clock_event_device *dev)
  36 {
  37         __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
  38                 LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  39         __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
  40         __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
  41                 LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  42
  43         return 0;
  44 }
  45
  46 static int lpc32xx_shutdown(struct clock_event_device *evt)
  47 {
  48         /*
  49          * Disable the timer. When using oneshot, we must also
  50          * disable the timer to wait for the first call to
  51          * set_next_event().
  52          */
  53         __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  54         return 0;
  55 }
  56
  57 static struct clock_event_device lpc32xx_clkevt = {
  58         .name                   = "lpc32xx_clkevt",
  59         .features               = CLOCK_EVT_FEAT_ONESHOT,
  60         .rating                 = 300,
  61         .set_next_event         = lpc32xx_clkevt_next_event,
  62         .set_state_shutdown     = lpc32xx_shutdown,
  63         .set_state_oneshot      = lpc32xx_shutdown,
  64 };
  65
  66 static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
  67 {
  68         struct clock_event_device *evt = &lpc32xx_clkevt;
  69
  70         /* Clear match */
  71         __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
  72                 LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
  73
  74         evt->event_handler(evt);
  75
  76         return IRQ_HANDLED;
  77 }
  78
  79 static struct irqaction lpc32xx_timer_irq = {
  80         .name           = "LPC32XX Timer Tick",
  81         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
  82         .handler        = lpc32xx_timer_interrupt,
  83 };
  84
  85 /*
  86  * The clock management driver isn't initialized at this point, so the
  87  * clocks need to be enabled here manually and then tagged as used in
  88  * the clock driver initialization
  89  */
  90 void __init lpc32xx_timer_init(void)
  91 {
  92         u32 clkrate, pllreg;
  93
  94         /* Enable timer clock */
  95         __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
  96                 LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
  97                 LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
  98
  99         /*
 100          * The clock driver isn't initialized at this point. So determine if
 101          * the SYSCLK is driven from the PLL397 or main oscillator and then use
 102          * it to compute the PLL frequency and the PCLK divider to get the base
 103          * timer rates. This rate is needed to compute the tick rate.
 104          */
 105         if (clk_is_sysclk_mainosc() != 0)
 106                 clkrate = LPC32XX_MAIN_OSC_FREQ;
 107         else
 108                 clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
 109
 110         /* Get ARM HCLKPLL register and convert it into a frequency */
 111         pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
 112         clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
 113
 114         /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
 115         clkrate = clkrate / clk_get_pclk_div();
 116
 117         /* Initial timer setup */
 118         __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 119         __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
 120                 LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 121         __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
 122         __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
 123                 LPC32XX_TIMER_CNTR_MCR_STOP(0) |
 124                 LPC32XX_TIMER_CNTR_MCR_RESET(0),
 125                 LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 126
 127         /* Setup tick interrupt */
 128         setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
 129
 130         /* Setup the clockevent structure. */
 131         lpc32xx_clkevt.cpumask = cpumask_of(0);
 132         clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
 133
 134         /* Use timer1 as clock source. */
 135         __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
 136                 LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 137         __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
 138         __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
 139         __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
 140                 LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 141
 142         clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
 143                 "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
 144 }