arch/arm/mach-mmp/irq-mmp2.c

   1 /*
   2  *  linux/arch/arm/mach-mmp/irq-mmp2.c
   3  *
   4  *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
   5  *
   6  *  Author:     Haojian Zhuang <haojian.zhuang@marvell.com>
   7  *  Copyright:  Marvell International Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/irq.h>
  16 #include <linux/io.h>
  17
  18 #include <mach/regs-icu.h>
  19
  20 #include "common.h"
  21
  22 static void icu_mask_irq(unsigned int irq)
  23 {
  24         uint32_t r = __raw_readl(ICU_INT_CONF(irq));
  25
  26         r &= ~ICU_INT_ROUTE_PJ4_IRQ;
  27         __raw_writel(r, ICU_INT_CONF(irq));
  28 }
  29
  30 static void icu_unmask_irq(unsigned int irq)
  31 {
  32         uint32_t r = __raw_readl(ICU_INT_CONF(irq));
  33
  34         r |= ICU_INT_ROUTE_PJ4_IRQ;
  35         __raw_writel(r, ICU_INT_CONF(irq));
  36 }
  37
  38 static struct irq_chip icu_irq_chip = {
  39         .name           = "icu_irq",
  40         .mask           = icu_mask_irq,
  41         .mask_ack       = icu_mask_irq,
  42         .unmask         = icu_unmask_irq,
  43 };
  44
  45 #define SECOND_IRQ_MASK(_name_, irq_base, prefix)                       \
  46 static void _name_##_mask_irq(unsigned int irq)                         \
  47 {                                                                       \
  48         uint32_t r;                                                     \
  49         r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base));       \
  50         __raw_writel(r, prefix##_MASK);                                 \
  51 }
  52
  53 #define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                     \
  54 static void _name_##_unmask_irq(unsigned int irq)                       \
  55 {                                                                       \
  56         uint32_t r;                                                     \
  57         r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base));      \
  58         __raw_writel(r, prefix##_MASK);                                 \
  59 }
  60
  61 #define SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                      \
  62 static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
  63 {                                                                       \
  64         unsigned long status, mask, n;                                  \
  65         mask = __raw_readl(prefix##_MASK);                              \
  66         while (1) {                                                     \
  67                 status = __raw_readl(prefix##_STATUS) & ~mask;          \
  68                 if (status == 0)                                        \
  69                         break;                                          \
  70                 n = find_first_bit(&status, BITS_PER_LONG);             \
  71                 while (n < BITS_PER_LONG) {                             \
  72                         generic_handle_irq(irq_base + n);               \
  73                         n = find_next_bit(&status, BITS_PER_LONG, n+1); \
  74                 }                                                       \
  75         }                                                               \
  76 }
  77
  78 #define SECOND_IRQ_CHIP(_name_, irq_base, prefix)                       \
  79 SECOND_IRQ_MASK(_name_, irq_base, prefix)                               \
  80 SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                             \
  81 SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                              \
  82 static struct irq_chip _name_##_irq_chip = {                            \
  83         .name           = #_name_,                                      \
  84         .mask           = _name_##_mask_irq,                            \
  85         .mask_ack       = _name_##_mask_irq,                            \
  86         .unmask         = _name_##_unmask_irq,                          \
  87 }
  88
  89 SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
  90 SECOND_IRQ_CHIP(rtc,  IRQ_MMP2_RTC_BASE,  MMP2_ICU_INT5);
  91 SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
  92 SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
  93 SECOND_IRQ_CHIP(ssp,  IRQ_MMP2_SSP_BASE,  MMP2_ICU_INT51);
  94
  95 static void init_mux_irq(struct irq_chip *chip, int start, int num)
  96 {
  97         int irq;
  98
  99         for (irq = start; num > 0; irq++, num--) {
 100                 chip->mask_ack(irq);
 101                 set_irq_chip(irq, chip);
 102                 set_irq_flags(irq, IRQF_VALID);
 103                 set_irq_handler(irq, handle_level_irq);
 104         }
 105 }
 106
 107 void __init mmp2_init_icu(void)
 108 {
 109         int irq;
 110
 111         for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
 112                 icu_mask_irq(irq);
 113                 set_irq_chip(irq, &icu_irq_chip);
 114                 set_irq_flags(irq, IRQF_VALID);
 115
 116                 switch (irq) {
 117                 case IRQ_MMP2_PMIC_MUX:
 118                 case IRQ_MMP2_RTC_MUX:
 119                 case IRQ_MMP2_TWSI_MUX:
 120                 case IRQ_MMP2_MISC_MUX:
 121                 case IRQ_MMP2_SSP_MUX:
 122                         break;
 123                 default:
 124                         set_irq_handler(irq, handle_level_irq);
 125                         break;
 126                 }
 127         }
 128
 129         init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
 130         init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
 131         init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
 132         init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
 133         init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
 134
 135         set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
 136         set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
 137         set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
 138         set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
 139         set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
 140 }