arch/arm/mach-mvebu/coherency.c

   1 /*
   2  * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
   3  * platforms.
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Yehuda Yitschak <yehuday@marvell.com>
   8  * Gregory Clement <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
  16  * responsible for ensuring hardware coherency between all CPUs and between
  17  * CPUs and I/O masters. This file initializes the coherency fabric and
  18  * supplies basic routines for configuring and controlling hardware coherency
  19  */
  20
  21 #define pr_fmt(fmt) "mvebu-coherency: " fmt
  22
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/of_address.h>
  26 #include <linux/io.h>
  27 #include <linux/smp.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include <linux/mbus.h>
  32 #include <linux/pci.h>
  33 #include <asm/smp_plat.h>
  34 #include <asm/cacheflush.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/dma-mapping.h>
  37 #include "coherency.h"
  38 #include "mvebu-soc-id.h"
  39
  40 unsigned long coherency_phys_base;
  41 void __iomem *coherency_base;
  42 static void __iomem *coherency_cpu_base;
  43 static void __iomem *cpu_config_base;
  44
  45 /* Coherency fabric registers */
  46 #define IO_SYNC_BARRIER_CTL_OFFSET                 0x0
  47
  48 enum {
  49         COHERENCY_FABRIC_TYPE_NONE,
  50         COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
  51         COHERENCY_FABRIC_TYPE_ARMADA_375,
  52         COHERENCY_FABRIC_TYPE_ARMADA_380,
  53 };
  54
  55 static const struct of_device_id of_coherency_table[] = {
  56         {.compatible = "marvell,coherency-fabric",
  57          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
  58         {.compatible = "marvell,armada-375-coherency-fabric",
  59          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
  60         {.compatible = "marvell,armada-380-coherency-fabric",
  61          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
  62         { /* end of list */ },
  63 };
  64
  65 /* Functions defined in coherency_ll.S */
  66 int ll_enable_coherency(void);
  67 void ll_add_cpu_to_smp_group(void);
  68
  69 #define CPU_CONFIG_SHARED_L2 BIT(16)
  70
  71 /*
  72  * Disable the "Shared L2 Present" bit in CPU Configuration register
  73  * on Armada XP.
  74  *
  75  * The "Shared L2 Present" bit affects the "level of coherence" value
  76  * in the clidr CP15 register.  Cache operation functions such as
  77  * "flush all" and "invalidate all" operate on all the cache levels
  78  * that included in the defined level of coherence. When HW I/O
  79  * coherency is used, this bit causes unnecessary flushes of the L2
  80  * cache.
  81  */
  82 static void armada_xp_clear_shared_l2(void)
  83 {
  84         u32 reg;
  85
  86         if (!cpu_config_base)
  87                 return;
  88
  89         reg = readl(cpu_config_base);
  90         reg &= ~CPU_CONFIG_SHARED_L2;
  91         writel(reg, cpu_config_base);
  92 }
  93
  94 static int mvebu_hwcc_notifier(struct notifier_block *nb,
  95                                unsigned long event, void *__dev)
  96 {
  97         struct device *dev = __dev;
  98
  99         if (event != BUS_NOTIFY_ADD_DEVICE)
 100                 return NOTIFY_DONE;
 101         set_dma_ops(dev, &arm_coherent_dma_ops);
 102
 103         return NOTIFY_OK;
 104 }
 105
 106 static struct notifier_block mvebu_hwcc_nb = {
 107         .notifier_call = mvebu_hwcc_notifier,
 108 };
 109
 110 static struct notifier_block mvebu_hwcc_pci_nb __maybe_unused = {
 111         .notifier_call = mvebu_hwcc_notifier,
 112 };
 113
 114 static int armada_xp_clear_shared_l2_notifier_func(struct notifier_block *nfb,
 115                                         unsigned long action, void *hcpu)
 116 {
 117         if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
 118                 armada_xp_clear_shared_l2();
 119
 120         return NOTIFY_OK;
 121 }
 122
 123 static struct notifier_block armada_xp_clear_shared_l2_notifier = {
 124         .notifier_call = armada_xp_clear_shared_l2_notifier_func,
 125         .priority = 100,
 126 };
 127
 128 static void __init armada_370_coherency_init(struct device_node *np)
 129 {
 130         struct resource res;
 131         struct device_node *cpu_config_np;
 132
 133         of_address_to_resource(np, 0, &res);
 134         coherency_phys_base = res.start;
 135         /*
 136          * Ensure secondary CPUs will see the updated value,
 137          * which they read before they join the coherency
 138          * fabric, and therefore before they are coherent with
 139          * the boot CPU cache.
 140          */
 141         sync_cache_w(&coherency_phys_base);
 142         coherency_base = of_iomap(np, 0);
 143         coherency_cpu_base = of_iomap(np, 1);
 144
 145         cpu_config_np = of_find_compatible_node(NULL, NULL,
 146                                                 "marvell,armada-xp-cpu-config");
 147         if (!cpu_config_np)
 148                 goto exit;
 149
 150         cpu_config_base = of_iomap(cpu_config_np, 0);
 151         if (!cpu_config_base) {
 152                 of_node_put(cpu_config_np);
 153                 goto exit;
 154         }
 155
 156         of_node_put(cpu_config_np);
 157
 158         register_cpu_notifier(&armada_xp_clear_shared_l2_notifier);
 159
 160 exit:
 161         set_cpu_coherent();
 162 }
 163
 164 /*
 165  * This ioremap hook is used on Armada 375/38x to ensure that PCIe
 166  * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
 167  * is needed as a workaround for a deadlock issue between the PCIe
 168  * interface and the cache controller.
 169  */
 170 static void __iomem *
 171 armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
 172                               unsigned int mtype, void *caller)
 173 {
 174         struct resource pcie_mem;
 175
 176         mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
 177
 178         if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
 179                 mtype = MT_UNCACHED;
 180
 181         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 182 }
 183
 184 static void __init armada_375_380_coherency_init(struct device_node *np)
 185 {
 186         struct device_node *cache_dn;
 187
 188         coherency_cpu_base = of_iomap(np, 0);
 189         arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
 190
 191         /*
 192          * We should switch the PL310 to I/O coherency mode only if
 193          * I/O coherency is actually enabled.
 194          */
 195         if (!coherency_available())
 196                 return;
 197
 198         /*
 199          * Add the PL310 property "arm,io-coherent". This makes sure the
 200          * outer sync operation is not used, which allows to
 201          * workaround the system erratum that causes deadlocks when
 202          * doing PCIe in an SMP situation on Armada 375 and Armada
 203          * 38x.
 204          */
 205         for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
 206                 struct property *p;
 207
 208                 p = kzalloc(sizeof(*p), GFP_KERNEL);
 209                 p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
 210                 of_add_property(cache_dn, p);
 211         }
 212 }
 213
 214 static int coherency_type(void)
 215 {
 216         struct device_node *np;
 217         const struct of_device_id *match;
 218         int type;
 219
 220         /*
 221          * The coherency fabric is needed:
 222          * - For coherency between processors on Armada XP, so only
 223          *   when SMP is enabled.
 224          * - For coherency between the processor and I/O devices, but
 225          *   this coherency requires many pre-requisites (write
 226          *   allocate cache policy, shareable pages, SMP bit set) that
 227          *   are only meant in SMP situations.
 228          *
 229          * Note that this means that on Armada 370, there is currently
 230          * no way to use hardware I/O coherency, because even when
 231          * CONFIG_SMP is enabled, is_smp() returns false due to the
 232          * Armada 370 being a single-core processor. To lift this
 233          * limitation, we would have to find a way to make the cache
 234          * policy set to write-allocate (on all Armada SoCs), and to
 235          * set the shareable attribute in page tables (on all Armada
 236          * SoCs except the Armada 370). Unfortunately, such decisions
 237          * are taken very early in the kernel boot process, at a point
 238          * where we don't know yet on which SoC we are running.
 239
 240          */
 241         if (!is_smp())
 242                 return COHERENCY_FABRIC_TYPE_NONE;
 243
 244         np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
 245         if (!np)
 246                 return COHERENCY_FABRIC_TYPE_NONE;
 247
 248         type = (int) match->data;
 249
 250         of_node_put(np);
 251
 252         return type;
 253 }
 254
 255 int set_cpu_coherent(void)
 256 {
 257         int type = coherency_type();
 258
 259         if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
 260                 if (!coherency_base) {
 261                         pr_warn("Can't make current CPU cache coherent.\n");
 262                         pr_warn("Coherency fabric is not initialized\n");
 263                         return 1;
 264                 }
 265
 266                 armada_xp_clear_shared_l2();
 267                 ll_add_cpu_to_smp_group();
 268                 return ll_enable_coherency();
 269         }
 270
 271         return 0;
 272 }
 273
 274 int coherency_available(void)
 275 {
 276         return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
 277 }
 278
 279 int __init coherency_init(void)
 280 {
 281         int type = coherency_type();
 282         struct device_node *np;
 283
 284         np = of_find_matching_node(NULL, of_coherency_table);
 285
 286         if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
 287                 armada_370_coherency_init(np);
 288         else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
 289                  type == COHERENCY_FABRIC_TYPE_ARMADA_380)
 290                 armada_375_380_coherency_init(np);
 291
 292         of_node_put(np);
 293
 294         return 0;
 295 }
 296
 297 static int __init coherency_late_init(void)
 298 {
 299         if (coherency_available())
 300                 bus_register_notifier(&platform_bus_type,
 301                                       &mvebu_hwcc_nb);
 302         return 0;
 303 }
 304
 305 postcore_initcall(coherency_late_init);
 306
 307 #if IS_ENABLED(CONFIG_PCI)
 308 static int __init coherency_pci_init(void)
 309 {
 310         if (coherency_available())
 311                 bus_register_notifier(&pci_bus_type,
 312                                        &mvebu_hwcc_pci_nb);
 313         return 0;
 314 }
 315
 316 arch_initcall(coherency_pci_init);
 317 #endif