arch/arm/mach-mvebu/platsmp.c

   1 /*
   2  * Symmetric Multi Processing (SMP) support for Armada XP
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Yehuda Yitschak <yehuday@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
  16  * This file implements the routines for preparing the SMP infrastructure
  17  * and waking up the secondary CPUs
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/smp.h>
  22 #include <linux/clk.h>
  23 #include <linux/of.h>
  24 #include <linux/mbus.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/smp_plat.h>
  27 #include "common.h"
  28 #include "armada-370-xp.h"
  29 #include "pmsu.h"
  30 #include "coherency.h"
  31
  32 void __init set_secondary_cpus_clock(void)
  33 {
  34         int thiscpu;
  35         unsigned long rate;
  36         struct clk *cpu_clk = NULL;
  37         struct device_node *np = NULL;
  38
  39         thiscpu = smp_processor_id();
  40         for_each_node_by_type(np, "cpu") {
  41                 int err;
  42                 int cpu;
  43
  44                 err = of_property_read_u32(np, "reg", &cpu);
  45                 if (WARN_ON(err))
  46                         return;
  47
  48                 if (cpu == thiscpu) {
  49                         cpu_clk = of_clk_get(np, 0);
  50                         break;
  51                 }
  52         }
  53         if (WARN_ON(IS_ERR(cpu_clk)))
  54                 return;
  55         clk_prepare_enable(cpu_clk);
  56         rate = clk_get_rate(cpu_clk);
  57
  58         /* set all the other CPU clk to the same rate than the boot CPU */
  59         for_each_node_by_type(np, "cpu") {
  60                 int err;
  61                 int cpu;
  62
  63                 err = of_property_read_u32(np, "reg", &cpu);
  64                 if (WARN_ON(err))
  65                         return;
  66
  67                 if (cpu != thiscpu) {
  68                         cpu_clk = of_clk_get(np, 0);
  69                         clk_set_rate(cpu_clk, rate);
  70                 }
  71         }
  72 }
  73
  74 static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
  75 {
  76         armada_xp_mpic_smp_cpu_init();
  77 }
  78
  79 static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
  80                                               struct task_struct *idle)
  81 {
  82         pr_info("Booting CPU %d\n", cpu);
  83
  84         armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
  85
  86         return 0;
  87 }
  88
  89 static void __init armada_xp_smp_init_cpus(void)
  90 {
  91         struct device_node *np;
  92         unsigned int i, ncores;
  93
  94         np = of_find_node_by_name(NULL, "cpus");
  95         if (!np)
  96                 panic("No 'cpus' node found\n");
  97
  98         ncores = of_get_child_count(np);
  99         if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
 100                 panic("Invalid number of CPUs in DT\n");
 101
 102         /* Limit possible CPUs to defconfig */
 103         if (ncores > nr_cpu_ids) {
 104                 pr_warn("SMP: %d CPUs physically present. Only %d configured.",
 105                         ncores, nr_cpu_ids);
 106                 pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
 107                 ncores = nr_cpu_ids;
 108         }
 109
 110         for (i = 0; i < ncores; i++)
 111                 set_cpu_possible(i, true);
 112
 113         set_smp_cross_call(armada_mpic_send_doorbell);
 114 }
 115
 116 void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
 117 {
 118         set_secondary_cpus_clock();
 119         flush_cache_all();
 120         set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
 121         mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
 122 }
 123
 124 struct smp_operations armada_xp_smp_ops __initdata = {
 125         .smp_init_cpus          = armada_xp_smp_init_cpus,
 126         .smp_prepare_cpus       = armada_xp_smp_prepare_cpus,
 127         .smp_secondary_init     = armada_xp_secondary_init,
 128         .smp_boot_secondary     = armada_xp_boot_secondary,
 129 #ifdef CONFIG_HOTPLUG_CPU
 130         .cpu_die                = armada_xp_cpu_die,
 131 #endif
 132 };