2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/clk.h>
25 #include <asm/clkdev.h>
27 #include <mach/clock.h>
28 #include <mach/hardware.h>
29 #include <mach/common.h>
30 #include <mach/mx25.h>
32 #define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
34 #define CCM_MPCTL 0x00
35 #define CCM_UPCTL 0x04
37 #define CCM_CGCR0 0x0C
38 #define CCM_CGCR1 0x10
39 #define CCM_CGCR2 0x14
40 #define CCM_PCDR0 0x18
41 #define CCM_PCDR1 0x1C
42 #define CCM_PCDR2 0x20
43 #define CCM_PCDR3 0x24
46 #define CCM_DCVR0 0x30
47 #define CCM_DCVR1 0x34
48 #define CCM_DCVR2 0x38
49 #define CCM_DCVR3 0x3c
55 static unsigned long get_rate_mpll(void)
57 ulong mpctl
= __raw_readl(CRM_BASE
+ CCM_MPCTL
);
59 return mxc_decode_pll(mpctl
, 24000000);
62 static unsigned long get_rate_upll(void)
64 ulong mpctl
= __raw_readl(CRM_BASE
+ CCM_UPCTL
);
66 return mxc_decode_pll(mpctl
, 24000000);
69 unsigned long get_rate_arm(struct clk
*clk
)
71 unsigned long cctl
= readl(CRM_BASE
+ CCM_CCTL
);
72 unsigned long rate
= get_rate_mpll();
75 rate
= (rate
* 3) >> 2;
77 return rate
/ ((cctl
>> 30) + 1);
80 static unsigned long get_rate_ahb(struct clk
*clk
)
82 unsigned long cctl
= readl(CRM_BASE
+ CCM_CCTL
);
84 return get_rate_arm(NULL
) / (((cctl
>> 28) & 0x3) + 1);
87 static unsigned long get_rate_ipg(struct clk
*clk
)
89 return get_rate_ahb(NULL
) >> 1;
92 static unsigned long get_rate_per(int per
)
94 unsigned long ofs
= (per
& 0x3) * 8;
95 unsigned long reg
= per
& ~0x3;
96 unsigned long val
= (readl(CRM_BASE
+ CCM_PCDR0
+ reg
) >> ofs
) & 0x3f;
99 if (readl(CRM_BASE
+ 0x64) & (1 << per
))
100 fref
= get_rate_upll();
102 fref
= get_rate_ahb(NULL
);
104 return fref
/ (val
+ 1);
107 static unsigned long get_rate_uart(struct clk
*clk
)
109 return get_rate_per(15);
112 static unsigned long get_rate_ssi2(struct clk
*clk
)
114 return get_rate_per(14);
117 static unsigned long get_rate_ssi1(struct clk
*clk
)
119 return get_rate_per(13);
122 static unsigned long get_rate_i2c(struct clk
*clk
)
124 return get_rate_per(6);
127 static unsigned long get_rate_nfc(struct clk
*clk
)
129 return get_rate_per(8);
132 static unsigned long get_rate_gpt(struct clk
*clk
)
134 return get_rate_per(5);
137 static unsigned long get_rate_lcdc(struct clk
*clk
)
139 return get_rate_per(7);
142 static unsigned long get_rate_esdhc1(struct clk
*clk
)
144 return get_rate_per(3);
147 static unsigned long get_rate_esdhc2(struct clk
*clk
)
149 return get_rate_per(4);
152 static unsigned long get_rate_csi(struct clk
*clk
)
154 return get_rate_per(0);
157 static unsigned long get_rate_otg(struct clk
*clk
)
159 unsigned long cctl
= readl(CRM_BASE
+ CCM_CCTL
);
160 unsigned long rate
= get_rate_upll();
162 return (cctl
& (1 << 23)) ? 0 : rate
/ ((0x3F & (cctl
>> 16)) + 1);
165 static int clk_cgcr_enable(struct clk
*clk
)
169 reg
= __raw_readl(clk
->enable_reg
);
170 reg
|= 1 << clk
->enable_shift
;
171 __raw_writel(reg
, clk
->enable_reg
);
176 static void clk_cgcr_disable(struct clk
*clk
)
180 reg
= __raw_readl(clk
->enable_reg
);
181 reg
&= ~(1 << clk
->enable_shift
);
182 __raw_writel(reg
, clk
->enable_reg
);
185 #define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
186 static struct clk name = { \
188 .enable_reg = CRM_BASE + er, \
189 .enable_shift = es, \
192 .enable = clk_cgcr_enable, \
193 .disable = clk_cgcr_disable, \
198 * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
199 * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
200 * taken from the Freescale released BSP.
202 * bit reg offset clock
219 DEFINE_CLOCK(gpt_clk
, 0, CCM_CGCR0
, 5, get_rate_gpt
, NULL
, NULL
);
220 DEFINE_CLOCK(uart_per_clk
, 0, CCM_CGCR0
, 15, get_rate_uart
, NULL
, NULL
);
221 DEFINE_CLOCK(ssi1_per_clk
, 0, CCM_CGCR0
, 13, get_rate_ipg
, NULL
, NULL
);
222 DEFINE_CLOCK(ssi2_per_clk
, 0, CCM_CGCR0
, 14, get_rate_ipg
, NULL
, NULL
);
223 DEFINE_CLOCK(cspi1_clk
, 0, CCM_CGCR1
, 5, get_rate_ipg
, NULL
, NULL
);
224 DEFINE_CLOCK(cspi2_clk
, 0, CCM_CGCR1
, 6, get_rate_ipg
, NULL
, NULL
);
225 DEFINE_CLOCK(cspi3_clk
, 0, CCM_CGCR1
, 7, get_rate_ipg
, NULL
, NULL
);
226 DEFINE_CLOCK(esdhc1_ahb_clk
, 0, CCM_CGCR0
, 21, get_rate_esdhc1
, NULL
, NULL
);
227 DEFINE_CLOCK(esdhc1_per_clk
, 0, CCM_CGCR0
, 3, get_rate_esdhc1
, NULL
,
229 DEFINE_CLOCK(esdhc2_ahb_clk
, 0, CCM_CGCR0
, 22, get_rate_esdhc2
, NULL
, NULL
);
230 DEFINE_CLOCK(esdhc2_per_clk
, 0, CCM_CGCR0
, 4, get_rate_esdhc2
, NULL
,
232 DEFINE_CLOCK(fec_ahb_clk
, 0, CCM_CGCR0
, 23, NULL
, NULL
, NULL
);
233 DEFINE_CLOCK(lcdc_ahb_clk
, 0, CCM_CGCR0
, 24, NULL
, NULL
, NULL
);
234 DEFINE_CLOCK(lcdc_per_clk
, 0, CCM_CGCR0
, 7, NULL
, NULL
, &lcdc_ahb_clk
);
235 DEFINE_CLOCK(csi_ahb_clk
, 0, CCM_CGCR0
, 18, get_rate_csi
, NULL
, NULL
);
236 DEFINE_CLOCK(csi_per_clk
, 0, CCM_CGCR0
, 0, get_rate_csi
, NULL
, &csi_ahb_clk
);
237 DEFINE_CLOCK(uart1_clk
, 0, CCM_CGCR2
, 14, get_rate_uart
, NULL
, &uart_per_clk
);
238 DEFINE_CLOCK(uart2_clk
, 0, CCM_CGCR2
, 15, get_rate_uart
, NULL
, &uart_per_clk
);
239 DEFINE_CLOCK(uart3_clk
, 0, CCM_CGCR2
, 16, get_rate_uart
, NULL
, &uart_per_clk
);
240 DEFINE_CLOCK(uart4_clk
, 0, CCM_CGCR2
, 17, get_rate_uart
, NULL
, &uart_per_clk
);
241 DEFINE_CLOCK(uart5_clk
, 0, CCM_CGCR2
, 18, get_rate_uart
, NULL
, &uart_per_clk
);
242 DEFINE_CLOCK(nfc_clk
, 0, CCM_CGCR0
, 8, get_rate_nfc
, NULL
, NULL
);
243 DEFINE_CLOCK(usbotg_clk
, 0, CCM_CGCR0
, 28, get_rate_otg
, NULL
, NULL
);
244 DEFINE_CLOCK(pwm1_clk
, 0, CCM_CGCR1
, 31, get_rate_ipg
, NULL
, NULL
);
245 DEFINE_CLOCK(pwm2_clk
, 0, CCM_CGCR2
, 0, get_rate_ipg
, NULL
, NULL
);
246 DEFINE_CLOCK(pwm3_clk
, 0, CCM_CGCR2
, 1, get_rate_ipg
, NULL
, NULL
);
247 DEFINE_CLOCK(pwm4_clk
, 0, CCM_CGCR2
, 2, get_rate_ipg
, NULL
, NULL
);
248 DEFINE_CLOCK(kpp_clk
, 0, CCM_CGCR1
, 28, get_rate_ipg
, NULL
, NULL
);
249 DEFINE_CLOCK(tsc_clk
, 0, CCM_CGCR2
, 13, get_rate_ipg
, NULL
, NULL
);
250 DEFINE_CLOCK(i2c_clk
, 0, CCM_CGCR0
, 6, get_rate_i2c
, NULL
, NULL
);
251 DEFINE_CLOCK(fec_clk
, 0, CCM_CGCR1
, 15, get_rate_ipg
, NULL
, &fec_ahb_clk
);
252 DEFINE_CLOCK(dryice_clk
, 0, CCM_CGCR1
, 8, get_rate_ipg
, NULL
, NULL
);
253 DEFINE_CLOCK(lcdc_clk
, 0, CCM_CGCR1
, 29, get_rate_lcdc
, NULL
, &lcdc_per_clk
);
254 DEFINE_CLOCK(wdt_clk
, 0, CCM_CGCR2
, 19, get_rate_ipg
, NULL
, NULL
);
255 DEFINE_CLOCK(ssi1_clk
, 0, CCM_CGCR2
, 11, get_rate_ssi1
, NULL
, &ssi1_per_clk
);
256 DEFINE_CLOCK(ssi2_clk
, 1, CCM_CGCR2
, 12, get_rate_ssi2
, NULL
, &ssi2_per_clk
);
257 DEFINE_CLOCK(esdhc1_clk
, 0, CCM_CGCR1
, 13, get_rate_esdhc1
, NULL
,
259 DEFINE_CLOCK(esdhc2_clk
, 1, CCM_CGCR1
, 14, get_rate_esdhc2
, NULL
,
261 DEFINE_CLOCK(audmux_clk
, 0, CCM_CGCR1
, 0, NULL
, NULL
, NULL
);
262 DEFINE_CLOCK(csi_clk
, 0, CCM_CGCR1
, 4, get_rate_csi
, NULL
, &csi_per_clk
);
263 DEFINE_CLOCK(can1_clk
, 0, CCM_CGCR1
, 2, get_rate_ipg
, NULL
, NULL
);
264 DEFINE_CLOCK(can2_clk
, 1, CCM_CGCR1
, 3, get_rate_ipg
, NULL
, NULL
);
266 #define _REGISTER_CLOCK(d, n, c) \
273 static struct clk_lookup lookups
[] = {
274 _REGISTER_CLOCK("imx-uart.0", NULL
, uart1_clk
)
275 _REGISTER_CLOCK("imx-uart.1", NULL
, uart2_clk
)
276 _REGISTER_CLOCK("imx-uart.2", NULL
, uart3_clk
)
277 _REGISTER_CLOCK("imx-uart.3", NULL
, uart4_clk
)
278 _REGISTER_CLOCK("imx-uart.4", NULL
, uart5_clk
)
279 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk
)
280 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk
)
281 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk
)
282 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk
)
283 _REGISTER_CLOCK("mxc_nand.0", NULL
, nfc_clk
)
284 _REGISTER_CLOCK("imx25-cspi.0", NULL
, cspi1_clk
)
285 _REGISTER_CLOCK("imx25-cspi.1", NULL
, cspi2_clk
)
286 _REGISTER_CLOCK("imx25-cspi.2", NULL
, cspi3_clk
)
287 _REGISTER_CLOCK("mxc_pwm.0", NULL
, pwm1_clk
)
288 _REGISTER_CLOCK("mxc_pwm.1", NULL
, pwm2_clk
)
289 _REGISTER_CLOCK("mxc_pwm.2", NULL
, pwm3_clk
)
290 _REGISTER_CLOCK("mxc_pwm.3", NULL
, pwm4_clk
)
291 _REGISTER_CLOCK("imx-keypad", NULL
, kpp_clk
)
292 _REGISTER_CLOCK("mx25-adc", NULL
, tsc_clk
)
293 _REGISTER_CLOCK("imx-i2c.0", NULL
, i2c_clk
)
294 _REGISTER_CLOCK("imx-i2c.1", NULL
, i2c_clk
)
295 _REGISTER_CLOCK("imx-i2c.2", NULL
, i2c_clk
)
296 _REGISTER_CLOCK("fec.0", NULL
, fec_clk
)
297 _REGISTER_CLOCK("imxdi_rtc.0", NULL
, dryice_clk
)
298 _REGISTER_CLOCK("imx-fb.0", NULL
, lcdc_clk
)
299 _REGISTER_CLOCK("imx-wdt.0", NULL
, wdt_clk
)
300 _REGISTER_CLOCK("imx-ssi.0", NULL
, ssi1_clk
)
301 _REGISTER_CLOCK("imx-ssi.1", NULL
, ssi2_clk
)
302 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL
, esdhc1_clk
)
303 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL
, esdhc2_clk
)
304 _REGISTER_CLOCK("mx2-camera.0", NULL
, csi_clk
)
305 _REGISTER_CLOCK(NULL
, "audmux", audmux_clk
)
306 _REGISTER_CLOCK("flexcan.0", NULL
, can1_clk
)
307 _REGISTER_CLOCK("flexcan.1", NULL
, can2_clk
)
310 int __init
mx25_clocks_init(void)
312 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
314 /* Turn off all clocks except the ones we need to survive, namely:
315 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
318 __raw_writel((1 << 19), CRM_BASE
+ CCM_CGCR0
);
319 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE
+ CCM_CGCR1
);
320 __raw_writel((1 << 5), CRM_BASE
+ CCM_CGCR2
);
321 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
322 clk_enable(&uart1_clk
);
325 /* Clock source for lcdc and csi is upll */
326 __raw_writel(__raw_readl(CRM_BASE
+0x64) | (1 << 7) | (1 << 0),
329 mxc_timer_init(&gpt_clk
, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR
), 54);
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