3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c/tsc2007.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/fsl_devices.h>
27 #include <linux/i2c-gpio.h>
28 #include <linux/spi/spi.h>
29 #include <linux/can/platform/mcp251x.h>
31 #include <mach/eukrea-baseboards.h>
32 #include <mach/common.h>
33 #include <mach/hardware.h>
34 #include <mach/iomux-mx51.h>
35 #include <mach/mxc_ehci.h>
38 #include <asm/setup.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/time.h>
43 #include "devices-imx51.h"
46 #define USBH1_RST (1*32 + 28)
47 #define ETH_RST (1*32 + 31)
48 #define TSC2007_IRQGPIO (2*32 + 12)
49 #define CAN_IRQGPIO (0*32 + 1)
50 #define CAN_RST (3*32 + 15)
51 #define CAN_NCS (3*32 + 24)
52 #define CAN_RXOBF (0*32 + 4)
53 #define CAN_RX1BF (0*32 + 6)
54 #define CAN_TXORTS (0*32 + 7)
55 #define CAN_TX1RTS (0*32 + 8)
56 #define CAN_TX2RTS (0*32 + 9)
57 #define I2C_SCL (3*32 + 16)
58 #define I2C_SDA (3*32 + 17)
61 #define MX51_USB_CTRL_1_OFFSET 0x10
62 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
64 #define MX51_USB_PLLDIV_12_MHZ 0x00
65 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
66 #define MX51_USB_PLL_DIV_24_MHZ 0x02
68 #define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
69 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
71 static struct pad_desc eukrea_cpuimx51sd_pads
[] = {
73 MX51_PAD_UART1_RXD__UART1_RXD
,
74 MX51_PAD_UART1_TXD__UART1_TXD
,
75 MX51_PAD_UART1_RTS__UART1_RTS
,
76 MX51_PAD_UART1_CTS__UART1_CTS
,
79 MX51_PAD_USBH1_CLK__USBH1_CLK
,
80 MX51_PAD_USBH1_DIR__USBH1_DIR
,
81 MX51_PAD_USBH1_NXT__USBH1_NXT
,
82 MX51_PAD_USBH1_DATA0__USBH1_DATA0
,
83 MX51_PAD_USBH1_DATA1__USBH1_DATA1
,
84 MX51_PAD_USBH1_DATA2__USBH1_DATA2
,
85 MX51_PAD_USBH1_DATA3__USBH1_DATA3
,
86 MX51_PAD_USBH1_DATA4__USBH1_DATA4
,
87 MX51_PAD_USBH1_DATA5__USBH1_DATA5
,
88 MX51_PAD_USBH1_DATA6__USBH1_DATA6
,
89 MX51_PAD_USBH1_DATA7__USBH1_DATA7
,
90 MX51_PAD_USBH1_STP__USBH1_STP
,
91 MX51_PAD_EIM_CS3__GPIO_2_28
, /* PHY nRESET */
94 MX51_PAD_EIM_DTACK__GPIO_2_31
, /* PHY nRESET */
97 MX51_PAD_I2C1_CLK__GPIO_4_16
,
98 MX51_PAD_I2C1_DAT__GPIO_4_17
,
101 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI
,
102 MX51_PAD_CSPI1_MISO__ECSPI1_MISO
,
103 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK
,
104 MX51_PAD_CSPI1_SS0__GPIO_4_24
, /* nCS */
105 MX51_PAD_CSI2_PIXCLK__GPIO_4_15
, /* nReset */
106 MX51_PAD_GPIO_1_1__GPIO_1_1
, /* IRQ */
107 MX51_PAD_GPIO_1_4__GPIO_1_4
, /* Control signals */
108 MX51_PAD_GPIO_1_6__GPIO_1_6
,
109 MX51_PAD_GPIO_1_7__GPIO_1_7
,
110 MX51_PAD_GPIO_1_8__GPIO_1_8
,
111 MX51_PAD_GPIO_1_9__GPIO_1_9
,
114 CPUIMX51SD_GPIO_3_12
, /* IRQ */
117 static const struct imxuart_platform_data uart_pdata __initconst
= {
118 .flags
= IMXUART_HAVE_RTSCTS
,
121 static int ts_get_pendown_state(void)
123 return gpio_get_value(TSC2007_IRQGPIO
) ? 0 : 1;
126 static struct tsc2007_platform_data tsc2007_info
= {
129 .get_pendown_state
= ts_get_pendown_state
,
132 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices
[] = {
134 I2C_BOARD_INFO("pcf8563", 0x51),
136 I2C_BOARD_INFO("tsc2007", 0x49),
138 .platform_data
= &tsc2007_info
,
139 .irq
= gpio_to_irq(TSC2007_IRQGPIO
),
143 static const struct mxc_nand_platform_data
144 eukrea_cpuimx51sd_nand_board_info __initconst
= {
150 /* This function is board specific as the bit mask for the plldiv will also
151 be different for other Freescale SoCs, thus a common bitmask is not
152 possible and cannot get place in /plat-mxc/ehci.c.*/
153 static int initialize_otg_port(struct platform_device
*pdev
)
156 void __iomem
*usb_base
;
157 void __iomem
*usbother_base
;
159 usb_base
= ioremap(MX51_OTG_BASE_ADDR
, SZ_4K
);
160 usbother_base
= usb_base
+ MX5_USBOTHER_REGS_OFFSET
;
162 /* Set the PHY clock to 19.2MHz */
163 v
= __raw_readl(usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
164 v
&= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK
;
165 v
|= MX51_USB_PLL_DIV_19_2_MHZ
;
166 __raw_writel(v
, usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
171 static int initialize_usbh1_port(struct platform_device
*pdev
)
174 void __iomem
*usb_base
;
175 void __iomem
*usbother_base
;
177 usb_base
= ioremap(MX51_OTG_BASE_ADDR
, SZ_4K
);
178 usbother_base
= usb_base
+ MX5_USBOTHER_REGS_OFFSET
;
180 /* The clock for the USBH1 ULPI port will come from the PHY. */
181 v
= __raw_readl(usbother_base
+ MX51_USB_CTRL_1_OFFSET
);
182 __raw_writel(v
| MX51_USB_CTRL_UH1_EXT_CLK_EN
,
183 usbother_base
+ MX51_USB_CTRL_1_OFFSET
);
188 static struct mxc_usbh_platform_data dr_utmi_config
= {
189 .init
= initialize_otg_port
,
190 .portsc
= MXC_EHCI_UTMI_16BIT
,
191 .flags
= MXC_EHCI_INTERNAL_PHY
,
194 static struct fsl_usb2_platform_data usb_pdata
= {
195 .operating_mode
= FSL_USB2_DR_DEVICE
,
196 .phy_mode
= FSL_USB2_PHY_UTMI_WIDE
,
199 static struct mxc_usbh_platform_data usbh1_config
= {
200 .init
= initialize_usbh1_port
,
201 .portsc
= MXC_EHCI_MODE_ULPI
,
202 .flags
= (MXC_EHCI_POWER_PINS_ENABLED
| MXC_EHCI_ITC_NO_THRESHOLD
),
205 static int otg_mode_host
;
207 static int __init
eukrea_cpuimx51sd_otg_mode(char *options
)
209 if (!strcmp(options
, "host"))
211 else if (!strcmp(options
, "device"))
214 pr_info("otg_mode neither \"host\" nor \"device\". "
215 "Defaulting to device\n");
218 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode
);
220 static struct i2c_gpio_platform_data pdata
= {
222 .sda_is_open_drain
= 0,
224 .scl_is_open_drain
= 0,
228 static struct platform_device hsi2c_gpio_device
= {
231 .dev
.platform_data
= &pdata
,
234 static struct mcp251x_platform_data mcp251x_info
= {
235 .oscillator_frequency
= 24E6
,
238 static struct spi_board_info cpuimx51sd_spi_device
[] = {
240 .modalias
= "mcp2515",
241 .max_speed_hz
= 6500000,
245 .platform_data
= &mcp251x_info
,
246 .irq
= gpio_to_irq(0 * 32 + 1)
250 static int cpuimx51sd_spi1_cs
[] = {
254 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst
= {
255 .chipselect
= cpuimx51sd_spi1_cs
,
256 .num_chipselect
= ARRAY_SIZE(cpuimx51sd_spi1_cs
),
259 static struct platform_device
*platform_devices
[] __initdata
= {
263 static void __init
eukrea_cpuimx51sd_init(void)
265 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads
,
266 ARRAY_SIZE(eukrea_cpuimx51sd_pads
));
268 imx51_add_imx_uart(0, &uart_pdata
);
269 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info
);
271 gpio_request(ETH_RST
, "eth_rst");
272 gpio_set_value(ETH_RST
, 1);
275 gpio_request(CAN_IRQGPIO
, "can_irq");
276 gpio_direction_input(CAN_IRQGPIO
);
277 gpio_free(CAN_IRQGPIO
);
278 gpio_request(CAN_NCS
, "can_ncs");
279 gpio_direction_output(CAN_NCS
, 1);
281 gpio_request(CAN_RST
, "can_rst");
282 gpio_direction_output(CAN_RST
, 0);
284 gpio_set_value(CAN_RST
, 1);
285 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata
);
286 spi_register_board_info(cpuimx51sd_spi_device
,
287 ARRAY_SIZE(cpuimx51sd_spi_device
));
289 gpio_request(TSC2007_IRQGPIO
, "tsc2007_irq");
290 gpio_direction_input(TSC2007_IRQGPIO
);
291 gpio_free(TSC2007_IRQGPIO
);
293 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices
,
294 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices
));
295 platform_add_devices(platform_devices
, ARRAY_SIZE(platform_devices
));
298 mxc_register_device(&mxc_usbdr_host_device
, &dr_utmi_config
);
300 initialize_otg_port(NULL
);
301 mxc_register_device(&mxc_usbdr_udc_device
, &usb_pdata
);
304 gpio_request(USBH1_RST
, "usb_rst");
305 gpio_direction_output(USBH1_RST
, 0);
307 gpio_set_value(USBH1_RST
, 1);
308 mxc_register_device(&mxc_usbh1_device
, &usbh1_config
);
310 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
311 eukrea_mbimxsd51_baseboard_init();
315 static void __init
eukrea_cpuimx51sd_timer_init(void)
317 mx51_clocks_init(32768, 24000000, 22579200, 0);
320 static struct sys_timer mxc_timer
= {
321 .init
= eukrea_cpuimx51sd_timer_init
,
324 MACHINE_START(EUKREA_CPUIMX51SD
, "Eukrea CPUIMX51SD")
325 /* Maintainer: Eric Bénard <eric@eukrea.com> */
326 .phys_io
= MX51_AIPS1_BASE_ADDR
,
327 .io_pg_offst
= ((MX51_AIPS1_BASE_ADDR_VIRT
) >> 18) & 0xfffc,
328 .boot_params
= PHYS_OFFSET
+ 0x100,
329 .map_io
= mx51_map_io
,
330 .init_irq
= mx51_init_irq
,
331 .init_machine
= eukrea_cpuimx51sd_init
,