arch/arm/mach-mx5/board-mx51_efikamx.c

   1 /*
   2  * Copyright (C) 2010 Linaro Limited
   3  *
   4  * based on code from the following
   5  * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   6  * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
   7  * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/gpio.h>
  21 #include <linux/delay.h>
  22 #include <linux/io.h>
  23 #include <linux/fsl_devices.h>
  24
  25 #include <mach/common.h>
  26 #include <mach/hardware.h>
  27 #include <mach/iomux-mx51.h>
  28 #include <mach/i2c.h>
  29 #include <mach/mxc_ehci.h>
  30
  31 #include <asm/irq.h>
  32 #include <asm/setup.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/time.h>
  36
  37 #include "devices-imx51.h"
  38 #include "devices.h"
  39
  40 #define MX51_USB_PLL_DIV_24_MHZ 0x01
  41
  42 #define EFIKAMX_PCBID0          (2*32 + 16)
  43 #define EFIKAMX_PCBID1          (2*32 + 17)
  44 #define EFIKAMX_PCBID2          (2*32 + 11)
  45
  46 /* the pci ids pin have pull up. they're driven low according to board id */
  47 #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
  48 #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
  49 #define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
  50
  51 static iomux_v3_cfg_t mx51efikamx_pads[] = {
  52         /* UART1 */
  53         MX51_PAD_UART1_RXD__UART1_RXD,
  54         MX51_PAD_UART1_TXD__UART1_TXD,
  55         MX51_PAD_UART1_RTS__UART1_RTS,
  56         MX51_PAD_UART1_CTS__UART1_CTS,
  57         /* board id */
  58         MX51_PAD_PCBID0,
  59         MX51_PAD_PCBID1,
  60         MX51_PAD_PCBID2,
  61
  62         /* SD 1 */
  63         MX51_PAD_SD1_CMD__SD1_CMD,
  64         MX51_PAD_SD1_CLK__SD1_CLK,
  65         MX51_PAD_SD1_DATA0__SD1_DATA0,
  66         MX51_PAD_SD1_DATA1__SD1_DATA1,
  67         MX51_PAD_SD1_DATA2__SD1_DATA2,
  68         MX51_PAD_SD1_DATA3__SD1_DATA3,
  69
  70         /* SD 2 */
  71         MX51_PAD_SD2_CMD__SD2_CMD,
  72         MX51_PAD_SD2_CLK__SD2_CLK,
  73         MX51_PAD_SD2_DATA0__SD2_DATA0,
  74         MX51_PAD_SD2_DATA1__SD2_DATA1,
  75         MX51_PAD_SD2_DATA2__SD2_DATA2,
  76         MX51_PAD_SD2_DATA3__SD2_DATA3,
  77
  78         /* SD/MMC WP/CD */
  79         MX51_PAD_GPIO_1_0__ESDHC1_CD,
  80         MX51_PAD_GPIO_1_1__ESDHC1_WP,
  81         MX51_PAD_GPIO_1_7__ESDHC2_WP,
  82         MX51_PAD_GPIO_1_8__ESDHC2_CD,
  83 };
  84
  85 /* Serial ports */
  86 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
  87 static const struct imxuart_platform_data uart_pdata = {
  88         .flags = IMXUART_HAVE_RTSCTS,
  89 };
  90
  91 static inline void mxc_init_imx_uart(void)
  92 {
  93         imx51_add_imx_uart(0, &uart_pdata);
  94         imx51_add_imx_uart(1, &uart_pdata);
  95         imx51_add_imx_uart(2, &uart_pdata);
  96 }
  97 #else /* !SERIAL_IMX */
  98 static inline void mxc_init_imx_uart(void)
  99 {
 100 }
 101 #endif /* SERIAL_IMX */
 102
 103 /* This function is board specific as the bit mask for the plldiv will also
 104  * be different for other Freescale SoCs, thus a common bitmask is not
 105  * possible and cannot get place in /plat-mxc/ehci.c.
 106  */
 107 static int initialize_otg_port(struct platform_device *pdev)
 108 {
 109         u32 v;
 110         void __iomem *usb_base;
 111         void __iomem *usbother_base;
 112         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 113         usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
 114
 115         /* Set the PHY clock to 19.2MHz */
 116         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 117         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 118         v |= MX51_USB_PLL_DIV_24_MHZ;
 119         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 120         iounmap(usb_base);
 121         return 0;
 122 }
 123
 124 static struct mxc_usbh_platform_data dr_utmi_config = {
 125         .init   = initialize_otg_port,
 126         .portsc = MXC_EHCI_UTMI_16BIT,
 127         .flags  = MXC_EHCI_INTERNAL_PHY,
 128 };
 129
 130 /*   PCBID2  PCBID1 PCBID0  STATE
 131         1       1      1    ER1:rev1.1
 132         1       1      0    ER2:rev1.2
 133         1       0      1    ER3:rev1.3
 134         1       0      0    ER4:rev1.4
 135 */
 136 static void __init mx51_efikamx_board_id(void)
 137 {
 138         int id;
 139
 140         /* things are taking time to settle */
 141         msleep(150);
 142
 143         gpio_request(EFIKAMX_PCBID0, "pcbid0");
 144         gpio_direction_input(EFIKAMX_PCBID0);
 145         gpio_request(EFIKAMX_PCBID1, "pcbid1");
 146         gpio_direction_input(EFIKAMX_PCBID1);
 147         gpio_request(EFIKAMX_PCBID2, "pcbid2");
 148         gpio_direction_input(EFIKAMX_PCBID2);
 149
 150         id = gpio_get_value(EFIKAMX_PCBID0);
 151         id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
 152         id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
 153
 154         switch (id) {
 155         case 7:
 156                 system_rev = 0x11;
 157                 break;
 158         case 6:
 159                 system_rev = 0x12;
 160                 break;
 161         case 5:
 162                 system_rev = 0x13;
 163                 break;
 164         case 4:
 165                 system_rev = 0x14;
 166                 break;
 167         default:
 168                 system_rev = 0x10;
 169                 break;
 170         }
 171
 172         if ((system_rev == 0x10)
 173                 || (system_rev == 0x12)
 174                 || (system_rev == 0x14)) {
 175                 printk(KERN_WARNING
 176                         "EfikaMX: Unsupported board revision 1.%u!\n",
 177                         system_rev & 0xf);
 178         }
 179 }
 180
 181 static void __init mxc_board_init(void)
 182 {
 183         mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
 184                                         ARRAY_SIZE(mx51efikamx_pads));
 185         mx51_efikamx_board_id();
 186         mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 187         mxc_init_imx_uart();
 188         imx51_add_esdhc(0, NULL);
 189
 190         /* on < 1.2 boards both SD controllers are used */
 191         if (system_rev < 0x12)
 192                 imx51_add_esdhc(1, NULL);
 193 }
 194
 195 static void __init mx51_efikamx_timer_init(void)
 196 {
 197         mx51_clocks_init(32768, 24000000, 22579200, 24576000);
 198 }
 199
 200 static struct sys_timer mxc_timer = {
 201         .init   = mx51_efikamx_timer_init,
 202 };
 203
 204 MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
 205         /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
 206         .boot_params = MX51_PHYS_OFFSET + 0x100,
 207         .map_io = mx51_map_io,
 208         .init_irq = mx51_init_irq,
 209         .init_machine =  mxc_board_init,
 210         .timer = &mxc_timer,
 211 MACHINE_END