2 * linux/arch/arm/mach-omap1/irq.c
4 * Interrupt handler for all OMAP boards
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
10 * Completely re-written to support various OMAP chips with bank specific
13 * Some snippets of the code taken from the older OMAP interrupt handler
14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
39 #include <linux/init.h>
40 #include <linux/module.h>
41 #include <linux/sched.h>
42 #include <linux/interrupt.h>
45 #include <mach/hardware.h>
47 #include <asm/mach/irq.h>
48 #include <mach/gpio.h>
51 #define IRQ_BANK(irq) ((irq) >> 5)
52 #define IRQ_BIT(irq) ((irq) & 0x1f)
54 struct omap_irq_bank
{
55 unsigned long base_reg
;
56 unsigned long trigger_map
;
57 unsigned long wake_enable
;
60 static unsigned int irq_bank_count
;
61 static struct omap_irq_bank
*irq_banks
;
63 static inline unsigned int irq_bank_readl(int bank
, int offset
)
65 return omap_readl(irq_banks
[bank
].base_reg
+ offset
);
68 static inline void irq_bank_writel(unsigned long value
, int bank
, int offset
)
70 omap_writel(value
, irq_banks
[bank
].base_reg
+ offset
);
73 static void omap_ack_irq(unsigned int irq
)
76 omap_writel(0x1, OMAP_IH2_BASE
+ IRQ_CONTROL_REG_OFFSET
);
78 omap_writel(0x1, OMAP_IH1_BASE
+ IRQ_CONTROL_REG_OFFSET
);
81 static void omap_mask_irq(unsigned int irq
)
83 int bank
= IRQ_BANK(irq
);
86 l
= omap_readl(irq_banks
[bank
].base_reg
+ IRQ_MIR_REG_OFFSET
);
87 l
|= 1 << IRQ_BIT(irq
);
88 omap_writel(l
, irq_banks
[bank
].base_reg
+ IRQ_MIR_REG_OFFSET
);
91 static void omap_unmask_irq(unsigned int irq
)
93 int bank
= IRQ_BANK(irq
);
96 l
= omap_readl(irq_banks
[bank
].base_reg
+ IRQ_MIR_REG_OFFSET
);
97 l
&= ~(1 << IRQ_BIT(irq
));
98 omap_writel(l
, irq_banks
[bank
].base_reg
+ IRQ_MIR_REG_OFFSET
);
101 static void omap_mask_ack_irq(unsigned int irq
)
107 static int omap_wake_irq(unsigned int irq
, unsigned int enable
)
109 int bank
= IRQ_BANK(irq
);
112 irq_banks
[bank
].wake_enable
|= IRQ_BIT(irq
);
114 irq_banks
[bank
].wake_enable
&= ~IRQ_BIT(irq
);
121 * Allows tuning the IRQ type and priority
123 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
124 * mailing list threads on FIQ handlers if you are planning to
125 * add a FIQ handler for OMAP.
127 static void omap_irq_set_cfg(int irq
, int fiq
, int priority
, int trigger
)
130 unsigned long val
, offset
;
132 bank
= IRQ_BANK(irq
);
133 /* FIQ is only available on bank 0 interrupts */
134 fiq
= bank
? 0 : (fiq
& 0x1);
135 val
= fiq
| ((priority
& 0x1f) << 2) | ((trigger
& 0x1) << 1);
136 offset
= IRQ_ILR0_REG_OFFSET
+ IRQ_BIT(irq
) * 0x4;
137 irq_bank_writel(val
, bank
, offset
);
140 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
141 static struct omap_irq_bank omap730_irq_banks
[] = {
142 { .base_reg
= OMAP_IH1_BASE
, .trigger_map
= 0xb3f8e22f },
143 { .base_reg
= OMAP_IH2_BASE
, .trigger_map
= 0xfdb9c1f2 },
144 { .base_reg
= OMAP_IH2_BASE
+ 0x100, .trigger_map
= 0x800040f3 },
148 #ifdef CONFIG_ARCH_OMAP15XX
149 static struct omap_irq_bank omap1510_irq_banks
[] = {
150 { .base_reg
= OMAP_IH1_BASE
, .trigger_map
= 0xb3febfff },
151 { .base_reg
= OMAP_IH2_BASE
, .trigger_map
= 0xffbfffed },
153 static struct omap_irq_bank omap310_irq_banks
[] = {
154 { .base_reg
= OMAP_IH1_BASE
, .trigger_map
= 0xb3faefc3 },
155 { .base_reg
= OMAP_IH2_BASE
, .trigger_map
= 0x65b3c061 },
159 #if defined(CONFIG_ARCH_OMAP16XX)
161 static struct omap_irq_bank omap1610_irq_banks
[] = {
162 { .base_reg
= OMAP_IH1_BASE
, .trigger_map
= 0xb3fefe8f },
163 { .base_reg
= OMAP_IH2_BASE
, .trigger_map
= 0xfdb7c1fd },
164 { .base_reg
= OMAP_IH2_BASE
+ 0x100, .trigger_map
= 0xffffb7ff },
165 { .base_reg
= OMAP_IH2_BASE
+ 0x200, .trigger_map
= 0xffffffff },
169 static struct irq_chip omap_irq_chip
= {
171 .ack
= omap_mask_ack_irq
,
172 .mask
= omap_mask_irq
,
173 .unmask
= omap_unmask_irq
,
174 .set_wake
= omap_wake_irq
,
177 void __init
omap_init_irq(void)
181 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
182 if (cpu_is_omap7xx()) {
183 irq_banks
= omap730_irq_banks
;
184 irq_bank_count
= ARRAY_SIZE(omap730_irq_banks
);
187 #ifdef CONFIG_ARCH_OMAP15XX
188 if (cpu_is_omap1510()) {
189 irq_banks
= omap1510_irq_banks
;
190 irq_bank_count
= ARRAY_SIZE(omap1510_irq_banks
);
192 if (cpu_is_omap310()) {
193 irq_banks
= omap310_irq_banks
;
194 irq_bank_count
= ARRAY_SIZE(omap310_irq_banks
);
197 #if defined(CONFIG_ARCH_OMAP16XX)
198 if (cpu_is_omap16xx()) {
199 irq_banks
= omap1610_irq_banks
;
200 irq_bank_count
= ARRAY_SIZE(omap1610_irq_banks
);
203 printk("Total of %i interrupts in %i interrupt banks\n",
204 irq_bank_count
* 32, irq_bank_count
);
206 /* Mask and clear all interrupts */
207 for (i
= 0; i
< irq_bank_count
; i
++) {
208 irq_bank_writel(~0x0, i
, IRQ_MIR_REG_OFFSET
);
209 irq_bank_writel(0x0, i
, IRQ_ITR_REG_OFFSET
);
212 /* Clear any pending interrupts */
213 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET
);
214 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET
);
216 /* Enable interrupts in global mask */
217 if (cpu_is_omap7xx())
218 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET
);
220 /* Install the interrupt handlers for each bank */
221 for (i
= 0; i
< irq_bank_count
; i
++) {
222 for (j
= i
* 32; j
< (i
+ 1) * 32; j
++) {
225 irq_trigger
= irq_banks
[i
].trigger_map
>> IRQ_BIT(j
);
226 omap_irq_set_cfg(j
, 0, 0, irq_trigger
);
228 set_irq_chip(j
, &omap_irq_chip
);
229 set_irq_handler(j
, handle_level_irq
);
230 set_irq_flags(j
, IRQF_VALID
);
234 /* Unmask level 2 handler */
236 if (cpu_is_omap7xx())
237 omap_unmask_irq(INT_7XX_IH2_IRQ
);
238 else if (cpu_is_omap15xx())
239 omap_unmask_irq(INT_1510_IH2_IRQ
);
240 else if (cpu_is_omap16xx())
241 omap_unmask_irq(INT_1610_IH2_IRQ
);