4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/clk.h>
26 #include <plat/control.h>
27 #include <plat/clkdev_omap.h>
30 #include "clock44xx.h"
32 #include "cm-regbits-44xx.h"
34 #include "prm-regbits-44xx.h"
38 static struct clk extalt_clkin_ck
= {
39 .name
= "extalt_clkin_ck",
42 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
45 static struct clk pad_clks_ck
= {
46 .name
= "pad_clks_ck",
49 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
52 static struct clk pad_slimbus_core_clks_ck
= {
53 .name
= "pad_slimbus_core_clks_ck",
56 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
59 static struct clk secure_32k_clk_src_ck
= {
60 .name
= "secure_32k_clk_src_ck",
63 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
66 static struct clk slimbus_clk
= {
67 .name
= "slimbus_clk",
70 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
73 static struct clk sys_32k_ck
= {
77 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
80 static struct clk virt_12000000_ck
= {
81 .name
= "virt_12000000_ck",
86 static struct clk virt_13000000_ck
= {
87 .name
= "virt_13000000_ck",
92 static struct clk virt_16800000_ck
= {
93 .name
= "virt_16800000_ck",
98 static struct clk virt_19200000_ck
= {
99 .name
= "virt_19200000_ck",
104 static struct clk virt_26000000_ck
= {
105 .name
= "virt_26000000_ck",
110 static struct clk virt_27000000_ck
= {
111 .name
= "virt_27000000_ck",
116 static struct clk virt_38400000_ck
= {
117 .name
= "virt_38400000_ck",
122 static const struct clksel_rate div_1_0_rates
[] = {
123 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
127 static const struct clksel_rate div_1_1_rates
[] = {
128 { .div
= 1, .val
= 1, .flags
= RATE_IN_4430
},
132 static const struct clksel_rate div_1_2_rates
[] = {
133 { .div
= 1, .val
= 2, .flags
= RATE_IN_4430
},
137 static const struct clksel_rate div_1_3_rates
[] = {
138 { .div
= 1, .val
= 3, .flags
= RATE_IN_4430
},
142 static const struct clksel_rate div_1_4_rates
[] = {
143 { .div
= 1, .val
= 4, .flags
= RATE_IN_4430
},
147 static const struct clksel_rate div_1_5_rates
[] = {
148 { .div
= 1, .val
= 5, .flags
= RATE_IN_4430
},
152 static const struct clksel_rate div_1_6_rates
[] = {
153 { .div
= 1, .val
= 6, .flags
= RATE_IN_4430
},
157 static const struct clksel_rate div_1_7_rates
[] = {
158 { .div
= 1, .val
= 7, .flags
= RATE_IN_4430
},
162 static const struct clksel sys_clkin_sel
[] = {
163 { .parent
= &virt_12000000_ck
, .rates
= div_1_1_rates
},
164 { .parent
= &virt_13000000_ck
, .rates
= div_1_2_rates
},
165 { .parent
= &virt_16800000_ck
, .rates
= div_1_3_rates
},
166 { .parent
= &virt_19200000_ck
, .rates
= div_1_4_rates
},
167 { .parent
= &virt_26000000_ck
, .rates
= div_1_5_rates
},
168 { .parent
= &virt_27000000_ck
, .rates
= div_1_6_rates
},
169 { .parent
= &virt_38400000_ck
, .rates
= div_1_7_rates
},
173 static struct clk sys_clkin_ck
= {
174 .name
= "sys_clkin_ck",
176 .clksel
= sys_clkin_sel
,
177 .init
= &omap2_init_clksel_parent
,
178 .clksel_reg
= OMAP4430_CM_SYS_CLKSEL
,
179 .clksel_mask
= OMAP4430_SYS_CLKSEL_MASK
,
181 .recalc
= &omap2_clksel_recalc
,
182 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
185 static struct clk utmi_phy_clkout_ck
= {
186 .name
= "utmi_phy_clkout_ck",
189 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
192 static struct clk xclk60mhsp1_ck
= {
193 .name
= "xclk60mhsp1_ck",
196 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
199 static struct clk xclk60mhsp2_ck
= {
200 .name
= "xclk60mhsp2_ck",
203 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
206 static struct clk xclk60motg_ck
= {
207 .name
= "xclk60motg_ck",
210 .flags
= CLOCK_IN_OMAP4430
| ALWAYS_ENABLED
,
213 /* Module clocks and DPLL outputs */
215 static const struct clksel_rate div2_1to2_rates
[] = {
216 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
217 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
221 static const struct clksel dpll_sys_ref_clk_div
[] = {
222 { .parent
= &sys_clkin_ck
, .rates
= div2_1to2_rates
},
226 static struct clk dpll_sys_ref_clk
= {
227 .name
= "dpll_sys_ref_clk",
228 .parent
= &sys_clkin_ck
,
229 .clksel
= dpll_sys_ref_clk_div
,
230 .clksel_reg
= OMAP4430_CM_DPLL_SYS_REF_CLKSEL
,
231 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
233 .recalc
= &omap2_clksel_recalc
,
234 .round_rate
= &omap2_clksel_round_rate
,
235 .set_rate
= &omap2_clksel_set_rate
,
236 .flags
= CLOCK_IN_OMAP4430
,
239 static const struct clksel abe_dpll_refclk_mux_sel
[] = {
240 { .parent
= &dpll_sys_ref_clk
, .rates
= div_1_0_rates
},
241 { .parent
= &sys_32k_ck
, .rates
= div_1_1_rates
},
245 static struct clk abe_dpll_refclk_mux_ck
= {
246 .name
= "abe_dpll_refclk_mux_ck",
247 .parent
= &dpll_sys_ref_clk
,
248 .clksel
= abe_dpll_refclk_mux_sel
,
249 .init
= &omap2_init_clksel_parent
,
250 .clksel_reg
= OMAP4430_CM_ABE_PLL_REF_CLKSEL
,
251 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
253 .recalc
= &omap2_clksel_recalc
,
254 .flags
= CLOCK_IN_OMAP4430
,
258 static struct dpll_data dpll_abe_dd
= {
259 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_ABE
,
260 .clk_bypass
= &sys_clkin_ck
,
261 .clk_ref
= &abe_dpll_refclk_mux_ck
,
262 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_ABE
,
263 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
264 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_ABE
,
265 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_ABE
,
266 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
267 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
268 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
269 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
270 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
271 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
272 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
277 static struct clk dpll_abe_ck
= {
278 .name
= "dpll_abe_ck",
279 .parent
= &abe_dpll_refclk_mux_ck
,
280 .dpll_data
= &dpll_abe_dd
,
281 .init
= &omap2_init_dpll_parent
,
282 .ops
= &clkops_noncore_dpll_ops
,
283 .recalc
= &omap3_dpll_recalc
,
284 .round_rate
= &omap2_dpll_round_rate
,
285 .set_rate
= &omap3_noncore_dpll_set_rate
,
286 .flags
= CLOCK_IN_OMAP4430
,
289 static struct clk dpll_abe_m2x2_ck
= {
290 .name
= "dpll_abe_m2x2_ck",
291 .parent
= &dpll_abe_ck
,
293 .recalc
= &followparent_recalc
,
294 .flags
= CLOCK_IN_OMAP4430
,
297 static struct clk abe_24m_fclk
= {
298 .name
= "abe_24m_fclk",
299 .parent
= &dpll_abe_m2x2_ck
,
301 .recalc
= &followparent_recalc
,
302 .flags
= CLOCK_IN_OMAP4430
,
305 static const struct clksel_rate div3_1to4_rates
[] = {
306 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
307 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
308 { .div
= 4, .val
= 2, .flags
= RATE_IN_4430
},
312 static const struct clksel abe_clk_div
[] = {
313 { .parent
= &dpll_abe_m2x2_ck
, .rates
= div3_1to4_rates
},
317 static struct clk abe_clk
= {
319 .parent
= &dpll_abe_m2x2_ck
,
320 .clksel
= abe_clk_div
,
321 .clksel_reg
= OMAP4430_CM_CLKSEL_ABE
,
322 .clksel_mask
= OMAP4430_CLKSEL_OPP_MASK
,
324 .recalc
= &omap2_clksel_recalc
,
325 .round_rate
= &omap2_clksel_round_rate
,
326 .set_rate
= &omap2_clksel_set_rate
,
327 .flags
= CLOCK_IN_OMAP4430
,
330 static const struct clksel aess_fclk_div
[] = {
331 { .parent
= &abe_clk
, .rates
= div2_1to2_rates
},
335 static struct clk aess_fclk
= {
338 .clksel
= aess_fclk_div
,
339 .clksel_reg
= OMAP4430_CM1_ABE_AESS_CLKCTRL
,
340 .clksel_mask
= OMAP4430_CLKSEL_AESS_FCLK_MASK
,
342 .recalc
= &omap2_clksel_recalc
,
343 .round_rate
= &omap2_clksel_round_rate
,
344 .set_rate
= &omap2_clksel_set_rate
,
345 .flags
= CLOCK_IN_OMAP4430
,
348 static const struct clksel_rate div31_1to31_rates
[] = {
349 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
350 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
351 { .div
= 3, .val
= 2, .flags
= RATE_IN_4430
},
352 { .div
= 4, .val
= 3, .flags
= RATE_IN_4430
},
353 { .div
= 5, .val
= 4, .flags
= RATE_IN_4430
},
354 { .div
= 6, .val
= 5, .flags
= RATE_IN_4430
},
355 { .div
= 7, .val
= 6, .flags
= RATE_IN_4430
},
356 { .div
= 8, .val
= 7, .flags
= RATE_IN_4430
},
357 { .div
= 9, .val
= 8, .flags
= RATE_IN_4430
},
358 { .div
= 10, .val
= 9, .flags
= RATE_IN_4430
},
359 { .div
= 11, .val
= 10, .flags
= RATE_IN_4430
},
360 { .div
= 12, .val
= 11, .flags
= RATE_IN_4430
},
361 { .div
= 13, .val
= 12, .flags
= RATE_IN_4430
},
362 { .div
= 14, .val
= 13, .flags
= RATE_IN_4430
},
363 { .div
= 15, .val
= 14, .flags
= RATE_IN_4430
},
364 { .div
= 16, .val
= 15, .flags
= RATE_IN_4430
},
365 { .div
= 17, .val
= 16, .flags
= RATE_IN_4430
},
366 { .div
= 18, .val
= 17, .flags
= RATE_IN_4430
},
367 { .div
= 19, .val
= 18, .flags
= RATE_IN_4430
},
368 { .div
= 20, .val
= 19, .flags
= RATE_IN_4430
},
369 { .div
= 21, .val
= 20, .flags
= RATE_IN_4430
},
370 { .div
= 22, .val
= 21, .flags
= RATE_IN_4430
},
371 { .div
= 23, .val
= 22, .flags
= RATE_IN_4430
},
372 { .div
= 24, .val
= 23, .flags
= RATE_IN_4430
},
373 { .div
= 25, .val
= 24, .flags
= RATE_IN_4430
},
374 { .div
= 26, .val
= 25, .flags
= RATE_IN_4430
},
375 { .div
= 27, .val
= 26, .flags
= RATE_IN_4430
},
376 { .div
= 28, .val
= 27, .flags
= RATE_IN_4430
},
377 { .div
= 29, .val
= 28, .flags
= RATE_IN_4430
},
378 { .div
= 30, .val
= 29, .flags
= RATE_IN_4430
},
379 { .div
= 31, .val
= 30, .flags
= RATE_IN_4430
},
383 static const struct clksel dpll_abe_m3_div
[] = {
384 { .parent
= &dpll_abe_ck
, .rates
= div31_1to31_rates
},
388 static struct clk dpll_abe_m3_ck
= {
389 .name
= "dpll_abe_m3_ck",
390 .parent
= &dpll_abe_ck
,
391 .clksel
= dpll_abe_m3_div
,
392 .clksel_reg
= OMAP4430_CM_DIV_M3_DPLL_ABE
,
393 .clksel_mask
= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
,
395 .recalc
= &omap2_clksel_recalc
,
396 .round_rate
= &omap2_clksel_round_rate
,
397 .set_rate
= &omap2_clksel_set_rate
,
398 .flags
= CLOCK_IN_OMAP4430
,
401 static const struct clksel core_hsd_byp_clk_mux_sel
[] = {
402 { .parent
= &dpll_sys_ref_clk
, .rates
= div_1_0_rates
},
403 { .parent
= &dpll_abe_m3_ck
, .rates
= div_1_1_rates
},
407 static struct clk core_hsd_byp_clk_mux_ck
= {
408 .name
= "core_hsd_byp_clk_mux_ck",
409 .parent
= &dpll_sys_ref_clk
,
410 .clksel
= core_hsd_byp_clk_mux_sel
,
411 .init
= &omap2_init_clksel_parent
,
412 .clksel_reg
= OMAP4430_CM_CLKSEL_DPLL_CORE
,
413 .clksel_mask
= OMAP4430_DPLL_BYP_CLKSEL_MASK
,
415 .recalc
= &omap2_clksel_recalc
,
416 .flags
= CLOCK_IN_OMAP4430
,
420 static struct dpll_data dpll_core_dd
= {
421 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_CORE
,
422 .clk_bypass
= &core_hsd_byp_clk_mux_ck
,
423 .clk_ref
= &dpll_sys_ref_clk
,
424 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_CORE
,
425 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
426 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_CORE
,
427 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_CORE
,
428 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
429 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
430 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
431 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
432 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
433 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
434 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
439 static struct clk dpll_core_ck
= {
440 .name
= "dpll_core_ck",
441 .parent
= &dpll_sys_ref_clk
,
442 .dpll_data
= &dpll_core_dd
,
443 .init
= &omap2_init_dpll_parent
,
445 .recalc
= &omap3_dpll_recalc
,
446 .flags
= CLOCK_IN_OMAP4430
,
449 static const struct clksel dpll_core_m6_div
[] = {
450 { .parent
= &dpll_core_ck
, .rates
= div31_1to31_rates
},
454 static struct clk dpll_core_m6_ck
= {
455 .name
= "dpll_core_m6_ck",
456 .parent
= &dpll_core_ck
,
457 .clksel
= dpll_core_m6_div
,
458 .clksel_reg
= OMAP4430_CM_DIV_M6_DPLL_CORE
,
459 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK
,
461 .recalc
= &omap2_clksel_recalc
,
462 .round_rate
= &omap2_clksel_round_rate
,
463 .set_rate
= &omap2_clksel_set_rate
,
464 .flags
= CLOCK_IN_OMAP4430
,
467 static const struct clksel dbgclk_mux_sel
[] = {
468 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
469 { .parent
= &dpll_core_m6_ck
, .rates
= div_1_1_rates
},
473 static struct clk dbgclk_mux_ck
= {
474 .name
= "dbgclk_mux_ck",
475 .parent
= &sys_clkin_ck
,
477 .recalc
= &followparent_recalc
,
478 .flags
= CLOCK_IN_OMAP4430
,
481 static struct clk dpll_core_m2_ck
= {
482 .name
= "dpll_core_m2_ck",
483 .parent
= &dpll_core_ck
,
484 .clksel
= dpll_core_m6_div
,
485 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_CORE
,
486 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
488 .recalc
= &omap2_clksel_recalc
,
489 .round_rate
= &omap2_clksel_round_rate
,
490 .set_rate
= &omap2_clksel_set_rate
,
491 .flags
= CLOCK_IN_OMAP4430
,
494 static struct clk ddrphy_ck
= {
496 .parent
= &dpll_core_m2_ck
,
498 .recalc
= &followparent_recalc
,
499 .flags
= CLOCK_IN_OMAP4430
,
502 static struct clk dpll_core_m5_ck
= {
503 .name
= "dpll_core_m5_ck",
504 .parent
= &dpll_core_ck
,
505 .clksel
= dpll_core_m6_div
,
506 .clksel_reg
= OMAP4430_CM_DIV_M5_DPLL_CORE
,
507 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
,
509 .recalc
= &omap2_clksel_recalc
,
510 .round_rate
= &omap2_clksel_round_rate
,
511 .set_rate
= &omap2_clksel_set_rate
,
512 .flags
= CLOCK_IN_OMAP4430
,
515 static const struct clksel div_core_div
[] = {
516 { .parent
= &dpll_core_m5_ck
, .rates
= div2_1to2_rates
},
520 static struct clk div_core_ck
= {
521 .name
= "div_core_ck",
522 .parent
= &dpll_core_m5_ck
,
523 .clksel
= div_core_div
,
524 .clksel_reg
= OMAP4430_CM_CLKSEL_CORE
,
525 .clksel_mask
= OMAP4430_CLKSEL_CORE_MASK
,
527 .recalc
= &omap2_clksel_recalc
,
528 .round_rate
= &omap2_clksel_round_rate
,
529 .set_rate
= &omap2_clksel_set_rate
,
530 .flags
= CLOCK_IN_OMAP4430
,
533 static const struct clksel_rate div4_1to8_rates
[] = {
534 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
535 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
536 { .div
= 4, .val
= 2, .flags
= RATE_IN_4430
},
537 { .div
= 8, .val
= 3, .flags
= RATE_IN_4430
},
541 static const struct clksel div_iva_hs_clk_div
[] = {
542 { .parent
= &dpll_core_m5_ck
, .rates
= div4_1to8_rates
},
546 static struct clk div_iva_hs_clk
= {
547 .name
= "div_iva_hs_clk",
548 .parent
= &dpll_core_m5_ck
,
549 .clksel
= div_iva_hs_clk_div
,
550 .clksel_reg
= OMAP4430_CM_BYPCLK_DPLL_IVA
,
551 .clksel_mask
= OMAP4430_CLKSEL_0_1_MASK
,
553 .recalc
= &omap2_clksel_recalc
,
554 .round_rate
= &omap2_clksel_round_rate
,
555 .set_rate
= &omap2_clksel_set_rate
,
556 .flags
= CLOCK_IN_OMAP4430
,
559 static struct clk div_mpu_hs_clk
= {
560 .name
= "div_mpu_hs_clk",
561 .parent
= &dpll_core_m5_ck
,
562 .clksel
= div_iva_hs_clk_div
,
563 .clksel_reg
= OMAP4430_CM_BYPCLK_DPLL_MPU
,
564 .clksel_mask
= OMAP4430_CLKSEL_0_1_MASK
,
566 .recalc
= &omap2_clksel_recalc
,
567 .round_rate
= &omap2_clksel_round_rate
,
568 .set_rate
= &omap2_clksel_set_rate
,
569 .flags
= CLOCK_IN_OMAP4430
,
572 static struct clk dpll_core_m4_ck
= {
573 .name
= "dpll_core_m4_ck",
574 .parent
= &dpll_core_ck
,
575 .clksel
= dpll_core_m6_div
,
576 .clksel_reg
= OMAP4430_CM_DIV_M4_DPLL_CORE
,
577 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
,
579 .recalc
= &omap2_clksel_recalc
,
580 .round_rate
= &omap2_clksel_round_rate
,
581 .set_rate
= &omap2_clksel_set_rate
,
582 .flags
= CLOCK_IN_OMAP4430
,
585 static struct clk dll_clk_div_ck
= {
586 .name
= "dll_clk_div_ck",
587 .parent
= &dpll_core_m4_ck
,
589 .recalc
= &followparent_recalc
,
590 .flags
= CLOCK_IN_OMAP4430
,
593 static struct clk dpll_abe_m2_ck
= {
594 .name
= "dpll_abe_m2_ck",
595 .parent
= &dpll_abe_ck
,
596 .clksel
= dpll_abe_m3_div
,
597 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_ABE
,
598 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
600 .recalc
= &omap2_clksel_recalc
,
601 .round_rate
= &omap2_clksel_round_rate
,
602 .set_rate
= &omap2_clksel_set_rate
,
603 .flags
= CLOCK_IN_OMAP4430
,
606 static struct clk dpll_core_m3_ck
= {
607 .name
= "dpll_core_m3_ck",
608 .parent
= &dpll_core_ck
,
609 .clksel
= dpll_core_m6_div
,
610 .clksel_reg
= OMAP4430_CM_DIV_M3_DPLL_CORE
,
611 .clksel_mask
= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
,
613 .recalc
= &omap2_clksel_recalc
,
614 .round_rate
= &omap2_clksel_round_rate
,
615 .set_rate
= &omap2_clksel_set_rate
,
616 .flags
= CLOCK_IN_OMAP4430
,
619 static struct clk dpll_core_m7_ck
= {
620 .name
= "dpll_core_m7_ck",
621 .parent
= &dpll_core_ck
,
622 .clksel
= dpll_core_m6_div
,
623 .clksel_reg
= OMAP4430_CM_DIV_M7_DPLL_CORE
,
624 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK
,
626 .recalc
= &omap2_clksel_recalc
,
627 .round_rate
= &omap2_clksel_round_rate
,
628 .set_rate
= &omap2_clksel_set_rate
,
629 .flags
= CLOCK_IN_OMAP4430
,
632 static const struct clksel iva_hsd_byp_clk_mux_sel
[] = {
633 { .parent
= &dpll_sys_ref_clk
, .rates
= div_1_0_rates
},
634 { .parent
= &div_iva_hs_clk
, .rates
= div_1_1_rates
},
638 static struct clk iva_hsd_byp_clk_mux_ck
= {
639 .name
= "iva_hsd_byp_clk_mux_ck",
640 .parent
= &dpll_sys_ref_clk
,
642 .recalc
= &followparent_recalc
,
643 .flags
= CLOCK_IN_OMAP4430
,
647 static struct dpll_data dpll_iva_dd
= {
648 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_IVA
,
649 .clk_bypass
= &iva_hsd_byp_clk_mux_ck
,
650 .clk_ref
= &dpll_sys_ref_clk
,
651 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_IVA
,
652 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
653 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_IVA
,
654 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_IVA
,
655 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
656 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
657 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
658 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
659 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
660 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
661 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
666 static struct clk dpll_iva_ck
= {
667 .name
= "dpll_iva_ck",
668 .parent
= &dpll_sys_ref_clk
,
669 .dpll_data
= &dpll_iva_dd
,
670 .init
= &omap2_init_dpll_parent
,
671 .ops
= &clkops_noncore_dpll_ops
,
672 .recalc
= &omap3_dpll_recalc
,
673 .round_rate
= &omap2_dpll_round_rate
,
674 .set_rate
= &omap3_noncore_dpll_set_rate
,
675 .flags
= CLOCK_IN_OMAP4430
,
678 static const struct clksel dpll_iva_m4_div
[] = {
679 { .parent
= &dpll_iva_ck
, .rates
= div31_1to31_rates
},
683 static struct clk dpll_iva_m4_ck
= {
684 .name
= "dpll_iva_m4_ck",
685 .parent
= &dpll_iva_ck
,
686 .clksel
= dpll_iva_m4_div
,
687 .clksel_reg
= OMAP4430_CM_DIV_M4_DPLL_IVA
,
688 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
,
690 .recalc
= &omap2_clksel_recalc
,
691 .round_rate
= &omap2_clksel_round_rate
,
692 .set_rate
= &omap2_clksel_set_rate
,
693 .flags
= CLOCK_IN_OMAP4430
,
696 static struct clk dpll_iva_m5_ck
= {
697 .name
= "dpll_iva_m5_ck",
698 .parent
= &dpll_iva_ck
,
699 .clksel
= dpll_iva_m4_div
,
700 .clksel_reg
= OMAP4430_CM_DIV_M5_DPLL_IVA
,
701 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
,
703 .recalc
= &omap2_clksel_recalc
,
704 .round_rate
= &omap2_clksel_round_rate
,
705 .set_rate
= &omap2_clksel_set_rate
,
706 .flags
= CLOCK_IN_OMAP4430
,
710 static struct dpll_data dpll_mpu_dd
= {
711 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_MPU
,
712 .clk_bypass
= &div_mpu_hs_clk
,
713 .clk_ref
= &dpll_sys_ref_clk
,
714 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_MPU
,
715 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
716 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_MPU
,
717 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_MPU
,
718 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
719 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
720 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
721 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
722 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
723 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
724 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
729 static struct clk dpll_mpu_ck
= {
730 .name
= "dpll_mpu_ck",
731 .parent
= &dpll_sys_ref_clk
,
732 .dpll_data
= &dpll_mpu_dd
,
733 .init
= &omap2_init_dpll_parent
,
734 .ops
= &clkops_noncore_dpll_ops
,
735 .recalc
= &omap3_dpll_recalc
,
736 .round_rate
= &omap2_dpll_round_rate
,
737 .set_rate
= &omap3_noncore_dpll_set_rate
,
738 .flags
= CLOCK_IN_OMAP4430
,
741 static const struct clksel dpll_mpu_m2_div
[] = {
742 { .parent
= &dpll_mpu_ck
, .rates
= div31_1to31_rates
},
746 static struct clk dpll_mpu_m2_ck
= {
747 .name
= "dpll_mpu_m2_ck",
748 .parent
= &dpll_mpu_ck
,
749 .clksel
= dpll_mpu_m2_div
,
750 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_MPU
,
751 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
753 .recalc
= &omap2_clksel_recalc
,
754 .round_rate
= &omap2_clksel_round_rate
,
755 .set_rate
= &omap2_clksel_set_rate
,
756 .flags
= CLOCK_IN_OMAP4430
,
759 static struct clk per_hs_clk_div_ck
= {
760 .name
= "per_hs_clk_div_ck",
761 .parent
= &dpll_abe_m3_ck
,
763 .recalc
= &followparent_recalc
,
764 .flags
= CLOCK_IN_OMAP4430
,
767 static const struct clksel per_hsd_byp_clk_mux_sel
[] = {
768 { .parent
= &dpll_sys_ref_clk
, .rates
= div_1_0_rates
},
769 { .parent
= &per_hs_clk_div_ck
, .rates
= div_1_1_rates
},
773 static struct clk per_hsd_byp_clk_mux_ck
= {
774 .name
= "per_hsd_byp_clk_mux_ck",
775 .parent
= &dpll_sys_ref_clk
,
776 .clksel
= per_hsd_byp_clk_mux_sel
,
777 .init
= &omap2_init_clksel_parent
,
778 .clksel_reg
= OMAP4430_CM_CLKSEL_DPLL_PER
,
779 .clksel_mask
= OMAP4430_DPLL_BYP_CLKSEL_MASK
,
781 .recalc
= &omap2_clksel_recalc
,
782 .flags
= CLOCK_IN_OMAP4430
,
786 static struct dpll_data dpll_per_dd
= {
787 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_PER
,
788 .clk_bypass
= &per_hsd_byp_clk_mux_ck
,
789 .clk_ref
= &dpll_sys_ref_clk
,
790 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_PER
,
791 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
792 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_PER
,
793 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_PER
,
794 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
795 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
796 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
797 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
798 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
799 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
800 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
805 static struct clk dpll_per_ck
= {
806 .name
= "dpll_per_ck",
807 .parent
= &dpll_sys_ref_clk
,
808 .dpll_data
= &dpll_per_dd
,
809 .init
= &omap2_init_dpll_parent
,
810 .ops
= &clkops_noncore_dpll_ops
,
811 .recalc
= &omap3_dpll_recalc
,
812 .round_rate
= &omap2_dpll_round_rate
,
813 .set_rate
= &omap3_noncore_dpll_set_rate
,
814 .flags
= CLOCK_IN_OMAP4430
,
817 static const struct clksel dpll_per_m2_div
[] = {
818 { .parent
= &dpll_per_ck
, .rates
= div31_1to31_rates
},
822 static struct clk dpll_per_m2_ck
= {
823 .name
= "dpll_per_m2_ck",
824 .parent
= &dpll_per_ck
,
825 .clksel
= dpll_per_m2_div
,
826 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_PER
,
827 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
829 .recalc
= &omap2_clksel_recalc
,
830 .round_rate
= &omap2_clksel_round_rate
,
831 .set_rate
= &omap2_clksel_set_rate
,
832 .flags
= CLOCK_IN_OMAP4430
,
835 static struct clk dpll_per_m2x2_ck
= {
836 .name
= "dpll_per_m2x2_ck",
837 .parent
= &dpll_per_ck
,
839 .recalc
= &followparent_recalc
,
840 .flags
= CLOCK_IN_OMAP4430
,
843 static struct clk dpll_per_m3_ck
= {
844 .name
= "dpll_per_m3_ck",
845 .parent
= &dpll_per_ck
,
846 .clksel
= dpll_per_m2_div
,
847 .clksel_reg
= OMAP4430_CM_DIV_M3_DPLL_PER
,
848 .clksel_mask
= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
,
850 .recalc
= &omap2_clksel_recalc
,
851 .round_rate
= &omap2_clksel_round_rate
,
852 .set_rate
= &omap2_clksel_set_rate
,
853 .flags
= CLOCK_IN_OMAP4430
,
856 static struct clk dpll_per_m4_ck
= {
857 .name
= "dpll_per_m4_ck",
858 .parent
= &dpll_per_ck
,
859 .clksel
= dpll_per_m2_div
,
860 .clksel_reg
= OMAP4430_CM_DIV_M4_DPLL_PER
,
861 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
,
863 .recalc
= &omap2_clksel_recalc
,
864 .round_rate
= &omap2_clksel_round_rate
,
865 .set_rate
= &omap2_clksel_set_rate
,
866 .flags
= CLOCK_IN_OMAP4430
,
869 static struct clk dpll_per_m5_ck
= {
870 .name
= "dpll_per_m5_ck",
871 .parent
= &dpll_per_ck
,
872 .clksel
= dpll_per_m2_div
,
873 .clksel_reg
= OMAP4430_CM_DIV_M5_DPLL_PER
,
874 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
,
876 .recalc
= &omap2_clksel_recalc
,
877 .round_rate
= &omap2_clksel_round_rate
,
878 .set_rate
= &omap2_clksel_set_rate
,
879 .flags
= CLOCK_IN_OMAP4430
,
882 static struct clk dpll_per_m6_ck
= {
883 .name
= "dpll_per_m6_ck",
884 .parent
= &dpll_per_ck
,
885 .clksel
= dpll_per_m2_div
,
886 .clksel_reg
= OMAP4430_CM_DIV_M6_DPLL_PER
,
887 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK
,
889 .recalc
= &omap2_clksel_recalc
,
890 .round_rate
= &omap2_clksel_round_rate
,
891 .set_rate
= &omap2_clksel_set_rate
,
892 .flags
= CLOCK_IN_OMAP4430
,
895 static struct clk dpll_per_m7_ck
= {
896 .name
= "dpll_per_m7_ck",
897 .parent
= &dpll_per_ck
,
898 .clksel
= dpll_per_m2_div
,
899 .clksel_reg
= OMAP4430_CM_DIV_M7_DPLL_PER
,
900 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK
,
902 .recalc
= &omap2_clksel_recalc
,
903 .round_rate
= &omap2_clksel_round_rate
,
904 .set_rate
= &omap2_clksel_set_rate
,
905 .flags
= CLOCK_IN_OMAP4430
,
909 static struct dpll_data dpll_unipro_dd
= {
910 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_UNIPRO
,
911 .clk_bypass
= &dpll_sys_ref_clk
,
912 .clk_ref
= &dpll_sys_ref_clk
,
913 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_UNIPRO
,
914 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
915 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO
,
916 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_UNIPRO
,
917 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
918 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
919 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
920 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
921 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
922 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
923 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
928 static struct clk dpll_unipro_ck
= {
929 .name
= "dpll_unipro_ck",
930 .parent
= &dpll_sys_ref_clk
,
931 .dpll_data
= &dpll_unipro_dd
,
932 .init
= &omap2_init_dpll_parent
,
933 .ops
= &clkops_noncore_dpll_ops
,
934 .recalc
= &omap3_dpll_recalc
,
935 .round_rate
= &omap2_dpll_round_rate
,
936 .set_rate
= &omap3_noncore_dpll_set_rate
,
937 .flags
= CLOCK_IN_OMAP4430
,
940 static const struct clksel dpll_unipro_m2x2_div
[] = {
941 { .parent
= &dpll_unipro_ck
, .rates
= div31_1to31_rates
},
945 static struct clk dpll_unipro_m2x2_ck
= {
946 .name
= "dpll_unipro_m2x2_ck",
947 .parent
= &dpll_unipro_ck
,
948 .clksel
= dpll_unipro_m2x2_div
,
949 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_UNIPRO
,
950 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
952 .recalc
= &omap2_clksel_recalc
,
953 .round_rate
= &omap2_clksel_round_rate
,
954 .set_rate
= &omap2_clksel_set_rate
,
955 .flags
= CLOCK_IN_OMAP4430
,
958 static struct clk usb_hs_clk_div_ck
= {
959 .name
= "usb_hs_clk_div_ck",
960 .parent
= &dpll_abe_m3_ck
,
962 .recalc
= &followparent_recalc
,
963 .flags
= CLOCK_IN_OMAP4430
,
967 static struct dpll_data dpll_usb_dd
= {
968 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_USB
,
969 .clk_bypass
= &usb_hs_clk_div_ck
,
970 .clk_ref
= &dpll_sys_ref_clk
,
971 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_USB
,
972 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
973 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_USB
,
974 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_USB
,
975 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
976 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
977 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
978 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
979 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
980 .max_multiplier
= OMAP4430_MAX_DPLL_MULT
,
981 .max_divider
= OMAP4430_MAX_DPLL_DIV
,
986 static struct clk dpll_usb_ck
= {
987 .name
= "dpll_usb_ck",
988 .parent
= &dpll_sys_ref_clk
,
989 .dpll_data
= &dpll_usb_dd
,
990 .init
= &omap2_init_dpll_parent
,
991 .ops
= &clkops_noncore_dpll_ops
,
992 .recalc
= &omap3_dpll_recalc
,
993 .round_rate
= &omap2_dpll_round_rate
,
994 .set_rate
= &omap3_noncore_dpll_set_rate
,
995 .flags
= CLOCK_IN_OMAP4430
,
998 static struct clk dpll_usb_clkdcoldo_ck
= {
999 .name
= "dpll_usb_clkdcoldo_ck",
1000 .parent
= &dpll_usb_ck
,
1001 .ops
= &clkops_null
,
1002 .recalc
= &followparent_recalc
,
1003 .flags
= CLOCK_IN_OMAP4430
,
1006 static const struct clksel dpll_usb_m2_div
[] = {
1007 { .parent
= &dpll_usb_ck
, .rates
= div31_1to31_rates
},
1011 static struct clk dpll_usb_m2_ck
= {
1012 .name
= "dpll_usb_m2_ck",
1013 .parent
= &dpll_usb_ck
,
1014 .clksel
= dpll_usb_m2_div
,
1015 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_USB
,
1016 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK
,
1017 .ops
= &clkops_null
,
1018 .recalc
= &omap2_clksel_recalc
,
1019 .round_rate
= &omap2_clksel_round_rate
,
1020 .set_rate
= &omap2_clksel_set_rate
,
1021 .flags
= CLOCK_IN_OMAP4430
,
1024 static const struct clksel ducati_clk_mux_sel
[] = {
1025 { .parent
= &div_core_ck
, .rates
= div_1_0_rates
},
1026 { .parent
= &dpll_per_m6_ck
, .rates
= div_1_1_rates
},
1030 static struct clk ducati_clk_mux_ck
= {
1031 .name
= "ducati_clk_mux_ck",
1032 .parent
= &div_core_ck
,
1033 .clksel
= ducati_clk_mux_sel
,
1034 .init
= &omap2_init_clksel_parent
,
1035 .clksel_reg
= OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT
,
1036 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1037 .ops
= &clkops_null
,
1038 .recalc
= &omap2_clksel_recalc
,
1039 .flags
= CLOCK_IN_OMAP4430
,
1042 static struct clk func_12m_fclk
= {
1043 .name
= "func_12m_fclk",
1044 .parent
= &dpll_per_m2x2_ck
,
1045 .ops
= &clkops_null
,
1046 .recalc
= &followparent_recalc
,
1047 .flags
= CLOCK_IN_OMAP4430
,
1050 static struct clk func_24m_clk
= {
1051 .name
= "func_24m_clk",
1052 .parent
= &dpll_per_m2_ck
,
1053 .ops
= &clkops_null
,
1054 .recalc
= &followparent_recalc
,
1055 .flags
= CLOCK_IN_OMAP4430
,
1058 static struct clk func_24mc_fclk
= {
1059 .name
= "func_24mc_fclk",
1060 .parent
= &dpll_per_m2x2_ck
,
1061 .ops
= &clkops_null
,
1062 .recalc
= &followparent_recalc
,
1063 .flags
= CLOCK_IN_OMAP4430
,
1066 static const struct clksel_rate div2_4to8_rates
[] = {
1067 { .div
= 4, .val
= 0, .flags
= RATE_IN_4430
},
1068 { .div
= 8, .val
= 1, .flags
= RATE_IN_4430
},
1072 static const struct clksel func_48m_fclk_div
[] = {
1073 { .parent
= &dpll_per_m2x2_ck
, .rates
= div2_4to8_rates
},
1077 static struct clk func_48m_fclk
= {
1078 .name
= "func_48m_fclk",
1079 .parent
= &dpll_per_m2x2_ck
,
1080 .clksel
= func_48m_fclk_div
,
1081 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1082 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1083 .ops
= &clkops_null
,
1084 .recalc
= &omap2_clksel_recalc
,
1085 .round_rate
= &omap2_clksel_round_rate
,
1086 .set_rate
= &omap2_clksel_set_rate
,
1087 .flags
= CLOCK_IN_OMAP4430
,
1090 static struct clk func_48mc_fclk
= {
1091 .name
= "func_48mc_fclk",
1092 .parent
= &dpll_per_m2x2_ck
,
1093 .ops
= &clkops_null
,
1094 .recalc
= &followparent_recalc
,
1095 .flags
= CLOCK_IN_OMAP4430
,
1098 static const struct clksel_rate div2_2to4_rates
[] = {
1099 { .div
= 2, .val
= 0, .flags
= RATE_IN_4430
},
1100 { .div
= 4, .val
= 1, .flags
= RATE_IN_4430
},
1104 static const struct clksel func_64m_fclk_div
[] = {
1105 { .parent
= &dpll_per_m4_ck
, .rates
= div2_2to4_rates
},
1109 static struct clk func_64m_fclk
= {
1110 .name
= "func_64m_fclk",
1111 .parent
= &dpll_per_m4_ck
,
1112 .clksel
= func_64m_fclk_div
,
1113 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1114 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1115 .ops
= &clkops_null
,
1116 .recalc
= &omap2_clksel_recalc
,
1117 .round_rate
= &omap2_clksel_round_rate
,
1118 .set_rate
= &omap2_clksel_set_rate
,
1119 .flags
= CLOCK_IN_OMAP4430
,
1122 static const struct clksel func_96m_fclk_div
[] = {
1123 { .parent
= &dpll_per_m2x2_ck
, .rates
= div2_2to4_rates
},
1127 static struct clk func_96m_fclk
= {
1128 .name
= "func_96m_fclk",
1129 .parent
= &dpll_per_m2x2_ck
,
1130 .clksel
= func_96m_fclk_div
,
1131 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1132 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1133 .ops
= &clkops_null
,
1134 .recalc
= &omap2_clksel_recalc
,
1135 .round_rate
= &omap2_clksel_round_rate
,
1136 .set_rate
= &omap2_clksel_set_rate
,
1137 .flags
= CLOCK_IN_OMAP4430
,
1140 static const struct clksel hsmmc6_fclk_sel
[] = {
1141 { .parent
= &func_64m_fclk
, .rates
= div_1_0_rates
},
1142 { .parent
= &func_96m_fclk
, .rates
= div_1_1_rates
},
1146 static struct clk hsmmc6_fclk
= {
1147 .name
= "hsmmc6_fclk",
1148 .parent
= &func_64m_fclk
,
1149 .ops
= &clkops_null
,
1150 .recalc
= &followparent_recalc
,
1151 .flags
= CLOCK_IN_OMAP4430
,
1154 static const struct clksel_rate div2_1to8_rates
[] = {
1155 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
1156 { .div
= 8, .val
= 1, .flags
= RATE_IN_4430
},
1160 static const struct clksel init_60m_fclk_div
[] = {
1161 { .parent
= &dpll_usb_m2_ck
, .rates
= div2_1to8_rates
},
1165 static struct clk init_60m_fclk
= {
1166 .name
= "init_60m_fclk",
1167 .parent
= &dpll_usb_m2_ck
,
1168 .clksel
= init_60m_fclk_div
,
1169 .clksel_reg
= OMAP4430_CM_CLKSEL_USB_60MHZ
,
1170 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1171 .ops
= &clkops_null
,
1172 .recalc
= &omap2_clksel_recalc
,
1173 .round_rate
= &omap2_clksel_round_rate
,
1174 .set_rate
= &omap2_clksel_set_rate
,
1175 .flags
= CLOCK_IN_OMAP4430
,
1178 static const struct clksel l3_div_div
[] = {
1179 { .parent
= &div_core_ck
, .rates
= div2_1to2_rates
},
1183 static struct clk l3_div_ck
= {
1184 .name
= "l3_div_ck",
1185 .parent
= &div_core_ck
,
1186 .clksel
= l3_div_div
,
1187 .clksel_reg
= OMAP4430_CM_CLKSEL_CORE
,
1188 .clksel_mask
= OMAP4430_CLKSEL_L3_MASK
,
1189 .ops
= &clkops_null
,
1190 .recalc
= &omap2_clksel_recalc
,
1191 .round_rate
= &omap2_clksel_round_rate
,
1192 .set_rate
= &omap2_clksel_set_rate
,
1193 .flags
= CLOCK_IN_OMAP4430
,
1196 static const struct clksel l4_div_div
[] = {
1197 { .parent
= &l3_div_ck
, .rates
= div2_1to2_rates
},
1201 static struct clk l4_div_ck
= {
1202 .name
= "l4_div_ck",
1203 .parent
= &l3_div_ck
,
1204 .clksel
= l4_div_div
,
1205 .clksel_reg
= OMAP4430_CM_CLKSEL_CORE
,
1206 .clksel_mask
= OMAP4430_CLKSEL_L4_MASK
,
1207 .ops
= &clkops_null
,
1208 .recalc
= &omap2_clksel_recalc
,
1209 .round_rate
= &omap2_clksel_round_rate
,
1210 .set_rate
= &omap2_clksel_set_rate
,
1211 .flags
= CLOCK_IN_OMAP4430
,
1214 static struct clk lp_clk_div_ck
= {
1215 .name
= "lp_clk_div_ck",
1216 .parent
= &dpll_abe_m2x2_ck
,
1217 .ops
= &clkops_null
,
1218 .recalc
= &followparent_recalc
,
1219 .flags
= CLOCK_IN_OMAP4430
,
1222 static const struct clksel l4_wkup_clk_mux_sel
[] = {
1223 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
1224 { .parent
= &lp_clk_div_ck
, .rates
= div_1_1_rates
},
1228 static struct clk l4_wkup_clk_mux_ck
= {
1229 .name
= "l4_wkup_clk_mux_ck",
1230 .parent
= &sys_clkin_ck
,
1231 .clksel
= l4_wkup_clk_mux_sel
,
1232 .init
= &omap2_init_clksel_parent
,
1233 .clksel_reg
= OMAP4430_CM_L4_WKUP_CLKSEL
,
1234 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1235 .ops
= &clkops_null
,
1236 .recalc
= &omap2_clksel_recalc
,
1237 .flags
= CLOCK_IN_OMAP4430
,
1240 static const struct clksel per_abe_nc_fclk_div
[] = {
1241 { .parent
= &dpll_abe_m2_ck
, .rates
= div2_1to2_rates
},
1245 static struct clk per_abe_nc_fclk
= {
1246 .name
= "per_abe_nc_fclk",
1247 .parent
= &dpll_abe_m2_ck
,
1248 .clksel
= per_abe_nc_fclk_div
,
1249 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1250 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1251 .ops
= &clkops_null
,
1252 .recalc
= &omap2_clksel_recalc
,
1253 .round_rate
= &omap2_clksel_round_rate
,
1254 .set_rate
= &omap2_clksel_set_rate
,
1255 .flags
= CLOCK_IN_OMAP4430
,
1258 static const struct clksel mcasp2_fclk_sel
[] = {
1259 { .parent
= &func_96m_fclk
, .rates
= div_1_0_rates
},
1260 { .parent
= &per_abe_nc_fclk
, .rates
= div_1_1_rates
},
1264 static struct clk mcasp2_fclk
= {
1265 .name
= "mcasp2_fclk",
1266 .parent
= &func_96m_fclk
,
1267 .ops
= &clkops_null
,
1268 .recalc
= &followparent_recalc
,
1269 .flags
= CLOCK_IN_OMAP4430
,
1272 static struct clk mcasp3_fclk
= {
1273 .name
= "mcasp3_fclk",
1274 .parent
= &func_96m_fclk
,
1275 .ops
= &clkops_null
,
1276 .recalc
= &followparent_recalc
,
1277 .flags
= CLOCK_IN_OMAP4430
,
1280 static struct clk ocp_abe_iclk
= {
1281 .name
= "ocp_abe_iclk",
1282 .parent
= &aess_fclk
,
1283 .ops
= &clkops_null
,
1284 .recalc
= &followparent_recalc
,
1285 .flags
= CLOCK_IN_OMAP4430
,
1288 static struct clk per_abe_24m_fclk
= {
1289 .name
= "per_abe_24m_fclk",
1290 .parent
= &dpll_abe_m2_ck
,
1291 .ops
= &clkops_null
,
1292 .recalc
= &followparent_recalc
,
1293 .flags
= CLOCK_IN_OMAP4430
,
1296 static const struct clksel pmd_stm_clock_mux_sel
[] = {
1297 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
1298 { .parent
= &dpll_core_m6_ck
, .rates
= div_1_1_rates
},
1299 { .parent
= &dpll_per_m7_ck
, .rates
= div_1_2_rates
},
1303 static struct clk pmd_stm_clock_mux_ck
= {
1304 .name
= "pmd_stm_clock_mux_ck",
1305 .parent
= &sys_clkin_ck
,
1306 .ops
= &clkops_null
,
1307 .recalc
= &followparent_recalc
,
1308 .flags
= CLOCK_IN_OMAP4430
,
1311 static struct clk pmd_trace_clk_mux_ck
= {
1312 .name
= "pmd_trace_clk_mux_ck",
1313 .parent
= &sys_clkin_ck
,
1314 .ops
= &clkops_null
,
1315 .recalc
= &followparent_recalc
,
1316 .flags
= CLOCK_IN_OMAP4430
,
1319 static struct clk syc_clk_div_ck
= {
1320 .name
= "syc_clk_div_ck",
1321 .parent
= &sys_clkin_ck
,
1322 .clksel
= dpll_sys_ref_clk_div
,
1323 .clksel_reg
= OMAP4430_CM_ABE_DSS_SYS_CLKSEL
,
1324 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1325 .ops
= &clkops_null
,
1326 .recalc
= &omap2_clksel_recalc
,
1327 .round_rate
= &omap2_clksel_round_rate
,
1328 .set_rate
= &omap2_clksel_set_rate
,
1329 .flags
= CLOCK_IN_OMAP4430
,
1332 /* Leaf clocks controlled by modules */
1334 static struct clk aes1_ck
= {
1336 .ops
= &clkops_omap2_dflt
,
1337 .enable_reg
= OMAP4430_CM_L4SEC_AES1_CLKCTRL
,
1338 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1339 .clkdm_name
= "l4_secure_clkdm",
1340 .parent
= &l3_div_ck
,
1341 .recalc
= &followparent_recalc
,
1344 static struct clk aes2_ck
= {
1346 .ops
= &clkops_omap2_dflt
,
1347 .enable_reg
= OMAP4430_CM_L4SEC_AES2_CLKCTRL
,
1348 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1349 .clkdm_name
= "l4_secure_clkdm",
1350 .parent
= &l3_div_ck
,
1351 .recalc
= &followparent_recalc
,
1354 static struct clk aess_ck
= {
1356 .ops
= &clkops_omap2_dflt
,
1357 .enable_reg
= OMAP4430_CM1_ABE_AESS_CLKCTRL
,
1358 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1359 .clkdm_name
= "abe_clkdm",
1360 .parent
= &aess_fclk
,
1361 .recalc
= &followparent_recalc
,
1364 static struct clk cust_efuse_ck
= {
1365 .name
= "cust_efuse_ck",
1366 .ops
= &clkops_omap2_dflt
,
1367 .enable_reg
= OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL
,
1368 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1369 .clkdm_name
= "l4_cefuse_clkdm",
1370 .parent
= &sys_clkin_ck
,
1371 .recalc
= &followparent_recalc
,
1374 static struct clk des3des_ck
= {
1375 .name
= "des3des_ck",
1376 .ops
= &clkops_omap2_dflt
,
1377 .enable_reg
= OMAP4430_CM_L4SEC_DES3DES_CLKCTRL
,
1378 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1379 .clkdm_name
= "l4_secure_clkdm",
1380 .parent
= &l4_div_ck
,
1381 .recalc
= &followparent_recalc
,
1384 static const struct clksel dmic_sync_mux_sel
[] = {
1385 { .parent
= &abe_24m_fclk
, .rates
= div_1_0_rates
},
1386 { .parent
= &syc_clk_div_ck
, .rates
= div_1_1_rates
},
1387 { .parent
= &func_24m_clk
, .rates
= div_1_2_rates
},
1391 static struct clk dmic_sync_mux_ck
= {
1392 .name
= "dmic_sync_mux_ck",
1393 .parent
= &abe_24m_fclk
,
1394 .clksel
= dmic_sync_mux_sel
,
1395 .init
= &omap2_init_clksel_parent
,
1396 .clksel_reg
= OMAP4430_CM1_ABE_DMIC_CLKCTRL
,
1397 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1398 .ops
= &clkops_null
,
1399 .recalc
= &omap2_clksel_recalc
,
1400 .flags
= CLOCK_IN_OMAP4430
,
1403 static const struct clksel func_dmic_abe_gfclk_sel
[] = {
1404 { .parent
= &dmic_sync_mux_ck
, .rates
= div_1_0_rates
},
1405 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1406 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1410 /* Merged func_dmic_abe_gfclk into dmic_ck */
1411 static struct clk dmic_ck
= {
1413 .parent
= &dmic_sync_mux_ck
,
1414 .clksel
= func_dmic_abe_gfclk_sel
,
1415 .init
= &omap2_init_clksel_parent
,
1416 .clksel_reg
= OMAP4430_CM1_ABE_DMIC_CLKCTRL
,
1417 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1418 .ops
= &clkops_omap2_dflt
,
1419 .recalc
= &omap2_clksel_recalc
,
1420 .flags
= CLOCK_IN_OMAP4430
,
1421 .enable_reg
= OMAP4430_CM1_ABE_DMIC_CLKCTRL
,
1422 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1423 .clkdm_name
= "abe_clkdm",
1426 static struct clk dss_ck
= {
1428 .ops
= &clkops_omap2_dflt
,
1429 .enable_reg
= OMAP4430_CM_DSS_DSS_CLKCTRL
,
1430 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1431 .clkdm_name
= "l3_dss_clkdm",
1432 .parent
= &l3_div_ck
,
1433 .recalc
= &followparent_recalc
,
1436 static struct clk ducati_ck
= {
1437 .name
= "ducati_ck",
1438 .ops
= &clkops_omap2_dflt
,
1439 .enable_reg
= OMAP4430_CM_DUCATI_DUCATI_CLKCTRL
,
1440 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1441 .clkdm_name
= "ducati_clkdm",
1442 .parent
= &ducati_clk_mux_ck
,
1443 .recalc
= &followparent_recalc
,
1446 static struct clk emif1_ck
= {
1448 .ops
= &clkops_omap2_dflt
,
1449 .enable_reg
= OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL
,
1450 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1451 .clkdm_name
= "l3_emif_clkdm",
1452 .parent
= &ddrphy_ck
,
1453 .recalc
= &followparent_recalc
,
1456 static struct clk emif2_ck
= {
1458 .ops
= &clkops_omap2_dflt
,
1459 .enable_reg
= OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL
,
1460 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1461 .clkdm_name
= "l3_emif_clkdm",
1462 .parent
= &ddrphy_ck
,
1463 .recalc
= &followparent_recalc
,
1466 static const struct clksel fdif_fclk_div
[] = {
1467 { .parent
= &dpll_per_m4_ck
, .rates
= div3_1to4_rates
},
1471 /* Merged fdif_fclk into fdif_ck */
1472 static struct clk fdif_ck
= {
1474 .parent
= &dpll_per_m4_ck
,
1475 .clksel
= fdif_fclk_div
,
1476 .clksel_reg
= OMAP4430_CM_CAM_FDIF_CLKCTRL
,
1477 .clksel_mask
= OMAP4430_CLKSEL_FCLK_MASK
,
1478 .ops
= &clkops_omap2_dflt
,
1479 .recalc
= &omap2_clksel_recalc
,
1480 .round_rate
= &omap2_clksel_round_rate
,
1481 .set_rate
= &omap2_clksel_set_rate
,
1482 .flags
= CLOCK_IN_OMAP4430
,
1483 .enable_reg
= OMAP4430_CM_CAM_FDIF_CLKCTRL
,
1484 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1485 .clkdm_name
= "iss_clkdm",
1488 static const struct clksel per_sgx_fclk_div
[] = {
1489 { .parent
= &dpll_per_m2x2_ck
, .rates
= div3_1to4_rates
},
1493 static struct clk per_sgx_fclk
= {
1494 .name
= "per_sgx_fclk",
1495 .parent
= &dpll_per_m2x2_ck
,
1496 .clksel
= per_sgx_fclk_div
,
1497 .clksel_reg
= OMAP4430_CM_GFX_GFX_CLKCTRL
,
1498 .clksel_mask
= OMAP4430_CLKSEL_PER_192M_MASK
,
1499 .ops
= &clkops_null
,
1500 .recalc
= &omap2_clksel_recalc
,
1501 .round_rate
= &omap2_clksel_round_rate
,
1502 .set_rate
= &omap2_clksel_set_rate
,
1503 .flags
= CLOCK_IN_OMAP4430
,
1506 static const struct clksel sgx_clk_mux_sel
[] = {
1507 { .parent
= &dpll_core_m7_ck
, .rates
= div_1_0_rates
},
1508 { .parent
= &per_sgx_fclk
, .rates
= div_1_1_rates
},
1512 /* Merged sgx_clk_mux into gfx_ck */
1513 static struct clk gfx_ck
= {
1515 .parent
= &dpll_core_m7_ck
,
1516 .clksel
= sgx_clk_mux_sel
,
1517 .init
= &omap2_init_clksel_parent
,
1518 .clksel_reg
= OMAP4430_CM_GFX_GFX_CLKCTRL
,
1519 .clksel_mask
= OMAP4430_CLKSEL_SGX_FCLK_MASK
,
1520 .ops
= &clkops_omap2_dflt
,
1521 .recalc
= &omap2_clksel_recalc
,
1522 .flags
= CLOCK_IN_OMAP4430
,
1523 .enable_reg
= OMAP4430_CM_GFX_GFX_CLKCTRL
,
1524 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1525 .clkdm_name
= "l3_gfx_clkdm",
1528 static struct clk gpio1_ck
= {
1530 .ops
= &clkops_omap2_dflt
,
1531 .enable_reg
= OMAP4430_CM_WKUP_GPIO1_CLKCTRL
,
1532 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1533 .clkdm_name
= "l4_wkup_clkdm",
1534 .parent
= &l4_wkup_clk_mux_ck
,
1535 .recalc
= &followparent_recalc
,
1538 static struct clk gpio2_ck
= {
1540 .ops
= &clkops_omap2_dflt
,
1541 .enable_reg
= OMAP4430_CM_L4PER_GPIO2_CLKCTRL
,
1542 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1543 .clkdm_name
= "l4_per_clkdm",
1544 .parent
= &l4_div_ck
,
1545 .recalc
= &followparent_recalc
,
1548 static struct clk gpio3_ck
= {
1550 .ops
= &clkops_omap2_dflt
,
1551 .enable_reg
= OMAP4430_CM_L4PER_GPIO3_CLKCTRL
,
1552 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1553 .clkdm_name
= "l4_per_clkdm",
1554 .parent
= &l4_div_ck
,
1555 .recalc
= &followparent_recalc
,
1558 static struct clk gpio4_ck
= {
1560 .ops
= &clkops_omap2_dflt
,
1561 .enable_reg
= OMAP4430_CM_L4PER_GPIO4_CLKCTRL
,
1562 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1563 .clkdm_name
= "l4_per_clkdm",
1564 .parent
= &l4_div_ck
,
1565 .recalc
= &followparent_recalc
,
1568 static struct clk gpio5_ck
= {
1570 .ops
= &clkops_omap2_dflt
,
1571 .enable_reg
= OMAP4430_CM_L4PER_GPIO5_CLKCTRL
,
1572 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1573 .clkdm_name
= "l4_per_clkdm",
1574 .parent
= &l4_div_ck
,
1575 .recalc
= &followparent_recalc
,
1578 static struct clk gpio6_ck
= {
1580 .ops
= &clkops_omap2_dflt
,
1581 .enable_reg
= OMAP4430_CM_L4PER_GPIO6_CLKCTRL
,
1582 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1583 .clkdm_name
= "l4_per_clkdm",
1584 .parent
= &l4_div_ck
,
1585 .recalc
= &followparent_recalc
,
1588 static struct clk gpmc_ck
= {
1590 .ops
= &clkops_omap2_dflt
,
1591 .enable_reg
= OMAP4430_CM_L3_2_GPMC_CLKCTRL
,
1592 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1593 .clkdm_name
= "l3_2_clkdm",
1594 .parent
= &l3_div_ck
,
1595 .recalc
= &followparent_recalc
,
1598 static const struct clksel dmt1_clk_mux_sel
[] = {
1599 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
1600 { .parent
= &sys_32k_ck
, .rates
= div_1_1_rates
},
1604 /* Merged dmt1_clk_mux into gptimer1_ck */
1605 static struct clk gptimer1_ck
= {
1606 .name
= "gptimer1_ck",
1607 .parent
= &sys_clkin_ck
,
1608 .clksel
= dmt1_clk_mux_sel
,
1609 .init
= &omap2_init_clksel_parent
,
1610 .clksel_reg
= OMAP4430_CM_WKUP_TIMER1_CLKCTRL
,
1611 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1612 .ops
= &clkops_omap2_dflt
,
1613 .recalc
= &omap2_clksel_recalc
,
1614 .flags
= CLOCK_IN_OMAP4430
,
1615 .enable_reg
= OMAP4430_CM_WKUP_TIMER1_CLKCTRL
,
1616 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1617 .clkdm_name
= "l4_wkup_clkdm",
1620 /* Merged cm2_dm10_mux into gptimer10_ck */
1621 static struct clk gptimer10_ck
= {
1622 .name
= "gptimer10_ck",
1623 .parent
= &sys_clkin_ck
,
1624 .clksel
= dmt1_clk_mux_sel
,
1625 .init
= &omap2_init_clksel_parent
,
1626 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL
,
1627 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1628 .ops
= &clkops_omap2_dflt
,
1629 .recalc
= &omap2_clksel_recalc
,
1630 .flags
= CLOCK_IN_OMAP4430
,
1631 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL
,
1632 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1633 .clkdm_name
= "l4_per_clkdm",
1636 /* Merged cm2_dm11_mux into gptimer11_ck */
1637 static struct clk gptimer11_ck
= {
1638 .name
= "gptimer11_ck",
1639 .parent
= &sys_clkin_ck
,
1640 .clksel
= dmt1_clk_mux_sel
,
1641 .init
= &omap2_init_clksel_parent
,
1642 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL
,
1643 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1644 .ops
= &clkops_omap2_dflt
,
1645 .recalc
= &omap2_clksel_recalc
,
1646 .flags
= CLOCK_IN_OMAP4430
,
1647 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL
,
1648 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1649 .clkdm_name
= "l4_per_clkdm",
1652 /* Merged cm2_dm2_mux into gptimer2_ck */
1653 static struct clk gptimer2_ck
= {
1654 .name
= "gptimer2_ck",
1655 .parent
= &sys_clkin_ck
,
1656 .clksel
= dmt1_clk_mux_sel
,
1657 .init
= &omap2_init_clksel_parent
,
1658 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL
,
1659 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1660 .ops
= &clkops_omap2_dflt
,
1661 .recalc
= &omap2_clksel_recalc
,
1662 .flags
= CLOCK_IN_OMAP4430
,
1663 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL
,
1664 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1665 .clkdm_name
= "l4_per_clkdm",
1668 /* Merged cm2_dm3_mux into gptimer3_ck */
1669 static struct clk gptimer3_ck
= {
1670 .name
= "gptimer3_ck",
1671 .parent
= &sys_clkin_ck
,
1672 .clksel
= dmt1_clk_mux_sel
,
1673 .init
= &omap2_init_clksel_parent
,
1674 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL
,
1675 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1676 .ops
= &clkops_omap2_dflt
,
1677 .recalc
= &omap2_clksel_recalc
,
1678 .flags
= CLOCK_IN_OMAP4430
,
1679 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL
,
1680 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1681 .clkdm_name
= "l4_per_clkdm",
1684 /* Merged cm2_dm4_mux into gptimer4_ck */
1685 static struct clk gptimer4_ck
= {
1686 .name
= "gptimer4_ck",
1687 .parent
= &sys_clkin_ck
,
1688 .clksel
= dmt1_clk_mux_sel
,
1689 .init
= &omap2_init_clksel_parent
,
1690 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL
,
1691 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1692 .ops
= &clkops_omap2_dflt
,
1693 .recalc
= &omap2_clksel_recalc
,
1694 .flags
= CLOCK_IN_OMAP4430
,
1695 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL
,
1696 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1697 .clkdm_name
= "l4_per_clkdm",
1700 static const struct clksel timer5_sync_mux_sel
[] = {
1701 { .parent
= &syc_clk_div_ck
, .rates
= div_1_0_rates
},
1702 { .parent
= &sys_32k_ck
, .rates
= div_1_1_rates
},
1706 /* Merged timer5_sync_mux into gptimer5_ck */
1707 static struct clk gptimer5_ck
= {
1708 .name
= "gptimer5_ck",
1709 .parent
= &syc_clk_div_ck
,
1710 .clksel
= timer5_sync_mux_sel
,
1711 .init
= &omap2_init_clksel_parent
,
1712 .clksel_reg
= OMAP4430_CM1_ABE_TIMER5_CLKCTRL
,
1713 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1714 .ops
= &clkops_omap2_dflt
,
1715 .recalc
= &omap2_clksel_recalc
,
1716 .flags
= CLOCK_IN_OMAP4430
,
1717 .enable_reg
= OMAP4430_CM1_ABE_TIMER5_CLKCTRL
,
1718 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1719 .clkdm_name
= "abe_clkdm",
1722 /* Merged timer6_sync_mux into gptimer6_ck */
1723 static struct clk gptimer6_ck
= {
1724 .name
= "gptimer6_ck",
1725 .parent
= &syc_clk_div_ck
,
1726 .clksel
= timer5_sync_mux_sel
,
1727 .init
= &omap2_init_clksel_parent
,
1728 .clksel_reg
= OMAP4430_CM1_ABE_TIMER6_CLKCTRL
,
1729 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1730 .ops
= &clkops_omap2_dflt
,
1731 .recalc
= &omap2_clksel_recalc
,
1732 .flags
= CLOCK_IN_OMAP4430
,
1733 .enable_reg
= OMAP4430_CM1_ABE_TIMER6_CLKCTRL
,
1734 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1735 .clkdm_name
= "abe_clkdm",
1738 /* Merged timer7_sync_mux into gptimer7_ck */
1739 static struct clk gptimer7_ck
= {
1740 .name
= "gptimer7_ck",
1741 .parent
= &syc_clk_div_ck
,
1742 .clksel
= timer5_sync_mux_sel
,
1743 .init
= &omap2_init_clksel_parent
,
1744 .clksel_reg
= OMAP4430_CM1_ABE_TIMER7_CLKCTRL
,
1745 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1746 .ops
= &clkops_omap2_dflt
,
1747 .recalc
= &omap2_clksel_recalc
,
1748 .flags
= CLOCK_IN_OMAP4430
,
1749 .enable_reg
= OMAP4430_CM1_ABE_TIMER7_CLKCTRL
,
1750 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1751 .clkdm_name
= "abe_clkdm",
1754 /* Merged timer8_sync_mux into gptimer8_ck */
1755 static struct clk gptimer8_ck
= {
1756 .name
= "gptimer8_ck",
1757 .parent
= &syc_clk_div_ck
,
1758 .clksel
= timer5_sync_mux_sel
,
1759 .init
= &omap2_init_clksel_parent
,
1760 .clksel_reg
= OMAP4430_CM1_ABE_TIMER8_CLKCTRL
,
1761 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1762 .ops
= &clkops_omap2_dflt
,
1763 .recalc
= &omap2_clksel_recalc
,
1764 .flags
= CLOCK_IN_OMAP4430
,
1765 .enable_reg
= OMAP4430_CM1_ABE_TIMER8_CLKCTRL
,
1766 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1767 .clkdm_name
= "abe_clkdm",
1770 /* Merged cm2_dm9_mux into gptimer9_ck */
1771 static struct clk gptimer9_ck
= {
1772 .name
= "gptimer9_ck",
1773 .parent
= &sys_clkin_ck
,
1774 .clksel
= dmt1_clk_mux_sel
,
1775 .init
= &omap2_init_clksel_parent
,
1776 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL
,
1777 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
1778 .ops
= &clkops_omap2_dflt
,
1779 .recalc
= &omap2_clksel_recalc
,
1780 .flags
= CLOCK_IN_OMAP4430
,
1781 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL
,
1782 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1783 .clkdm_name
= "l4_per_clkdm",
1786 static struct clk hdq1w_ck
= {
1788 .ops
= &clkops_omap2_dflt
,
1789 .enable_reg
= OMAP4430_CM_L4PER_HDQ1W_CLKCTRL
,
1790 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1791 .clkdm_name
= "l4_per_clkdm",
1792 .parent
= &func_12m_fclk
,
1793 .recalc
= &followparent_recalc
,
1796 /* Merged hsi_fclk into hsi_ck */
1797 static struct clk hsi_ck
= {
1799 .parent
= &dpll_per_m2x2_ck
,
1800 .clksel
= per_sgx_fclk_div
,
1801 .clksel_reg
= OMAP4430_CM_L3INIT_HSI_CLKCTRL
,
1802 .clksel_mask
= OMAP4430_CLKSEL_24_25_MASK
,
1803 .ops
= &clkops_omap2_dflt
,
1804 .recalc
= &omap2_clksel_recalc
,
1805 .round_rate
= &omap2_clksel_round_rate
,
1806 .set_rate
= &omap2_clksel_set_rate
,
1807 .flags
= CLOCK_IN_OMAP4430
,
1808 .enable_reg
= OMAP4430_CM_L3INIT_HSI_CLKCTRL
,
1809 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1810 .clkdm_name
= "l3_init_clkdm",
1813 static struct clk i2c1_ck
= {
1815 .ops
= &clkops_omap2_dflt
,
1816 .enable_reg
= OMAP4430_CM_L4PER_I2C1_CLKCTRL
,
1817 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1818 .clkdm_name
= "l4_per_clkdm",
1819 .parent
= &func_96m_fclk
,
1820 .recalc
= &followparent_recalc
,
1823 static struct clk i2c2_ck
= {
1825 .ops
= &clkops_omap2_dflt
,
1826 .enable_reg
= OMAP4430_CM_L4PER_I2C2_CLKCTRL
,
1827 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1828 .clkdm_name
= "l4_per_clkdm",
1829 .parent
= &func_96m_fclk
,
1830 .recalc
= &followparent_recalc
,
1833 static struct clk i2c3_ck
= {
1835 .ops
= &clkops_omap2_dflt
,
1836 .enable_reg
= OMAP4430_CM_L4PER_I2C3_CLKCTRL
,
1837 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1838 .clkdm_name
= "l4_per_clkdm",
1839 .parent
= &func_96m_fclk
,
1840 .recalc
= &followparent_recalc
,
1843 static struct clk i2c4_ck
= {
1845 .ops
= &clkops_omap2_dflt
,
1846 .enable_reg
= OMAP4430_CM_L4PER_I2C4_CLKCTRL
,
1847 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1848 .clkdm_name
= "l4_per_clkdm",
1849 .parent
= &func_96m_fclk
,
1850 .recalc
= &followparent_recalc
,
1853 static struct clk iss_ck
= {
1855 .ops
= &clkops_omap2_dflt
,
1856 .enable_reg
= OMAP4430_CM_CAM_ISS_CLKCTRL
,
1857 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1858 .clkdm_name
= "iss_clkdm",
1859 .parent
= &ducati_clk_mux_ck
,
1860 .recalc
= &followparent_recalc
,
1863 static struct clk ivahd_ck
= {
1865 .ops
= &clkops_omap2_dflt
,
1866 .enable_reg
= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL
,
1867 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1868 .clkdm_name
= "ivahd_clkdm",
1869 .parent
= &dpll_iva_m5_ck
,
1870 .recalc
= &followparent_recalc
,
1873 static struct clk keyboard_ck
= {
1874 .name
= "keyboard_ck",
1875 .ops
= &clkops_omap2_dflt
,
1876 .enable_reg
= OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL
,
1877 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1878 .clkdm_name
= "l4_wkup_clkdm",
1879 .parent
= &sys_32k_ck
,
1880 .recalc
= &followparent_recalc
,
1883 static struct clk l3_instr_interconnect_ck
= {
1884 .name
= "l3_instr_interconnect_ck",
1885 .ops
= &clkops_omap2_dflt
,
1886 .enable_reg
= OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL
,
1887 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1888 .clkdm_name
= "l3_instr_clkdm",
1889 .parent
= &l3_div_ck
,
1890 .recalc
= &followparent_recalc
,
1893 static struct clk l3_interconnect_3_ck
= {
1894 .name
= "l3_interconnect_3_ck",
1895 .ops
= &clkops_omap2_dflt
,
1896 .enable_reg
= OMAP4430_CM_L3INSTR_L3_3_CLKCTRL
,
1897 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1898 .clkdm_name
= "l3_instr_clkdm",
1899 .parent
= &l3_div_ck
,
1900 .recalc
= &followparent_recalc
,
1903 static struct clk mcasp_sync_mux_ck
= {
1904 .name
= "mcasp_sync_mux_ck",
1905 .parent
= &abe_24m_fclk
,
1906 .clksel
= dmic_sync_mux_sel
,
1907 .init
= &omap2_init_clksel_parent
,
1908 .clksel_reg
= OMAP4430_CM1_ABE_MCASP_CLKCTRL
,
1909 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1910 .ops
= &clkops_null
,
1911 .recalc
= &omap2_clksel_recalc
,
1912 .flags
= CLOCK_IN_OMAP4430
,
1915 static const struct clksel func_mcasp_abe_gfclk_sel
[] = {
1916 { .parent
= &mcasp_sync_mux_ck
, .rates
= div_1_0_rates
},
1917 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1918 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1922 /* Merged func_mcasp_abe_gfclk into mcasp_ck */
1923 static struct clk mcasp_ck
= {
1925 .parent
= &mcasp_sync_mux_ck
,
1926 .clksel
= func_mcasp_abe_gfclk_sel
,
1927 .init
= &omap2_init_clksel_parent
,
1928 .clksel_reg
= OMAP4430_CM1_ABE_MCASP_CLKCTRL
,
1929 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1930 .ops
= &clkops_omap2_dflt
,
1931 .recalc
= &omap2_clksel_recalc
,
1932 .flags
= CLOCK_IN_OMAP4430
,
1933 .enable_reg
= OMAP4430_CM1_ABE_MCASP_CLKCTRL
,
1934 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1935 .clkdm_name
= "abe_clkdm",
1938 static struct clk mcbsp1_sync_mux_ck
= {
1939 .name
= "mcbsp1_sync_mux_ck",
1940 .parent
= &abe_24m_fclk
,
1941 .clksel
= dmic_sync_mux_sel
,
1942 .init
= &omap2_init_clksel_parent
,
1943 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
,
1944 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1945 .ops
= &clkops_null
,
1946 .recalc
= &omap2_clksel_recalc
,
1947 .flags
= CLOCK_IN_OMAP4430
,
1950 static const struct clksel func_mcbsp1_gfclk_sel
[] = {
1951 { .parent
= &mcbsp1_sync_mux_ck
, .rates
= div_1_0_rates
},
1952 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1953 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1957 /* Merged func_mcbsp1_gfclk into mcbsp1_ck */
1958 static struct clk mcbsp1_ck
= {
1959 .name
= "mcbsp1_ck",
1960 .parent
= &mcbsp1_sync_mux_ck
,
1961 .clksel
= func_mcbsp1_gfclk_sel
,
1962 .init
= &omap2_init_clksel_parent
,
1963 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
,
1964 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1965 .ops
= &clkops_omap2_dflt
,
1966 .recalc
= &omap2_clksel_recalc
,
1967 .flags
= CLOCK_IN_OMAP4430
,
1968 .enable_reg
= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
,
1969 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1970 .clkdm_name
= "abe_clkdm",
1973 static struct clk mcbsp2_sync_mux_ck
= {
1974 .name
= "mcbsp2_sync_mux_ck",
1975 .parent
= &abe_24m_fclk
,
1976 .clksel
= dmic_sync_mux_sel
,
1977 .init
= &omap2_init_clksel_parent
,
1978 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
,
1979 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1980 .ops
= &clkops_null
,
1981 .recalc
= &omap2_clksel_recalc
,
1982 .flags
= CLOCK_IN_OMAP4430
,
1985 static const struct clksel func_mcbsp2_gfclk_sel
[] = {
1986 { .parent
= &mcbsp2_sync_mux_ck
, .rates
= div_1_0_rates
},
1987 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1988 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1992 /* Merged func_mcbsp2_gfclk into mcbsp2_ck */
1993 static struct clk mcbsp2_ck
= {
1994 .name
= "mcbsp2_ck",
1995 .parent
= &mcbsp2_sync_mux_ck
,
1996 .clksel
= func_mcbsp2_gfclk_sel
,
1997 .init
= &omap2_init_clksel_parent
,
1998 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
,
1999 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
2000 .ops
= &clkops_omap2_dflt
,
2001 .recalc
= &omap2_clksel_recalc
,
2002 .flags
= CLOCK_IN_OMAP4430
,
2003 .enable_reg
= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
,
2004 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2005 .clkdm_name
= "abe_clkdm",
2008 static struct clk mcbsp3_sync_mux_ck
= {
2009 .name
= "mcbsp3_sync_mux_ck",
2010 .parent
= &abe_24m_fclk
,
2011 .clksel
= dmic_sync_mux_sel
,
2012 .init
= &omap2_init_clksel_parent
,
2013 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
,
2014 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
2015 .ops
= &clkops_null
,
2016 .recalc
= &omap2_clksel_recalc
,
2017 .flags
= CLOCK_IN_OMAP4430
,
2020 static const struct clksel func_mcbsp3_gfclk_sel
[] = {
2021 { .parent
= &mcbsp3_sync_mux_ck
, .rates
= div_1_0_rates
},
2022 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
2023 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
2027 /* Merged func_mcbsp3_gfclk into mcbsp3_ck */
2028 static struct clk mcbsp3_ck
= {
2029 .name
= "mcbsp3_ck",
2030 .parent
= &mcbsp3_sync_mux_ck
,
2031 .clksel
= func_mcbsp3_gfclk_sel
,
2032 .init
= &omap2_init_clksel_parent
,
2033 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
,
2034 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
2035 .ops
= &clkops_omap2_dflt
,
2036 .recalc
= &omap2_clksel_recalc
,
2037 .flags
= CLOCK_IN_OMAP4430
,
2038 .enable_reg
= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
,
2039 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2040 .clkdm_name
= "abe_clkdm",
2043 static struct clk mcbsp4_sync_mux_ck
= {
2044 .name
= "mcbsp4_sync_mux_ck",
2045 .parent
= &func_96m_fclk
,
2046 .clksel
= mcasp2_fclk_sel
,
2047 .init
= &omap2_init_clksel_parent
,
2048 .clksel_reg
= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
,
2049 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
2050 .ops
= &clkops_null
,
2051 .recalc
= &omap2_clksel_recalc
,
2052 .flags
= CLOCK_IN_OMAP4430
,
2055 static const struct clksel per_mcbsp4_gfclk_sel
[] = {
2056 { .parent
= &mcbsp4_sync_mux_ck
, .rates
= div_1_0_rates
},
2057 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
2061 /* Merged per_mcbsp4_gfclk into mcbsp4_ck */
2062 static struct clk mcbsp4_ck
= {
2063 .name
= "mcbsp4_ck",
2064 .parent
= &mcbsp4_sync_mux_ck
,
2065 .clksel
= per_mcbsp4_gfclk_sel
,
2066 .init
= &omap2_init_clksel_parent
,
2067 .clksel_reg
= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
,
2068 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_24_24_MASK
,
2069 .ops
= &clkops_omap2_dflt
,
2070 .recalc
= &omap2_clksel_recalc
,
2071 .flags
= CLOCK_IN_OMAP4430
,
2072 .enable_reg
= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
,
2073 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2074 .clkdm_name
= "l4_per_clkdm",
2077 static struct clk mcspi1_ck
= {
2078 .name
= "mcspi1_ck",
2079 .ops
= &clkops_omap2_dflt
,
2080 .enable_reg
= OMAP4430_CM_L4PER_MCSPI1_CLKCTRL
,
2081 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2082 .clkdm_name
= "l4_per_clkdm",
2083 .parent
= &func_48m_fclk
,
2084 .recalc
= &followparent_recalc
,
2087 static struct clk mcspi2_ck
= {
2088 .name
= "mcspi2_ck",
2089 .ops
= &clkops_omap2_dflt
,
2090 .enable_reg
= OMAP4430_CM_L4PER_MCSPI2_CLKCTRL
,
2091 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2092 .clkdm_name
= "l4_per_clkdm",
2093 .parent
= &func_48m_fclk
,
2094 .recalc
= &followparent_recalc
,
2097 static struct clk mcspi3_ck
= {
2098 .name
= "mcspi3_ck",
2099 .ops
= &clkops_omap2_dflt
,
2100 .enable_reg
= OMAP4430_CM_L4PER_MCSPI3_CLKCTRL
,
2101 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2102 .clkdm_name
= "l4_per_clkdm",
2103 .parent
= &func_48m_fclk
,
2104 .recalc
= &followparent_recalc
,
2107 static struct clk mcspi4_ck
= {
2108 .name
= "mcspi4_ck",
2109 .ops
= &clkops_omap2_dflt
,
2110 .enable_reg
= OMAP4430_CM_L4PER_MCSPI4_CLKCTRL
,
2111 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2112 .clkdm_name
= "l4_per_clkdm",
2113 .parent
= &func_48m_fclk
,
2114 .recalc
= &followparent_recalc
,
2117 /* Merged hsmmc1_fclk into mmc1_ck */
2118 static struct clk mmc1_ck
= {
2120 .parent
= &func_64m_fclk
,
2121 .clksel
= hsmmc6_fclk_sel
,
2122 .init
= &omap2_init_clksel_parent
,
2123 .clksel_reg
= OMAP4430_CM_L3INIT_MMC1_CLKCTRL
,
2124 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2125 .ops
= &clkops_omap2_dflt
,
2126 .recalc
= &omap2_clksel_recalc
,
2127 .flags
= CLOCK_IN_OMAP4430
,
2128 .enable_reg
= OMAP4430_CM_L3INIT_MMC1_CLKCTRL
,
2129 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2130 .clkdm_name
= "l3_init_clkdm",
2133 /* Merged hsmmc2_fclk into mmc2_ck */
2134 static struct clk mmc2_ck
= {
2136 .parent
= &func_64m_fclk
,
2137 .clksel
= hsmmc6_fclk_sel
,
2138 .init
= &omap2_init_clksel_parent
,
2139 .clksel_reg
= OMAP4430_CM_L3INIT_MMC2_CLKCTRL
,
2140 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2141 .ops
= &clkops_omap2_dflt
,
2142 .recalc
= &omap2_clksel_recalc
,
2143 .flags
= CLOCK_IN_OMAP4430
,
2144 .enable_reg
= OMAP4430_CM_L3INIT_MMC2_CLKCTRL
,
2145 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2146 .clkdm_name
= "l3_init_clkdm",
2149 static struct clk mmc3_ck
= {
2151 .ops
= &clkops_omap2_dflt
,
2152 .enable_reg
= OMAP4430_CM_L4PER_MMCSD3_CLKCTRL
,
2153 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2154 .clkdm_name
= "l4_per_clkdm",
2155 .parent
= &func_48m_fclk
,
2156 .recalc
= &followparent_recalc
,
2159 static struct clk mmc4_ck
= {
2161 .ops
= &clkops_omap2_dflt
,
2162 .enable_reg
= OMAP4430_CM_L4PER_MMCSD4_CLKCTRL
,
2163 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2164 .clkdm_name
= "l4_per_clkdm",
2165 .parent
= &func_48m_fclk
,
2166 .recalc
= &followparent_recalc
,
2169 static struct clk mmc5_ck
= {
2171 .ops
= &clkops_omap2_dflt
,
2172 .enable_reg
= OMAP4430_CM_L4PER_MMCSD5_CLKCTRL
,
2173 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2174 .clkdm_name
= "l4_per_clkdm",
2175 .parent
= &func_48m_fclk
,
2176 .recalc
= &followparent_recalc
,
2179 static struct clk ocp_wp1_ck
= {
2180 .name
= "ocp_wp1_ck",
2181 .ops
= &clkops_omap2_dflt
,
2182 .enable_reg
= OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL
,
2183 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2184 .clkdm_name
= "l3_instr_clkdm",
2185 .parent
= &l3_div_ck
,
2186 .recalc
= &followparent_recalc
,
2189 static struct clk pdm_ck
= {
2191 .ops
= &clkops_omap2_dflt
,
2192 .enable_reg
= OMAP4430_CM1_ABE_PDM_CLKCTRL
,
2193 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2194 .clkdm_name
= "abe_clkdm",
2195 .parent
= &pad_clks_ck
,
2196 .recalc
= &followparent_recalc
,
2199 static struct clk pkaeip29_ck
= {
2200 .name
= "pkaeip29_ck",
2201 .ops
= &clkops_omap2_dflt
,
2202 .enable_reg
= OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL
,
2203 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2204 .clkdm_name
= "l4_secure_clkdm",
2205 .parent
= &l4_div_ck
,
2206 .recalc
= &followparent_recalc
,
2209 static struct clk rng_ck
= {
2211 .ops
= &clkops_omap2_dflt
,
2212 .enable_reg
= OMAP4430_CM_L4SEC_RNG_CLKCTRL
,
2213 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2214 .clkdm_name
= "l4_secure_clkdm",
2215 .parent
= &l4_div_ck
,
2216 .recalc
= &followparent_recalc
,
2219 static struct clk sha2md51_ck
= {
2220 .name
= "sha2md51_ck",
2221 .ops
= &clkops_omap2_dflt
,
2222 .enable_reg
= OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL
,
2223 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2224 .clkdm_name
= "l4_secure_clkdm",
2225 .parent
= &l3_div_ck
,
2226 .recalc
= &followparent_recalc
,
2229 static struct clk sl2_ck
= {
2231 .ops
= &clkops_omap2_dflt
,
2232 .enable_reg
= OMAP4430_CM_IVAHD_SL2_CLKCTRL
,
2233 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2234 .clkdm_name
= "ivahd_clkdm",
2235 .parent
= &dpll_iva_m5_ck
,
2236 .recalc
= &followparent_recalc
,
2239 static struct clk slimbus1_ck
= {
2240 .name
= "slimbus1_ck",
2241 .ops
= &clkops_omap2_dflt
,
2242 .enable_reg
= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
,
2243 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2244 .clkdm_name
= "abe_clkdm",
2245 .parent
= &ocp_abe_iclk
,
2246 .recalc
= &followparent_recalc
,
2249 static struct clk slimbus2_ck
= {
2250 .name
= "slimbus2_ck",
2251 .ops
= &clkops_omap2_dflt
,
2252 .enable_reg
= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL
,
2253 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2254 .clkdm_name
= "l4_per_clkdm",
2255 .parent
= &l4_div_ck
,
2256 .recalc
= &followparent_recalc
,
2259 static struct clk sr_core_ck
= {
2260 .name
= "sr_core_ck",
2261 .ops
= &clkops_omap2_dflt
,
2262 .enable_reg
= OMAP4430_CM_ALWON_SR_CORE_CLKCTRL
,
2263 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2264 .clkdm_name
= "l4_ao_clkdm",
2265 .parent
= &l4_wkup_clk_mux_ck
,
2266 .recalc
= &followparent_recalc
,
2269 static struct clk sr_iva_ck
= {
2270 .name
= "sr_iva_ck",
2271 .ops
= &clkops_omap2_dflt
,
2272 .enable_reg
= OMAP4430_CM_ALWON_SR_IVA_CLKCTRL
,
2273 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2274 .clkdm_name
= "l4_ao_clkdm",
2275 .parent
= &l4_wkup_clk_mux_ck
,
2276 .recalc
= &followparent_recalc
,
2279 static struct clk sr_mpu_ck
= {
2280 .name
= "sr_mpu_ck",
2281 .ops
= &clkops_omap2_dflt
,
2282 .enable_reg
= OMAP4430_CM_ALWON_SR_MPU_CLKCTRL
,
2283 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2284 .clkdm_name
= "l4_ao_clkdm",
2285 .parent
= &l4_wkup_clk_mux_ck
,
2286 .recalc
= &followparent_recalc
,
2289 static struct clk tesla_ck
= {
2291 .ops
= &clkops_omap2_dflt
,
2292 .enable_reg
= OMAP4430_CM_TESLA_TESLA_CLKCTRL
,
2293 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2294 .clkdm_name
= "tesla_clkdm",
2295 .parent
= &dpll_iva_m4_ck
,
2296 .recalc
= &followparent_recalc
,
2299 static struct clk uart1_ck
= {
2301 .ops
= &clkops_omap2_dflt
,
2302 .enable_reg
= OMAP4430_CM_L4PER_UART1_CLKCTRL
,
2303 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2304 .clkdm_name
= "l4_per_clkdm",
2305 .parent
= &func_48m_fclk
,
2306 .recalc
= &followparent_recalc
,
2309 static struct clk uart2_ck
= {
2311 .ops
= &clkops_omap2_dflt
,
2312 .enable_reg
= OMAP4430_CM_L4PER_UART2_CLKCTRL
,
2313 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2314 .clkdm_name
= "l4_per_clkdm",
2315 .parent
= &func_48m_fclk
,
2316 .recalc
= &followparent_recalc
,
2319 static struct clk uart3_ck
= {
2321 .ops
= &clkops_omap2_dflt
,
2322 .enable_reg
= OMAP4430_CM_L4PER_UART3_CLKCTRL
,
2323 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2324 .clkdm_name
= "l4_per_clkdm",
2325 .parent
= &func_48m_fclk
,
2326 .recalc
= &followparent_recalc
,
2329 static struct clk uart4_ck
= {
2331 .ops
= &clkops_omap2_dflt
,
2332 .enable_reg
= OMAP4430_CM_L4PER_UART4_CLKCTRL
,
2333 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2334 .clkdm_name
= "l4_per_clkdm",
2335 .parent
= &func_48m_fclk
,
2336 .recalc
= &followparent_recalc
,
2339 static struct clk unipro1_ck
= {
2340 .name
= "unipro1_ck",
2341 .ops
= &clkops_omap2_dflt
,
2342 .enable_reg
= OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL
,
2343 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2344 .clkdm_name
= "l3_init_clkdm",
2345 .parent
= &func_96m_fclk
,
2346 .recalc
= &followparent_recalc
,
2349 static struct clk usb_host_ck
= {
2350 .name
= "usb_host_ck",
2351 .ops
= &clkops_omap2_dflt
,
2352 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2353 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2354 .clkdm_name
= "l3_init_clkdm",
2355 .parent
= &init_60m_fclk
,
2356 .recalc
= &followparent_recalc
,
2359 static struct clk usb_host_fs_ck
= {
2360 .name
= "usb_host_fs_ck",
2361 .ops
= &clkops_omap2_dflt
,
2362 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL
,
2363 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2364 .clkdm_name
= "l3_init_clkdm",
2365 .parent
= &func_48mc_fclk
,
2366 .recalc
= &followparent_recalc
,
2369 static struct clk usb_otg_ck
= {
2370 .name
= "usb_otg_ck",
2371 .ops
= &clkops_omap2_dflt
,
2372 .enable_reg
= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL
,
2373 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2374 .clkdm_name
= "l3_init_clkdm",
2375 .parent
= &l3_div_ck
,
2376 .recalc
= &followparent_recalc
,
2379 static struct clk usb_tll_ck
= {
2380 .name
= "usb_tll_ck",
2381 .ops
= &clkops_omap2_dflt
,
2382 .enable_reg
= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL
,
2383 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2384 .clkdm_name
= "l3_init_clkdm",
2385 .parent
= &l4_div_ck
,
2386 .recalc
= &followparent_recalc
,
2389 static struct clk usbphyocp2scp_ck
= {
2390 .name
= "usbphyocp2scp_ck",
2391 .ops
= &clkops_omap2_dflt
,
2392 .enable_reg
= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL
,
2393 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2394 .clkdm_name
= "l3_init_clkdm",
2395 .parent
= &l4_div_ck
,
2396 .recalc
= &followparent_recalc
,
2399 static struct clk usim_ck
= {
2401 .ops
= &clkops_omap2_dflt
,
2402 .enable_reg
= OMAP4430_CM_WKUP_USIM_CLKCTRL
,
2403 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2404 .clkdm_name
= "l4_wkup_clkdm",
2405 .parent
= &sys_32k_ck
,
2406 .recalc
= &followparent_recalc
,
2409 static struct clk wdt2_ck
= {
2411 .ops
= &clkops_omap2_dflt
,
2412 .enable_reg
= OMAP4430_CM_WKUP_WDT2_CLKCTRL
,
2413 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2414 .clkdm_name
= "l4_wkup_clkdm",
2415 .parent
= &sys_32k_ck
,
2416 .recalc
= &followparent_recalc
,
2419 static struct clk wdt3_ck
= {
2421 .ops
= &clkops_omap2_dflt
,
2422 .enable_reg
= OMAP4430_CM1_ABE_WDT3_CLKCTRL
,
2423 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2424 .clkdm_name
= "abe_clkdm",
2425 .parent
= &sys_32k_ck
,
2426 .recalc
= &followparent_recalc
,
2429 /* Remaining optional clocks */
2430 static const struct clksel otg_60m_gfclk_sel
[] = {
2431 { .parent
= &utmi_phy_clkout_ck
, .rates
= div_1_0_rates
},
2432 { .parent
= &xclk60motg_ck
, .rates
= div_1_1_rates
},
2436 static struct clk otg_60m_gfclk_ck
= {
2437 .name
= "otg_60m_gfclk_ck",
2438 .parent
= &utmi_phy_clkout_ck
,
2439 .clksel
= otg_60m_gfclk_sel
,
2440 .init
= &omap2_init_clksel_parent
,
2441 .clksel_reg
= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL
,
2442 .clksel_mask
= OMAP4430_CLKSEL_60M_MASK
,
2443 .ops
= &clkops_null
,
2444 .recalc
= &omap2_clksel_recalc
,
2445 .flags
= CLOCK_IN_OMAP4430
,
2448 static const struct clksel stm_clk_div_div
[] = {
2449 { .parent
= &pmd_stm_clock_mux_ck
, .rates
= div3_1to4_rates
},
2453 static struct clk stm_clk_div_ck
= {
2454 .name
= "stm_clk_div_ck",
2455 .parent
= &pmd_stm_clock_mux_ck
,
2456 .clksel
= stm_clk_div_div
,
2457 .clksel_reg
= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL
,
2458 .clksel_mask
= OMAP4430_CLKSEL_PMD_STM_CLK_MASK
,
2459 .ops
= &clkops_null
,
2460 .recalc
= &omap2_clksel_recalc
,
2461 .round_rate
= &omap2_clksel_round_rate
,
2462 .set_rate
= &omap2_clksel_set_rate
,
2463 .flags
= CLOCK_IN_OMAP4430
,
2466 static const struct clksel trace_clk_div_div
[] = {
2467 { .parent
= &pmd_trace_clk_mux_ck
, .rates
= div3_1to4_rates
},
2471 static struct clk trace_clk_div_ck
= {
2472 .name
= "trace_clk_div_ck",
2473 .parent
= &pmd_trace_clk_mux_ck
,
2474 .clksel
= trace_clk_div_div
,
2475 .clksel_reg
= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL
,
2476 .clksel_mask
= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK
,
2477 .ops
= &clkops_null
,
2478 .recalc
= &omap2_clksel_recalc
,
2479 .round_rate
= &omap2_clksel_round_rate
,
2480 .set_rate
= &omap2_clksel_set_rate
,
2481 .flags
= CLOCK_IN_OMAP4430
,
2484 static const struct clksel_rate div2_14to18_rates
[] = {
2485 { .div
= 14, .val
= 0, .flags
= RATE_IN_4430
},
2486 { .div
= 18, .val
= 1, .flags
= RATE_IN_4430
},
2490 static const struct clksel usim_fclk_div
[] = {
2491 { .parent
= &dpll_per_m4_ck
, .rates
= div2_14to18_rates
},
2495 static struct clk usim_fclk
= {
2496 .name
= "usim_fclk",
2497 .parent
= &dpll_per_m4_ck
,
2498 .clksel
= usim_fclk_div
,
2499 .clksel_reg
= OMAP4430_CM_WKUP_USIM_CLKCTRL
,
2500 .clksel_mask
= OMAP4430_CLKSEL_DIV_MASK
,
2501 .ops
= &clkops_null
,
2502 .recalc
= &omap2_clksel_recalc
,
2503 .round_rate
= &omap2_clksel_round_rate
,
2504 .set_rate
= &omap2_clksel_set_rate
,
2505 .flags
= CLOCK_IN_OMAP4430
,
2508 static const struct clksel utmi_p1_gfclk_sel
[] = {
2509 { .parent
= &init_60m_fclk
, .rates
= div_1_0_rates
},
2510 { .parent
= &xclk60mhsp1_ck
, .rates
= div_1_1_rates
},
2514 static struct clk utmi_p1_gfclk_ck
= {
2515 .name
= "utmi_p1_gfclk_ck",
2516 .parent
= &init_60m_fclk
,
2517 .clksel
= utmi_p1_gfclk_sel
,
2518 .init
= &omap2_init_clksel_parent
,
2519 .clksel_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2520 .clksel_mask
= OMAP4430_CLKSEL_UTMI_P1_MASK
,
2521 .ops
= &clkops_null
,
2522 .recalc
= &omap2_clksel_recalc
,
2523 .flags
= CLOCK_IN_OMAP4430
,
2526 static const struct clksel utmi_p2_gfclk_sel
[] = {
2527 { .parent
= &init_60m_fclk
, .rates
= div_1_0_rates
},
2528 { .parent
= &xclk60mhsp2_ck
, .rates
= div_1_1_rates
},
2532 static struct clk utmi_p2_gfclk_ck
= {
2533 .name
= "utmi_p2_gfclk_ck",
2534 .parent
= &init_60m_fclk
,
2535 .clksel
= utmi_p2_gfclk_sel
,
2536 .init
= &omap2_init_clksel_parent
,
2537 .clksel_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2538 .clksel_mask
= OMAP4430_CLKSEL_UTMI_P2_MASK
,
2539 .ops
= &clkops_null
,
2540 .recalc
= &omap2_clksel_recalc
,
2541 .flags
= CLOCK_IN_OMAP4430
,
2548 static struct omap_clk omap44xx_clks
[] = {
2549 CLK(NULL
, "extalt_clkin_ck", &extalt_clkin_ck
, CK_443X
),
2550 CLK(NULL
, "pad_clks_ck", &pad_clks_ck
, CK_443X
),
2551 CLK(NULL
, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck
, CK_443X
),
2552 CLK(NULL
, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck
, CK_443X
),
2553 CLK(NULL
, "slimbus_clk", &slimbus_clk
, CK_443X
),
2554 CLK(NULL
, "sys_32k_ck", &sys_32k_ck
, CK_443X
),
2555 CLK(NULL
, "virt_12000000_ck", &virt_12000000_ck
, CK_443X
),
2556 CLK(NULL
, "virt_13000000_ck", &virt_13000000_ck
, CK_443X
),
2557 CLK(NULL
, "virt_16800000_ck", &virt_16800000_ck
, CK_443X
),
2558 CLK(NULL
, "virt_19200000_ck", &virt_19200000_ck
, CK_443X
),
2559 CLK(NULL
, "virt_26000000_ck", &virt_26000000_ck
, CK_443X
),
2560 CLK(NULL
, "virt_27000000_ck", &virt_27000000_ck
, CK_443X
),
2561 CLK(NULL
, "virt_38400000_ck", &virt_38400000_ck
, CK_443X
),
2562 CLK(NULL
, "sys_clkin_ck", &sys_clkin_ck
, CK_443X
),
2563 CLK(NULL
, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck
, CK_443X
),
2564 CLK(NULL
, "xclk60mhsp1_ck", &xclk60mhsp1_ck
, CK_443X
),
2565 CLK(NULL
, "xclk60mhsp2_ck", &xclk60mhsp2_ck
, CK_443X
),
2566 CLK(NULL
, "xclk60motg_ck", &xclk60motg_ck
, CK_443X
),
2567 CLK(NULL
, "dpll_sys_ref_clk", &dpll_sys_ref_clk
, CK_443X
),
2568 CLK(NULL
, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck
, CK_443X
),
2569 CLK(NULL
, "dpll_abe_ck", &dpll_abe_ck
, CK_443X
),
2570 CLK(NULL
, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck
, CK_443X
),
2571 CLK(NULL
, "abe_24m_fclk", &abe_24m_fclk
, CK_443X
),
2572 CLK(NULL
, "abe_clk", &abe_clk
, CK_443X
),
2573 CLK(NULL
, "aess_fclk", &aess_fclk
, CK_443X
),
2574 CLK(NULL
, "dpll_abe_m3_ck", &dpll_abe_m3_ck
, CK_443X
),
2575 CLK(NULL
, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck
, CK_443X
),
2576 CLK(NULL
, "dpll_core_ck", &dpll_core_ck
, CK_443X
),
2577 CLK(NULL
, "dpll_core_m6_ck", &dpll_core_m6_ck
, CK_443X
),
2578 CLK(NULL
, "dbgclk_mux_ck", &dbgclk_mux_ck
, CK_443X
),
2579 CLK(NULL
, "dpll_core_m2_ck", &dpll_core_m2_ck
, CK_443X
),
2580 CLK(NULL
, "ddrphy_ck", &ddrphy_ck
, CK_443X
),
2581 CLK(NULL
, "dpll_core_m5_ck", &dpll_core_m5_ck
, CK_443X
),
2582 CLK(NULL
, "div_core_ck", &div_core_ck
, CK_443X
),
2583 CLK(NULL
, "div_iva_hs_clk", &div_iva_hs_clk
, CK_443X
),
2584 CLK(NULL
, "div_mpu_hs_clk", &div_mpu_hs_clk
, CK_443X
),
2585 CLK(NULL
, "dpll_core_m4_ck", &dpll_core_m4_ck
, CK_443X
),
2586 CLK(NULL
, "dll_clk_div_ck", &dll_clk_div_ck
, CK_443X
),
2587 CLK(NULL
, "dpll_abe_m2_ck", &dpll_abe_m2_ck
, CK_443X
),
2588 CLK(NULL
, "dpll_core_m3_ck", &dpll_core_m3_ck
, CK_443X
),
2589 CLK(NULL
, "dpll_core_m7_ck", &dpll_core_m7_ck
, CK_443X
),
2590 CLK(NULL
, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck
, CK_443X
),
2591 CLK(NULL
, "dpll_iva_ck", &dpll_iva_ck
, CK_443X
),
2592 CLK(NULL
, "dpll_iva_m4_ck", &dpll_iva_m4_ck
, CK_443X
),
2593 CLK(NULL
, "dpll_iva_m5_ck", &dpll_iva_m5_ck
, CK_443X
),
2594 CLK(NULL
, "dpll_mpu_ck", &dpll_mpu_ck
, CK_443X
),
2595 CLK(NULL
, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck
, CK_443X
),
2596 CLK(NULL
, "per_hs_clk_div_ck", &per_hs_clk_div_ck
, CK_443X
),
2597 CLK(NULL
, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck
, CK_443X
),
2598 CLK(NULL
, "dpll_per_ck", &dpll_per_ck
, CK_443X
),
2599 CLK(NULL
, "dpll_per_m2_ck", &dpll_per_m2_ck
, CK_443X
),
2600 CLK(NULL
, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck
, CK_443X
),
2601 CLK(NULL
, "dpll_per_m3_ck", &dpll_per_m3_ck
, CK_443X
),
2602 CLK(NULL
, "dpll_per_m4_ck", &dpll_per_m4_ck
, CK_443X
),
2603 CLK(NULL
, "dpll_per_m5_ck", &dpll_per_m5_ck
, CK_443X
),
2604 CLK(NULL
, "dpll_per_m6_ck", &dpll_per_m6_ck
, CK_443X
),
2605 CLK(NULL
, "dpll_per_m7_ck", &dpll_per_m7_ck
, CK_443X
),
2606 CLK(NULL
, "dpll_unipro_ck", &dpll_unipro_ck
, CK_443X
),
2607 CLK(NULL
, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck
, CK_443X
),
2608 CLK(NULL
, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck
, CK_443X
),
2609 CLK(NULL
, "dpll_usb_ck", &dpll_usb_ck
, CK_443X
),
2610 CLK(NULL
, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck
, CK_443X
),
2611 CLK(NULL
, "dpll_usb_m2_ck", &dpll_usb_m2_ck
, CK_443X
),
2612 CLK(NULL
, "ducati_clk_mux_ck", &ducati_clk_mux_ck
, CK_443X
),
2613 CLK(NULL
, "func_12m_fclk", &func_12m_fclk
, CK_443X
),
2614 CLK(NULL
, "func_24m_clk", &func_24m_clk
, CK_443X
),
2615 CLK(NULL
, "func_24mc_fclk", &func_24mc_fclk
, CK_443X
),
2616 CLK(NULL
, "func_48m_fclk", &func_48m_fclk
, CK_443X
),
2617 CLK(NULL
, "func_48mc_fclk", &func_48mc_fclk
, CK_443X
),
2618 CLK(NULL
, "func_64m_fclk", &func_64m_fclk
, CK_443X
),
2619 CLK(NULL
, "func_96m_fclk", &func_96m_fclk
, CK_443X
),
2620 CLK(NULL
, "hsmmc6_fclk", &hsmmc6_fclk
, CK_443X
),
2621 CLK(NULL
, "init_60m_fclk", &init_60m_fclk
, CK_443X
),
2622 CLK(NULL
, "l3_div_ck", &l3_div_ck
, CK_443X
),
2623 CLK(NULL
, "l4_div_ck", &l4_div_ck
, CK_443X
),
2624 CLK(NULL
, "lp_clk_div_ck", &lp_clk_div_ck
, CK_443X
),
2625 CLK(NULL
, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck
, CK_443X
),
2626 CLK(NULL
, "per_abe_nc_fclk", &per_abe_nc_fclk
, CK_443X
),
2627 CLK(NULL
, "mcasp2_fclk", &mcasp2_fclk
, CK_443X
),
2628 CLK(NULL
, "mcasp3_fclk", &mcasp3_fclk
, CK_443X
),
2629 CLK(NULL
, "ocp_abe_iclk", &ocp_abe_iclk
, CK_443X
),
2630 CLK(NULL
, "per_abe_24m_fclk", &per_abe_24m_fclk
, CK_443X
),
2631 CLK(NULL
, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck
, CK_443X
),
2632 CLK(NULL
, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck
, CK_443X
),
2633 CLK(NULL
, "syc_clk_div_ck", &syc_clk_div_ck
, CK_443X
),
2634 CLK(NULL
, "aes1_ck", &aes1_ck
, CK_443X
),
2635 CLK(NULL
, "aes2_ck", &aes2_ck
, CK_443X
),
2636 CLK(NULL
, "aess_ck", &aess_ck
, CK_443X
),
2637 CLK(NULL
, "cust_efuse_ck", &cust_efuse_ck
, CK_443X
),
2638 CLK(NULL
, "des3des_ck", &des3des_ck
, CK_443X
),
2639 CLK(NULL
, "dmic_sync_mux_ck", &dmic_sync_mux_ck
, CK_443X
),
2640 CLK(NULL
, "dmic_ck", &dmic_ck
, CK_443X
),
2641 CLK(NULL
, "dss_ck", &dss_ck
, CK_443X
),
2642 CLK(NULL
, "ducati_ck", &ducati_ck
, CK_443X
),
2643 CLK(NULL
, "emif1_ck", &emif1_ck
, CK_443X
),
2644 CLK(NULL
, "emif2_ck", &emif2_ck
, CK_443X
),
2645 CLK(NULL
, "fdif_ck", &fdif_ck
, CK_443X
),
2646 CLK(NULL
, "per_sgx_fclk", &per_sgx_fclk
, CK_443X
),
2647 CLK(NULL
, "gfx_ck", &gfx_ck
, CK_443X
),
2648 CLK(NULL
, "gpio1_ck", &gpio1_ck
, CK_443X
),
2649 CLK(NULL
, "gpio2_ck", &gpio2_ck
, CK_443X
),
2650 CLK(NULL
, "gpio3_ck", &gpio3_ck
, CK_443X
),
2651 CLK(NULL
, "gpio4_ck", &gpio4_ck
, CK_443X
),
2652 CLK(NULL
, "gpio5_ck", &gpio5_ck
, CK_443X
),
2653 CLK(NULL
, "gpio6_ck", &gpio6_ck
, CK_443X
),
2654 CLK(NULL
, "gpmc_ck", &gpmc_ck
, CK_443X
),
2655 CLK(NULL
, "gptimer1_ck", &gptimer1_ck
, CK_443X
),
2656 CLK(NULL
, "gptimer10_ck", &gptimer10_ck
, CK_443X
),
2657 CLK(NULL
, "gptimer11_ck", &gptimer11_ck
, CK_443X
),
2658 CLK(NULL
, "gptimer2_ck", &gptimer2_ck
, CK_443X
),
2659 CLK(NULL
, "gptimer3_ck", &gptimer3_ck
, CK_443X
),
2660 CLK(NULL
, "gptimer4_ck", &gptimer4_ck
, CK_443X
),
2661 CLK(NULL
, "gptimer5_ck", &gptimer5_ck
, CK_443X
),
2662 CLK(NULL
, "gptimer6_ck", &gptimer6_ck
, CK_443X
),
2663 CLK(NULL
, "gptimer7_ck", &gptimer7_ck
, CK_443X
),
2664 CLK(NULL
, "gptimer8_ck", &gptimer8_ck
, CK_443X
),
2665 CLK(NULL
, "gptimer9_ck", &gptimer9_ck
, CK_443X
),
2666 CLK("omap2_hdq.0", "ick", &hdq1w_ck
, CK_443X
),
2667 CLK(NULL
, "hsi_ck", &hsi_ck
, CK_443X
),
2668 CLK("i2c_omap.1", "ick", &i2c1_ck
, CK_443X
),
2669 CLK("i2c_omap.2", "ick", &i2c2_ck
, CK_443X
),
2670 CLK("i2c_omap.3", "ick", &i2c3_ck
, CK_443X
),
2671 CLK("i2c_omap.4", "ick", &i2c4_ck
, CK_443X
),
2672 CLK(NULL
, "iss_ck", &iss_ck
, CK_443X
),
2673 CLK(NULL
, "ivahd_ck", &ivahd_ck
, CK_443X
),
2674 CLK(NULL
, "keyboard_ck", &keyboard_ck
, CK_443X
),
2675 CLK(NULL
, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck
, CK_443X
),
2676 CLK(NULL
, "l3_interconnect_3_ck", &l3_interconnect_3_ck
, CK_443X
),
2677 CLK(NULL
, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck
, CK_443X
),
2678 CLK(NULL
, "mcasp_ck", &mcasp_ck
, CK_443X
),
2679 CLK(NULL
, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck
, CK_443X
),
2680 CLK("omap-mcbsp.1", "fck", &mcbsp1_ck
, CK_443X
),
2681 CLK(NULL
, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck
, CK_443X
),
2682 CLK("omap-mcbsp.2", "fck", &mcbsp2_ck
, CK_443X
),
2683 CLK(NULL
, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck
, CK_443X
),
2684 CLK("omap-mcbsp.3", "fck", &mcbsp3_ck
, CK_443X
),
2685 CLK(NULL
, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck
, CK_443X
),
2686 CLK("omap-mcbsp.4", "fck", &mcbsp4_ck
, CK_443X
),
2687 CLK("omap2_mcspi.1", "fck", &mcspi1_ck
, CK_443X
),
2688 CLK("omap2_mcspi.2", "fck", &mcspi2_ck
, CK_443X
),
2689 CLK("omap2_mcspi.3", "fck", &mcspi3_ck
, CK_443X
),
2690 CLK("omap2_mcspi.4", "fck", &mcspi4_ck
, CK_443X
),
2691 CLK("mmci-omap-hs.0", "fck", &mmc1_ck
, CK_443X
),
2692 CLK("mmci-omap-hs.1", "fck", &mmc2_ck
, CK_443X
),
2693 CLK("mmci-omap-hs.2", "fck", &mmc3_ck
, CK_443X
),
2694 CLK("mmci-omap-hs.3", "fck", &mmc4_ck
, CK_443X
),
2695 CLK("mmci-omap-hs.4", "fck", &mmc5_ck
, CK_443X
),
2696 CLK(NULL
, "ocp_wp1_ck", &ocp_wp1_ck
, CK_443X
),
2697 CLK(NULL
, "pdm_ck", &pdm_ck
, CK_443X
),
2698 CLK(NULL
, "pkaeip29_ck", &pkaeip29_ck
, CK_443X
),
2699 CLK("omap_rng", "ick", &rng_ck
, CK_443X
),
2700 CLK(NULL
, "sha2md51_ck", &sha2md51_ck
, CK_443X
),
2701 CLK(NULL
, "sl2_ck", &sl2_ck
, CK_443X
),
2702 CLK(NULL
, "slimbus1_ck", &slimbus1_ck
, CK_443X
),
2703 CLK(NULL
, "slimbus2_ck", &slimbus2_ck
, CK_443X
),
2704 CLK(NULL
, "sr_core_ck", &sr_core_ck
, CK_443X
),
2705 CLK(NULL
, "sr_iva_ck", &sr_iva_ck
, CK_443X
),
2706 CLK(NULL
, "sr_mpu_ck", &sr_mpu_ck
, CK_443X
),
2707 CLK(NULL
, "tesla_ck", &tesla_ck
, CK_443X
),
2708 CLK(NULL
, "uart1_ck", &uart1_ck
, CK_443X
),
2709 CLK(NULL
, "uart2_ck", &uart2_ck
, CK_443X
),
2710 CLK(NULL
, "uart3_ck", &uart3_ck
, CK_443X
),
2711 CLK(NULL
, "uart4_ck", &uart4_ck
, CK_443X
),
2712 CLK(NULL
, "unipro1_ck", &unipro1_ck
, CK_443X
),
2713 CLK(NULL
, "usb_host_ck", &usb_host_ck
, CK_443X
),
2714 CLK(NULL
, "usb_host_fs_ck", &usb_host_fs_ck
, CK_443X
),
2715 CLK("musb_hdrc", "ick", &usb_otg_ck
, CK_443X
),
2716 CLK(NULL
, "usb_tll_ck", &usb_tll_ck
, CK_443X
),
2717 CLK(NULL
, "usbphyocp2scp_ck", &usbphyocp2scp_ck
, CK_443X
),
2718 CLK(NULL
, "usim_ck", &usim_ck
, CK_443X
),
2719 CLK("omap_wdt", "fck", &wdt2_ck
, CK_443X
),
2720 CLK(NULL
, "wdt3_ck", &wdt3_ck
, CK_443X
),
2721 CLK(NULL
, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck
, CK_443X
),
2722 CLK(NULL
, "stm_clk_div_ck", &stm_clk_div_ck
, CK_443X
),
2723 CLK(NULL
, "trace_clk_div_ck", &trace_clk_div_ck
, CK_443X
),
2724 CLK(NULL
, "usim_fclk", &usim_fclk
, CK_443X
),
2725 CLK(NULL
, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck
, CK_443X
),
2726 CLK(NULL
, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck
, CK_443X
),
2729 int __init
omap2_clk_init(void)
2731 /* struct prcm_config *prcm; */
2736 if (cpu_is_omap44xx()) {
2737 cpu_mask
= RATE_IN_4430
;
2738 cpu_clkflg
= CK_443X
;
2741 clk_init(&omap2_clk_functions
);
2743 for (c
= omap44xx_clks
; c
< omap44xx_clks
+ ARRAY_SIZE(omap44xx_clks
);
2745 clk_preinit(c
->lk
.clk
);
2747 for (c
= omap44xx_clks
; c
< omap44xx_clks
+ ARRAY_SIZE(omap44xx_clks
);
2749 if (c
->cpu
& cpu_clkflg
) {
2751 clk_register(c
->lk
.clk
);
2753 omap2_init_clk_clkdm(c->lk.clk);
2757 recalculate_root_clocks();
2760 * Only enable those clocks we will need, let the drivers
2761 * enable other clocks as necessary
2763 clk_enable_init_clocks();