arch/arm/mach-omap2/clockdomains.h

   1 /*
   2  * OMAP2/3 clockdomains
   3  *
   4  * Copyright (C) 2008 Texas Instruments, Inc.
   5  * Copyright (C) 2008-2009 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley and Jouni Högander
   8  *
   9  * This file contains clockdomains and clockdomain wakeup/sleep
  10  * dependencies for the OMAP2/3 chips.  Some notes:
  11  *
  12  * A useful validation rule for struct clockdomain: Any clockdomain
  13  * referenced by a wkdep_srcs or sleepdep_srcs array must have a
  14  * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
  15  * software-controllable dependencies.  Non-software-controllable
  16  * dependencies do exist, but they are not encoded below (yet).
  17  *
  18  * 24xx does not support programmable sleep dependencies (SLEEPDEP)
  19  *
  20  * The overly-specific dep_bit names are due to a bit name collision
  21  * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
  22  * value are the same for all powerdomains: 2
  23  *
  24  * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
  25  * sanity check?
  26  * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
  27  */
  28
  29 /*
  30  * To-Do List
  31  * -> Port the Sleep/Wakeup dependencies for the domains
  32  *    from the Power domain framework
  33  */
  34
  35 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  36 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  37
  38 #include <plat/clockdomain.h>
  39 #include "cm.h"
  40 #include "prm.h"
  41
  42 /*
  43  * Clockdomain dependencies for wkdeps/sleepdeps
  44  *
  45  * XXX Hardware dependencies (e.g., dependencies that cannot be
  46  * changed in software) are not included here yet, but should be.
  47  */
  48
  49 /* OMAP2/3-common wakeup dependencies */
  50
  51 /*
  52  * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
  53  * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
  54  * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
  55  * These can share data since they will never be present simultaneously
  56  * on the same device.
  57  */
  58 static struct clkdm_dep gfx_sgx_wkdeps[] = {
  59         {
  60                 .clkdm_name = "core_l3_clkdm",
  61                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  62         },
  63         {
  64                 .clkdm_name = "core_l4_clkdm",
  65                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  66         },
  67         {
  68                 .clkdm_name = "iva2_clkdm",
  69                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  70         },
  71         {
  72                 .clkdm_name = "mpu_clkdm",
  73                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  74                                             CHIP_IS_OMAP3430)
  75         },
  76         {
  77                 .clkdm_name = "wkup_clkdm",
  78                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  79                                             CHIP_IS_OMAP3430)
  80         },
  81         { NULL },
  82 };
  83
  84
  85 /* 24XX-specific possible dependencies */
  86
  87 #ifdef CONFIG_ARCH_OMAP24XX
  88
  89 /* Wakeup dependency source arrays */
  90
  91 /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
  92 static struct clkdm_dep dsp_24xx_wkdeps[] = {
  93         {
  94                 .clkdm_name = "core_l3_clkdm",
  95                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  96         },
  97         {
  98                 .clkdm_name = "core_l4_clkdm",
  99                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 100         },
 101         {
 102                 .clkdm_name = "mpu_clkdm",
 103                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 104         },
 105         {
 106                 .clkdm_name = "wkup_clkdm",
 107                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 108         },
 109         { NULL },
 110 };
 111
 112 /*
 113  * 2420/2430 PM_WKDEP_MDM: CORE, MPU, WKUP
 114  * XXX This is probably 2430-only; 2420 did not have a stacked modem config.
 115  */
 116 static struct clkdm_dep mdm_24xx_wkdeps[] = {
 117         {
 118                 .clkdm_name = "core_l3_clkdm",
 119                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 120         },
 121         {
 122                 .clkdm_name = "core_l4_clkdm",
 123                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 124         },
 125         {
 126                 .clkdm_name = "mpu_clkdm",
 127                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 128         },
 129         {
 130                 .clkdm_name = "wkup_clkdm",
 131                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 132         },
 133         { NULL },
 134 };
 135
 136 /*
 137  * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
 138  * 2430 adds MDM
 139  */
 140 static struct clkdm_dep mpu_24xx_wkdeps[] = {
 141         {
 142                 .clkdm_name = "core_l3_clkdm",
 143                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 144         },
 145         {
 146                 .clkdm_name = "core_l4_clkdm",
 147                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 148         },
 149         {
 150                 .clkdm_name = "dsp_clkdm",
 151                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 152         },
 153         {
 154                 .clkdm_name = "wkup_clkdm",
 155                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 156         },
 157         {
 158                 .clkdm_name = "mdm_clkdm",
 159                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 160         },
 161         { NULL },
 162 };
 163
 164 /*
 165  * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
 166  * 2430 adds MDM
 167  */
 168 static struct clkdm_dep core_24xx_wkdeps[] = {
 169         {
 170                 .clkdm_name = "dsp_clkdm",
 171                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 172         },
 173         {
 174                 .clkdm_name = "gfx_clkdm",
 175                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 176         },
 177         {
 178                 .clkdm_name = "mpu_clkdm",
 179                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 180         },
 181         {
 182                 .clkdm_name = "wkup_clkdm",
 183                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 184         },
 185         {
 186                 .clkdm_name = "mdm_clkdm",
 187                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 188         },
 189         { NULL },
 190 };
 191
 192 #endif
 193
 194 /* 34XX-specific possible dependencies */
 195
 196 #ifdef CONFIG_ARCH_OMAP34XX
 197
 198 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
 199 static struct clkdm_dep per_wkdeps[] = {
 200         {
 201                 .clkdm_name = "core_l3_clkdm",
 202                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 203         },
 204         {
 205                 .clkdm_name = "core_l4_clkdm",
 206                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 207         },
 208         {
 209                 .clkdm_name = "iva2_clkdm",
 210                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 211         },
 212         {
 213                 .clkdm_name = "mpu_clkdm",
 214                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 215         },
 216         {
 217                 .clkdm_name = "wkup_clkdm",
 218                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 219         },
 220         { NULL },
 221 };
 222
 223 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
 224 static struct clkdm_dep usbhost_wkdeps[] = {
 225         {
 226                 .clkdm_name = "core_l3_clkdm",
 227                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 228         },
 229         {
 230                 .clkdm_name = "core_l4_clkdm",
 231                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 232         },
 233         {
 234                 .clkdm_name = "iva2_clkdm",
 235                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 236         },
 237         {
 238                 .clkdm_name = "mpu_clkdm",
 239                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 240         },
 241         {
 242                 .clkdm_name = "wkup_clkdm",
 243                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 244         },
 245         { NULL },
 246 };
 247
 248 /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
 249 static struct clkdm_dep mpu_34xx_wkdeps[] = {
 250         {
 251                 .clkdm_name = "core_l3_clkdm",
 252                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 253         },
 254         {
 255                 .clkdm_name = "core_l4_clkdm",
 256                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 257         },
 258         {
 259                 .clkdm_name = "iva2_clkdm",
 260                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 261         },
 262         {
 263                 .clkdm_name = "dss_clkdm",
 264                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 265         },
 266         {
 267                 .clkdm_name = "per_clkdm",
 268                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 269         },
 270         { NULL },
 271 };
 272
 273 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
 274 static struct clkdm_dep iva2_wkdeps[] = {
 275         {
 276                 .clkdm_name = "core_l3_clkdm",
 277                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 278         },
 279         {
 280                 .clkdm_name = "core_l4_clkdm",
 281                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 282         },
 283         {
 284                 .clkdm_name = "mpu_clkdm",
 285                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 286         },
 287         {
 288                 .clkdm_name = "wkup_clkdm",
 289                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 290         },
 291         {
 292                 .clkdm_name = "dss_clkdm",
 293                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 294         },
 295         {
 296                 .clkdm_name = "per_clkdm",
 297                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 298         },
 299         { NULL },
 300 };
 301
 302
 303 /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
 304 static struct clkdm_dep cam_wkdeps[] = {
 305         {
 306                 .clkdm_name = "iva2_clkdm",
 307                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 308         },
 309         {
 310                 .clkdm_name = "mpu_clkdm",
 311                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 312         },
 313         {
 314                 .clkdm_name = "wkup_clkdm",
 315                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 316         },
 317         { NULL },
 318 };
 319
 320 /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
 321 static struct clkdm_dep dss_wkdeps[] = {
 322         {
 323                 .clkdm_name = "iva2_clkdm",
 324                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 325         },
 326         {
 327                 .clkdm_name = "mpu_clkdm",
 328                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 329         },
 330         {
 331                 .clkdm_name = "wkup_clkdm",
 332                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 333         },
 334         { NULL },
 335 };
 336
 337 /* 3430: PM_WKDEP_NEON: MPU */
 338 static struct clkdm_dep neon_wkdeps[] = {
 339         {
 340                 .clkdm_name = "mpu_clkdm",
 341                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 342         },
 343         { NULL },
 344 };
 345
 346
 347 /* Sleep dependency source arrays for 34xx-specific clkdms - 34XX only */
 348
 349 /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
 350 static struct clkdm_dep dss_sleepdeps[] = {
 351         {
 352                 .clkdm_name = "mpu_clkdm",
 353                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 354         },
 355         {
 356                 .clkdm_name = "iva2_clkdm",
 357                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 358         },
 359         { NULL },
 360 };
 361
 362 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
 363 static struct clkdm_dep per_sleepdeps[] = {
 364         {
 365                 .clkdm_name = "mpu_clkdm",
 366                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 367         },
 368         {
 369                 .clkdm_name = "iva2_clkdm",
 370                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 371         },
 372         { NULL },
 373 };
 374
 375 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
 376 static struct clkdm_dep usbhost_sleepdeps[] = {
 377         {
 378                 .clkdm_name = "mpu_clkdm",
 379                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 380         },
 381         {
 382                 .clkdm_name = "iva2_clkdm",
 383                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 384         },
 385         { NULL },
 386 };
 387
 388 /* 3430: CM_SLEEPDEP_CAM: MPU */
 389 static struct clkdm_dep cam_sleepdeps[] = {
 390         {
 391                 .clkdm_name = "mpu_clkdm",
 392                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 393         },
 394         { NULL },
 395 };
 396
 397 /*
 398  * 3430ES1: CM_SLEEPDEP_GFX: MPU
 399  * 3430ES2: CM_SLEEPDEP_SGX: MPU
 400  * These can share data since they will never be present simultaneously
 401  * on the same device.
 402  */
 403 static struct clkdm_dep gfx_sgx_sleepdeps[] = {
 404         {
 405                 .clkdm_name = "mpu_clkdm",
 406                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 407         },
 408         { NULL },
 409 };
 410
 411 #endif /* CONFIG_ARCH_OMAP34XX */
 412
 413
 414 /*
 415  * OMAP2/3-common clockdomains
 416  *
 417  * Even though the 2420 has a single PRCM module from the
 418  * interconnect's perspective, internally it does appear to have
 419  * separate PRM and CM clockdomains.  The usual test case is
 420  * sys_clkout/sys_clkout2.
 421  */
 422
 423 #if defined(CONFIG_ARCH_OMAP24XX) | defined(CONFIG_ARCH_OMAP34XX)
 424
 425 /* This is an implicit clockdomain - it is never defined as such in TRM */
 426 static struct clockdomain wkup_clkdm = {
 427         .name           = "wkup_clkdm",
 428         .pwrdm          = { .name = "wkup_pwrdm" },
 429         .dep_bit        = OMAP_EN_WKUP_SHIFT,
 430         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 431 };
 432
 433 static struct clockdomain prm_clkdm = {
 434         .name           = "prm_clkdm",
 435         .pwrdm          = { .name = "wkup_pwrdm" },
 436         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 437 };
 438
 439 static struct clockdomain cm_clkdm = {
 440         .name           = "cm_clkdm",
 441         .pwrdm          = { .name = "core_pwrdm" },
 442         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 443 };
 444
 445 #endif
 446
 447 /*
 448  * 2420-only clockdomains
 449  */
 450
 451 #if defined(CONFIG_ARCH_OMAP2420)
 452
 453 static struct clockdomain mpu_2420_clkdm = {
 454         .name           = "mpu_clkdm",
 455         .pwrdm          = { .name = "mpu_pwrdm" },
 456         .flags          = CLKDM_CAN_HWSUP,
 457         .clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
 458         .wkdep_srcs     = mpu_24xx_wkdeps,
 459         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 460         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 461 };
 462
 463 static struct clockdomain iva1_2420_clkdm = {
 464         .name           = "iva1_clkdm",
 465         .pwrdm          = { .name = "dsp_pwrdm" },
 466         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 467         .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
 468                                                  OMAP2_CM_CLKSTCTRL),
 469         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 470         .wkdep_srcs     = dsp_24xx_wkdeps,
 471         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
 472         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 473 };
 474
 475 static struct clockdomain dsp_2420_clkdm = {
 476         .name           = "dsp_clkdm",
 477         .pwrdm          = { .name = "dsp_pwrdm" },
 478         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 479         .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
 480                                                  OMAP2_CM_CLKSTCTRL),
 481         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 482         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 483 };
 484
 485 static struct clockdomain gfx_2420_clkdm = {
 486         .name           = "gfx_clkdm",
 487         .pwrdm          = { .name = "gfx_pwrdm" },
 488         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 489         .clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 490         .wkdep_srcs     = gfx_sgx_wkdeps,
 491         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 493 };
 494
 495 static struct clockdomain core_l3_2420_clkdm = {
 496         .name           = "core_l3_clkdm",
 497         .pwrdm          = { .name = "core_pwrdm" },
 498         .flags          = CLKDM_CAN_HWSUP,
 499         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 500         .wkdep_srcs     = core_24xx_wkdeps,
 501         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 502         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 503 };
 504
 505 static struct clockdomain core_l4_2420_clkdm = {
 506         .name           = "core_l4_clkdm",
 507         .pwrdm          = { .name = "core_pwrdm" },
 508         .flags          = CLKDM_CAN_HWSUP,
 509         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 510         .wkdep_srcs     = core_24xx_wkdeps,
 511         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 512         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 513 };
 514
 515 static struct clockdomain dss_2420_clkdm = {
 516         .name           = "dss_clkdm",
 517         .pwrdm          = { .name = "core_pwrdm" },
 518         .flags          = CLKDM_CAN_HWSUP,
 519         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 520         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 521         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 522 };
 523
 524 #endif   /* CONFIG_ARCH_OMAP2420 */
 525
 526
 527 /*
 528  * 2430-only clockdomains
 529  */
 530
 531 #if defined(CONFIG_ARCH_OMAP2430)
 532
 533 static struct clockdomain mpu_2430_clkdm = {
 534         .name           = "mpu_clkdm",
 535         .pwrdm          = { .name = "mpu_pwrdm" },
 536         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 537         .clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
 538                                                  OMAP2_CM_CLKSTCTRL),
 539         .wkdep_srcs     = mpu_24xx_wkdeps,
 540         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 541         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 542 };
 543
 544 /* Another case of bit name collisions between several registers: EN_MDM */
 545 static struct clockdomain mdm_clkdm = {
 546         .name           = "mdm_clkdm",
 547         .pwrdm          = { .name = "mdm_pwrdm" },
 548         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 549         .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
 550                                                  OMAP2_CM_CLKSTCTRL),
 551         .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
 552         .wkdep_srcs     = mdm_24xx_wkdeps,
 553         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
 554         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 555 };
 556
 557 static struct clockdomain dsp_2430_clkdm = {
 558         .name           = "dsp_clkdm",
 559         .pwrdm          = { .name = "dsp_pwrdm" },
 560         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 561         .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
 562                                                  OMAP2_CM_CLKSTCTRL),
 563         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 564         .wkdep_srcs     = dsp_24xx_wkdeps,
 565         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 566         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 567 };
 568
 569 static struct clockdomain gfx_2430_clkdm = {
 570         .name           = "gfx_clkdm",
 571         .pwrdm          = { .name = "gfx_pwrdm" },
 572         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 573         .clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 574         .wkdep_srcs     = gfx_sgx_wkdeps,
 575         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 577 };
 578
 579 /*
 580  * XXX add usecounting for clkdm dependencies, otherwise the presence
 581  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 582  * could cause trouble
 583  */
 584 static struct clockdomain core_l3_2430_clkdm = {
 585         .name           = "core_l3_clkdm",
 586         .pwrdm          = { .name = "core_pwrdm" },
 587         .flags          = CLKDM_CAN_HWSUP,
 588         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 589         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 590         .wkdep_srcs     = core_24xx_wkdeps,
 591         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 592         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 593 };
 594
 595 /*
 596  * XXX add usecounting for clkdm dependencies, otherwise the presence
 597  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 598  * could cause trouble
 599  */
 600 static struct clockdomain core_l4_2430_clkdm = {
 601         .name           = "core_l4_clkdm",
 602         .pwrdm          = { .name = "core_pwrdm" },
 603         .flags          = CLKDM_CAN_HWSUP,
 604         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 605         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 606         .wkdep_srcs     = core_24xx_wkdeps,
 607         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 608         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 609 };
 610
 611 static struct clockdomain dss_2430_clkdm = {
 612         .name           = "dss_clkdm",
 613         .pwrdm          = { .name = "core_pwrdm" },
 614         .flags          = CLKDM_CAN_HWSUP,
 615         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 616         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 617         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 618 };
 619
 620 #endif    /* CONFIG_ARCH_OMAP2430 */
 621
 622
 623 /*
 624  * 34xx clockdomains
 625  */
 626
 627 #if defined(CONFIG_ARCH_OMAP34XX)
 628
 629 static struct clockdomain mpu_34xx_clkdm = {
 630         .name           = "mpu_clkdm",
 631         .pwrdm          = { .name = "mpu_pwrdm" },
 632         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
 633         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
 634         .dep_bit        = OMAP3430_EN_MPU_SHIFT,
 635         .wkdep_srcs     = mpu_34xx_wkdeps,
 636         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 637         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 638 };
 639
 640 static struct clockdomain neon_clkdm = {
 641         .name           = "neon_clkdm",
 642         .pwrdm          = { .name = "neon_pwrdm" },
 643         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 644         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
 645                                                  OMAP2_CM_CLKSTCTRL),
 646         .wkdep_srcs     = neon_wkdeps,
 647         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
 648         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 649 };
 650
 651 static struct clockdomain iva2_clkdm = {
 652         .name           = "iva2_clkdm",
 653         .pwrdm          = { .name = "iva2_pwrdm" },
 654         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 655         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 656                                                  OMAP2_CM_CLKSTCTRL),
 657         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
 658         .wkdep_srcs     = iva2_wkdeps,
 659         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
 660         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 661 };
 662
 663 static struct clockdomain gfx_3430es1_clkdm = {
 664         .name           = "gfx_clkdm",
 665         .pwrdm          = { .name = "gfx_pwrdm" },
 666         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 667         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 668         .wkdep_srcs     = gfx_sgx_wkdeps,
 669         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 670         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
 671         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 672 };
 673
 674 static struct clockdomain sgx_clkdm = {
 675         .name           = "sgx_clkdm",
 676         .pwrdm          = { .name = "sgx_pwrdm" },
 677         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 678         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
 679                                                  OMAP2_CM_CLKSTCTRL),
 680         .wkdep_srcs     = gfx_sgx_wkdeps,
 681         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 682         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 683         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 684 };
 685
 686 /*
 687  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 688  * then that information was removed from the 34xx ES2+ TRM.  It is
 689  * unclear whether the core is still there, but the clockdomain logic
 690  * is there, and must be programmed to an appropriate state if the
 691  * CORE clockdomain is to become inactive.
 692  */
 693 static struct clockdomain d2d_clkdm = {
 694         .name           = "d2d_clkdm",
 695         .pwrdm          = { .name = "core_pwrdm" },
 696         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 697         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 698         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 699         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 700 };
 701
 702 /*
 703  * XXX add usecounting for clkdm dependencies, otherwise the presence
 704  * of a single dep bit for core_l3_34xx_clkdm and core_l4_34xx_clkdm
 705  * could cause trouble
 706  */
 707 static struct clockdomain core_l3_34xx_clkdm = {
 708         .name           = "core_l3_clkdm",
 709         .pwrdm          = { .name = "core_pwrdm" },
 710         .flags          = CLKDM_CAN_HWSUP,
 711         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 712         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 713         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
 714         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 715 };
 716
 717 /*
 718  * XXX add usecounting for clkdm dependencies, otherwise the presence
 719  * of a single dep bit for core_l3_34xx_clkdm and core_l4_34xx_clkdm
 720  * could cause trouble
 721  */
 722 static struct clockdomain core_l4_34xx_clkdm = {
 723         .name           = "core_l4_clkdm",
 724         .pwrdm          = { .name = "core_pwrdm" },
 725         .flags          = CLKDM_CAN_HWSUP,
 726         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 727         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 728         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
 729         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 730 };
 731
 732 /* Another case of bit name collisions between several registers: EN_DSS */
 733 static struct clockdomain dss_34xx_clkdm = {
 734         .name           = "dss_clkdm",
 735         .pwrdm          = { .name = "dss_pwrdm" },
 736         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 737         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
 738                                                  OMAP2_CM_CLKSTCTRL),
 739         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
 740         .wkdep_srcs     = dss_wkdeps,
 741         .sleepdep_srcs  = dss_sleepdeps,
 742         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 743         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 744 };
 745
 746 static struct clockdomain cam_clkdm = {
 747         .name           = "cam_clkdm",
 748         .pwrdm          = { .name = "cam_pwrdm" },
 749         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 750         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
 751                                                  OMAP2_CM_CLKSTCTRL),
 752         .wkdep_srcs     = cam_wkdeps,
 753         .sleepdep_srcs  = cam_sleepdeps,
 754         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
 755         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 756 };
 757
 758 static struct clockdomain usbhost_clkdm = {
 759         .name           = "usbhost_clkdm",
 760         .pwrdm          = { .name = "usbhost_pwrdm" },
 761         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 762         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
 763                                                  OMAP2_CM_CLKSTCTRL),
 764         .wkdep_srcs     = usbhost_wkdeps,
 765         .sleepdep_srcs  = usbhost_sleepdeps,
 766         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 767         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 768 };
 769
 770 static struct clockdomain per_clkdm = {
 771         .name           = "per_clkdm",
 772         .pwrdm          = { .name = "per_pwrdm" },
 773         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 774         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
 775                                                  OMAP2_CM_CLKSTCTRL),
 776         .dep_bit        = OMAP3430_EN_PER_SHIFT,
 777         .wkdep_srcs     = per_wkdeps,
 778         .sleepdep_srcs  = per_sleepdeps,
 779         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 780         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 781 };
 782
 783 /*
 784  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 785  * switched of even if sdti is in use
 786  */
 787 static struct clockdomain emu_clkdm = {
 788         .name           = "emu_clkdm",
 789         .pwrdm          = { .name = "emu_pwrdm" },
 790         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
 791         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
 792                                                  OMAP2_CM_CLKSTCTRL),
 793         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 794         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 795 };
 796
 797 static struct clockdomain dpll1_clkdm = {
 798         .name           = "dpll1_clkdm",
 799         .pwrdm          = { .name = "dpll1_pwrdm" },
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 801 };
 802
 803 static struct clockdomain dpll2_clkdm = {
 804         .name           = "dpll2_clkdm",
 805         .pwrdm          = { .name = "dpll2_pwrdm" },
 806         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 807 };
 808
 809 static struct clockdomain dpll3_clkdm = {
 810         .name           = "dpll3_clkdm",
 811         .pwrdm          = { .name = "dpll3_pwrdm" },
 812         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 813 };
 814
 815 static struct clockdomain dpll4_clkdm = {
 816         .name           = "dpll4_clkdm",
 817         .pwrdm          = { .name = "dpll4_pwrdm" },
 818         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 819 };
 820
 821 static struct clockdomain dpll5_clkdm = {
 822         .name           = "dpll5_clkdm",
 823         .pwrdm          = { .name = "dpll5_pwrdm" },
 824         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 825 };
 826
 827 #endif   /* CONFIG_ARCH_OMAP34XX */
 828
 829 #include "clockdomains44xx.h"
 830
 831 /*
 832  * Clockdomain hwsup dependencies (34XX only)
 833  */
 834
 835 static struct clkdm_autodep clkdm_autodeps[] = {
 836         {
 837                 .clkdm     = { .name = "mpu_clkdm" },
 838                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 839         },
 840         {
 841                 .clkdm     = { .name = "iva2_clkdm" },
 842                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 843         },
 844         {
 845                 .clkdm     = { .name = NULL },
 846         }
 847 };
 848
 849 /*
 850  * List of clockdomain pointers per platform
 851  */
 852
 853 static struct clockdomain *clockdomains_omap[] = {
 854
 855 #if defined(CONFIG_ARCH_OMAP24XX) | defined(CONFIG_ARCH_OMAP34XX)
 856         &wkup_clkdm,
 857         &cm_clkdm,
 858         &prm_clkdm,
 859 #endif
 860
 861 #ifdef CONFIG_ARCH_OMAP2420
 862         &mpu_2420_clkdm,
 863         &iva1_2420_clkdm,
 864         &dsp_2420_clkdm,
 865         &gfx_2420_clkdm,
 866         &core_l3_2420_clkdm,
 867         &core_l4_2420_clkdm,
 868         &dss_2420_clkdm,
 869 #endif
 870
 871 #ifdef CONFIG_ARCH_OMAP2430
 872         &mpu_2430_clkdm,
 873         &mdm_clkdm,
 874         &dsp_2430_clkdm,
 875         &gfx_2430_clkdm,
 876         &core_l3_2430_clkdm,
 877         &core_l4_2430_clkdm,
 878         &dss_2430_clkdm,
 879 #endif
 880
 881 #ifdef CONFIG_ARCH_OMAP34XX
 882         &mpu_34xx_clkdm,
 883         &neon_clkdm,
 884         &iva2_clkdm,
 885         &gfx_3430es1_clkdm,
 886         &sgx_clkdm,
 887         &d2d_clkdm,
 888         &core_l3_34xx_clkdm,
 889         &core_l4_34xx_clkdm,
 890         &dss_34xx_clkdm,
 891         &cam_clkdm,
 892         &usbhost_clkdm,
 893         &per_clkdm,
 894         &emu_clkdm,
 895         &dpll1_clkdm,
 896         &dpll2_clkdm,
 897         &dpll3_clkdm,
 898         &dpll4_clkdm,
 899         &dpll5_clkdm,
 900 #endif
 901
 902 #ifdef CONFIG_ARCH_OMAP4
 903         &l4_cefuse_44xx_clkdm,
 904         &l4_cfg_44xx_clkdm,
 905         &tesla_44xx_clkdm,
 906         &l3_gfx_44xx_clkdm,
 907         &ivahd_44xx_clkdm,
 908         &l4_secure_44xx_clkdm,
 909         &l4_per_44xx_clkdm,
 910         &abe_44xx_clkdm,
 911         &l3_instr_44xx_clkdm,
 912         &l3_init_44xx_clkdm,
 913         &mpuss_44xx_clkdm,
 914         &mpu0_44xx_clkdm,
 915         &mpu1_44xx_clkdm,
 916         &l3_emif_44xx_clkdm,
 917         &l4_ao_44xx_clkdm,
 918         &ducati_44xx_clkdm,
 919         &l3_2_44xx_clkdm,
 920         &l3_1_44xx_clkdm,
 921         &l3_d2d_44xx_clkdm,
 922         &iss_44xx_clkdm,
 923         &l3_dss_44xx_clkdm,
 924         &l4_wkup_44xx_clkdm,
 925         &emu_sys_44xx_clkdm,
 926         &l3_dma_44xx_clkdm,
 927 #endif
 928
 929         NULL,
 930 };
 931
 932 #endif