2 * OMAP2/3 CM module functions
4 * Copyright (C) 2009 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
25 #include "cm2xxx_3xxx.h"
26 #include "cm-regbits-24xx.h"
27 #include "cm-regbits-34xx.h"
29 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
30 #define DPLL_AUTOIDLE_DISABLE 0x0
31 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
33 /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
34 #define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
35 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
37 static const u8 cm_idlest_offs
[] = {
38 CM_IDLEST1
, CM_IDLEST2
, OMAP2430_CM_IDLEST3
, OMAP24XX_CM_IDLEST4
41 u32
omap2_cm_read_mod_reg(s16 module
, u16 idx
)
43 return __raw_readl(cm_base
+ module
+ idx
);
46 void omap2_cm_write_mod_reg(u32 val
, s16 module
, u16 idx
)
48 __raw_writel(val
, cm_base
+ module
+ idx
);
51 /* Read-modify-write a register in a CM module. Caller must lock */
52 u32
omap2_cm_rmw_mod_reg_bits(u32 mask
, u32 bits
, s16 module
, s16 idx
)
56 v
= omap2_cm_read_mod_reg(module
, idx
);
59 omap2_cm_write_mod_reg(v
, module
, idx
);
64 u32
omap2_cm_set_mod_reg_bits(u32 bits
, s16 module
, s16 idx
)
66 return omap2_cm_rmw_mod_reg_bits(bits
, bits
, module
, idx
);
69 u32
omap2_cm_clear_mod_reg_bits(u32 bits
, s16 module
, s16 idx
)
71 return omap2_cm_rmw_mod_reg_bits(bits
, 0x0, module
, idx
);
78 static void _write_clktrctrl(u8 c
, s16 module
, u32 mask
)
82 v
= omap2_cm_read_mod_reg(module
, OMAP2_CM_CLKSTCTRL
);
84 v
|= c
<< __ffs(mask
);
85 omap2_cm_write_mod_reg(v
, module
, OMAP2_CM_CLKSTCTRL
);
88 bool omap2_cm_is_clkdm_in_hwsup(s16 module
, u32 mask
)
93 BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
95 v
= omap2_cm_read_mod_reg(module
, OMAP2_CM_CLKSTCTRL
);
99 if (cpu_is_omap24xx())
100 ret
= (v
== OMAP24XX_CLKSTCTRL_ENABLE_AUTO
) ? 1 : 0;
102 ret
= (v
== OMAP34XX_CLKSTCTRL_ENABLE_AUTO
) ? 1 : 0;
107 void omap2xxx_cm_clkdm_enable_hwsup(s16 module
, u32 mask
)
109 _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO
, module
, mask
);
112 void omap2xxx_cm_clkdm_disable_hwsup(s16 module
, u32 mask
)
114 _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO
, module
, mask
);
117 void omap3xxx_cm_clkdm_enable_hwsup(s16 module
, u32 mask
)
119 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO
, module
, mask
);
122 void omap3xxx_cm_clkdm_disable_hwsup(s16 module
, u32 mask
)
124 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO
, module
, mask
);
127 void omap3xxx_cm_clkdm_force_sleep(s16 module
, u32 mask
)
129 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP
, module
, mask
);
132 void omap3xxx_cm_clkdm_force_wakeup(s16 module
, u32 mask
)
134 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP
, module
, mask
);
138 * DPLL autoidle control
141 static void _omap2xxx_set_dpll_autoidle(u8 m
)
145 v
= omap2_cm_read_mod_reg(PLL_MOD
, CM_AUTOIDLE
);
146 v
&= ~OMAP24XX_AUTO_DPLL_MASK
;
147 v
|= m
<< OMAP24XX_AUTO_DPLL_SHIFT
;
148 omap2_cm_write_mod_reg(v
, PLL_MOD
, CM_AUTOIDLE
);
151 void omap2xxx_cm_set_dpll_disable_autoidle(void)
153 _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP
);
156 void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
158 _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE
);
162 * APLL autoidle control
165 static void _omap2xxx_set_apll_autoidle(u8 m
, u32 mask
)
169 v
= omap2_cm_read_mod_reg(PLL_MOD
, CM_AUTOIDLE
);
171 v
|= m
<< __ffs(mask
);
172 omap2_cm_write_mod_reg(v
, PLL_MOD
, CM_AUTOIDLE
);
175 void omap2xxx_cm_set_apll54_disable_autoidle(void)
177 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP
,
178 OMAP24XX_AUTO_54M_MASK
);
181 void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
183 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE
,
184 OMAP24XX_AUTO_54M_MASK
);
187 void omap2xxx_cm_set_apll96_disable_autoidle(void)
189 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP
,
190 OMAP24XX_AUTO_96M_MASK
);
193 void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
195 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE
,
196 OMAP24XX_AUTO_96M_MASK
);
204 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
205 * @prcm_mod: PRCM module offset
206 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
207 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
211 int omap2_cm_wait_module_ready(s16 prcm_mod
, u8 idlest_id
, u8 idlest_shift
)
217 if (!idlest_id
|| (idlest_id
> ARRAY_SIZE(cm_idlest_offs
)))
220 cm_idlest_reg
= cm_idlest_offs
[idlest_id
- 1];
222 mask
= 1 << idlest_shift
;
224 if (cpu_is_omap24xx())
226 else if (cpu_is_omap34xx())
231 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod
, cm_idlest_reg
) & mask
) == ena
),
232 MAX_MODULE_READY_TIME
, i
);
234 return (i
< MAX_MODULE_READY_TIME
) ? 0 : -EBUSY
;
238 * Context save/restore code - OMAP3 only
240 #ifdef CONFIG_ARCH_OMAP3
241 struct omap3_cm_regs
{
250 u32 emu_cm_clkstctrl
;
252 u32 pll_cm_autoidle2
;
258 u32 iva2_cm_clken_pll
;
266 u32 usbhost_cm_fclken
;
275 u32 usbhost_cm_iclken
;
276 u32 iva2_cm_autoidle2
;
277 u32 mpu_cm_autoidle2
;
278 u32 iva2_cm_clkstctrl
;
279 u32 mpu_cm_clkstctrl
;
280 u32 core_cm_clkstctrl
;
281 u32 sgx_cm_clkstctrl
;
282 u32 dss_cm_clkstctrl
;
283 u32 cam_cm_clkstctrl
;
284 u32 per_cm_clkstctrl
;
285 u32 neon_cm_clkstctrl
;
286 u32 usbhost_cm_clkstctrl
;
287 u32 core_cm_autoidle1
;
288 u32 core_cm_autoidle2
;
289 u32 core_cm_autoidle3
;
290 u32 wkup_cm_autoidle
;
294 u32 usbhost_cm_autoidle
;
299 u32 usbhost_cm_sleepdep
;
303 static struct omap3_cm_regs cm_context
;
305 void omap3_cm_save_context(void)
307 cm_context
.iva2_cm_clksel1
=
308 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, CM_CLKSEL1
);
309 cm_context
.iva2_cm_clksel2
=
310 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, CM_CLKSEL2
);
311 cm_context
.cm_sysconfig
= __raw_readl(OMAP3430_CM_SYSCONFIG
);
312 cm_context
.sgx_cm_clksel
=
313 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD
, CM_CLKSEL
);
314 cm_context
.dss_cm_clksel
=
315 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD
, CM_CLKSEL
);
316 cm_context
.cam_cm_clksel
=
317 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD
, CM_CLKSEL
);
318 cm_context
.per_cm_clksel
=
319 omap2_cm_read_mod_reg(OMAP3430_PER_MOD
, CM_CLKSEL
);
320 cm_context
.emu_cm_clksel
=
321 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD
, CM_CLKSEL1
);
322 cm_context
.emu_cm_clkstctrl
=
323 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD
, OMAP2_CM_CLKSTCTRL
);
325 * As per erratum i671, ROM code does not respect the PER DPLL
326 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
327 * In this case, even though this register has been saved in
328 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
329 * by ourselves. So, we need to save it anyway.
331 cm_context
.pll_cm_autoidle
=
332 omap2_cm_read_mod_reg(PLL_MOD
, CM_AUTOIDLE
);
333 cm_context
.pll_cm_autoidle2
=
334 omap2_cm_read_mod_reg(PLL_MOD
, CM_AUTOIDLE2
);
335 cm_context
.pll_cm_clksel4
=
336 omap2_cm_read_mod_reg(PLL_MOD
, OMAP3430ES2_CM_CLKSEL4
);
337 cm_context
.pll_cm_clksel5
=
338 omap2_cm_read_mod_reg(PLL_MOD
, OMAP3430ES2_CM_CLKSEL5
);
339 cm_context
.pll_cm_clken2
=
340 omap2_cm_read_mod_reg(PLL_MOD
, OMAP3430ES2_CM_CLKEN2
);
341 cm_context
.cm_polctrl
= __raw_readl(OMAP3430_CM_POLCTRL
);
342 cm_context
.iva2_cm_fclken
=
343 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, CM_FCLKEN
);
344 cm_context
.iva2_cm_clken_pll
=
345 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKEN_PLL
);
346 cm_context
.core_cm_fclken1
=
347 omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
348 cm_context
.core_cm_fclken3
=
349 omap2_cm_read_mod_reg(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
);
350 cm_context
.sgx_cm_fclken
=
351 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD
, CM_FCLKEN
);
352 cm_context
.wkup_cm_fclken
=
353 omap2_cm_read_mod_reg(WKUP_MOD
, CM_FCLKEN
);
354 cm_context
.dss_cm_fclken
=
355 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD
, CM_FCLKEN
);
356 cm_context
.cam_cm_fclken
=
357 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD
, CM_FCLKEN
);
358 cm_context
.per_cm_fclken
=
359 omap2_cm_read_mod_reg(OMAP3430_PER_MOD
, CM_FCLKEN
);
360 cm_context
.usbhost_cm_fclken
=
361 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
);
362 cm_context
.core_cm_iclken1
=
363 omap2_cm_read_mod_reg(CORE_MOD
, CM_ICLKEN1
);
364 cm_context
.core_cm_iclken2
=
365 omap2_cm_read_mod_reg(CORE_MOD
, CM_ICLKEN2
);
366 cm_context
.core_cm_iclken3
=
367 omap2_cm_read_mod_reg(CORE_MOD
, CM_ICLKEN3
);
368 cm_context
.sgx_cm_iclken
=
369 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD
, CM_ICLKEN
);
370 cm_context
.wkup_cm_iclken
=
371 omap2_cm_read_mod_reg(WKUP_MOD
, CM_ICLKEN
);
372 cm_context
.dss_cm_iclken
=
373 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD
, CM_ICLKEN
);
374 cm_context
.cam_cm_iclken
=
375 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD
, CM_ICLKEN
);
376 cm_context
.per_cm_iclken
=
377 omap2_cm_read_mod_reg(OMAP3430_PER_MOD
, CM_ICLKEN
);
378 cm_context
.usbhost_cm_iclken
=
379 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
);
380 cm_context
.iva2_cm_autoidle2
=
381 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, CM_AUTOIDLE2
);
382 cm_context
.mpu_cm_autoidle2
=
383 omap2_cm_read_mod_reg(MPU_MOD
, CM_AUTOIDLE2
);
384 cm_context
.iva2_cm_clkstctrl
=
385 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, OMAP2_CM_CLKSTCTRL
);
386 cm_context
.mpu_cm_clkstctrl
=
387 omap2_cm_read_mod_reg(MPU_MOD
, OMAP2_CM_CLKSTCTRL
);
388 cm_context
.core_cm_clkstctrl
=
389 omap2_cm_read_mod_reg(CORE_MOD
, OMAP2_CM_CLKSTCTRL
);
390 cm_context
.sgx_cm_clkstctrl
=
391 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD
, OMAP2_CM_CLKSTCTRL
);
392 cm_context
.dss_cm_clkstctrl
=
393 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD
, OMAP2_CM_CLKSTCTRL
);
394 cm_context
.cam_cm_clkstctrl
=
395 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD
, OMAP2_CM_CLKSTCTRL
);
396 cm_context
.per_cm_clkstctrl
=
397 omap2_cm_read_mod_reg(OMAP3430_PER_MOD
, OMAP2_CM_CLKSTCTRL
);
398 cm_context
.neon_cm_clkstctrl
=
399 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD
, OMAP2_CM_CLKSTCTRL
);
400 cm_context
.usbhost_cm_clkstctrl
=
401 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD
,
403 cm_context
.core_cm_autoidle1
=
404 omap2_cm_read_mod_reg(CORE_MOD
, CM_AUTOIDLE1
);
405 cm_context
.core_cm_autoidle2
=
406 omap2_cm_read_mod_reg(CORE_MOD
, CM_AUTOIDLE2
);
407 cm_context
.core_cm_autoidle3
=
408 omap2_cm_read_mod_reg(CORE_MOD
, CM_AUTOIDLE3
);
409 cm_context
.wkup_cm_autoidle
=
410 omap2_cm_read_mod_reg(WKUP_MOD
, CM_AUTOIDLE
);
411 cm_context
.dss_cm_autoidle
=
412 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD
, CM_AUTOIDLE
);
413 cm_context
.cam_cm_autoidle
=
414 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD
, CM_AUTOIDLE
);
415 cm_context
.per_cm_autoidle
=
416 omap2_cm_read_mod_reg(OMAP3430_PER_MOD
, CM_AUTOIDLE
);
417 cm_context
.usbhost_cm_autoidle
=
418 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD
, CM_AUTOIDLE
);
419 cm_context
.sgx_cm_sleepdep
=
420 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD
,
421 OMAP3430_CM_SLEEPDEP
);
422 cm_context
.dss_cm_sleepdep
=
423 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD
, OMAP3430_CM_SLEEPDEP
);
424 cm_context
.cam_cm_sleepdep
=
425 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD
, OMAP3430_CM_SLEEPDEP
);
426 cm_context
.per_cm_sleepdep
=
427 omap2_cm_read_mod_reg(OMAP3430_PER_MOD
, OMAP3430_CM_SLEEPDEP
);
428 cm_context
.usbhost_cm_sleepdep
=
429 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD
,
430 OMAP3430_CM_SLEEPDEP
);
431 cm_context
.cm_clkout_ctrl
=
432 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD
,
433 OMAP3_CM_CLKOUT_CTRL_OFFSET
);
436 void omap3_cm_restore_context(void)
438 omap2_cm_write_mod_reg(cm_context
.iva2_cm_clksel1
, OMAP3430_IVA2_MOD
,
440 omap2_cm_write_mod_reg(cm_context
.iva2_cm_clksel2
, OMAP3430_IVA2_MOD
,
442 __raw_writel(cm_context
.cm_sysconfig
, OMAP3430_CM_SYSCONFIG
);
443 omap2_cm_write_mod_reg(cm_context
.sgx_cm_clksel
, OMAP3430ES2_SGX_MOD
,
445 omap2_cm_write_mod_reg(cm_context
.dss_cm_clksel
, OMAP3430_DSS_MOD
,
447 omap2_cm_write_mod_reg(cm_context
.cam_cm_clksel
, OMAP3430_CAM_MOD
,
449 omap2_cm_write_mod_reg(cm_context
.per_cm_clksel
, OMAP3430_PER_MOD
,
451 omap2_cm_write_mod_reg(cm_context
.emu_cm_clksel
, OMAP3430_EMU_MOD
,
453 omap2_cm_write_mod_reg(cm_context
.emu_cm_clkstctrl
, OMAP3430_EMU_MOD
,
456 * As per erratum i671, ROM code does not respect the PER DPLL
457 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
458 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
460 omap2_cm_write_mod_reg(cm_context
.pll_cm_autoidle
, PLL_MOD
,
462 omap2_cm_write_mod_reg(cm_context
.pll_cm_autoidle2
, PLL_MOD
,
464 omap2_cm_write_mod_reg(cm_context
.pll_cm_clksel4
, PLL_MOD
,
465 OMAP3430ES2_CM_CLKSEL4
);
466 omap2_cm_write_mod_reg(cm_context
.pll_cm_clksel5
, PLL_MOD
,
467 OMAP3430ES2_CM_CLKSEL5
);
468 omap2_cm_write_mod_reg(cm_context
.pll_cm_clken2
, PLL_MOD
,
469 OMAP3430ES2_CM_CLKEN2
);
470 __raw_writel(cm_context
.cm_polctrl
, OMAP3430_CM_POLCTRL
);
471 omap2_cm_write_mod_reg(cm_context
.iva2_cm_fclken
, OMAP3430_IVA2_MOD
,
473 omap2_cm_write_mod_reg(cm_context
.iva2_cm_clken_pll
, OMAP3430_IVA2_MOD
,
474 OMAP3430_CM_CLKEN_PLL
);
475 omap2_cm_write_mod_reg(cm_context
.core_cm_fclken1
, CORE_MOD
,
477 omap2_cm_write_mod_reg(cm_context
.core_cm_fclken3
, CORE_MOD
,
478 OMAP3430ES2_CM_FCLKEN3
);
479 omap2_cm_write_mod_reg(cm_context
.sgx_cm_fclken
, OMAP3430ES2_SGX_MOD
,
481 omap2_cm_write_mod_reg(cm_context
.wkup_cm_fclken
, WKUP_MOD
, CM_FCLKEN
);
482 omap2_cm_write_mod_reg(cm_context
.dss_cm_fclken
, OMAP3430_DSS_MOD
,
484 omap2_cm_write_mod_reg(cm_context
.cam_cm_fclken
, OMAP3430_CAM_MOD
,
486 omap2_cm_write_mod_reg(cm_context
.per_cm_fclken
, OMAP3430_PER_MOD
,
488 omap2_cm_write_mod_reg(cm_context
.usbhost_cm_fclken
,
489 OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
);
490 omap2_cm_write_mod_reg(cm_context
.core_cm_iclken1
, CORE_MOD
,
492 omap2_cm_write_mod_reg(cm_context
.core_cm_iclken2
, CORE_MOD
,
494 omap2_cm_write_mod_reg(cm_context
.core_cm_iclken3
, CORE_MOD
,
496 omap2_cm_write_mod_reg(cm_context
.sgx_cm_iclken
, OMAP3430ES2_SGX_MOD
,
498 omap2_cm_write_mod_reg(cm_context
.wkup_cm_iclken
, WKUP_MOD
, CM_ICLKEN
);
499 omap2_cm_write_mod_reg(cm_context
.dss_cm_iclken
, OMAP3430_DSS_MOD
,
501 omap2_cm_write_mod_reg(cm_context
.cam_cm_iclken
, OMAP3430_CAM_MOD
,
503 omap2_cm_write_mod_reg(cm_context
.per_cm_iclken
, OMAP3430_PER_MOD
,
505 omap2_cm_write_mod_reg(cm_context
.usbhost_cm_iclken
,
506 OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
);
507 omap2_cm_write_mod_reg(cm_context
.iva2_cm_autoidle2
, OMAP3430_IVA2_MOD
,
509 omap2_cm_write_mod_reg(cm_context
.mpu_cm_autoidle2
, MPU_MOD
,
511 omap2_cm_write_mod_reg(cm_context
.iva2_cm_clkstctrl
, OMAP3430_IVA2_MOD
,
513 omap2_cm_write_mod_reg(cm_context
.mpu_cm_clkstctrl
, MPU_MOD
,
515 omap2_cm_write_mod_reg(cm_context
.core_cm_clkstctrl
, CORE_MOD
,
517 omap2_cm_write_mod_reg(cm_context
.sgx_cm_clkstctrl
, OMAP3430ES2_SGX_MOD
,
519 omap2_cm_write_mod_reg(cm_context
.dss_cm_clkstctrl
, OMAP3430_DSS_MOD
,
521 omap2_cm_write_mod_reg(cm_context
.cam_cm_clkstctrl
, OMAP3430_CAM_MOD
,
523 omap2_cm_write_mod_reg(cm_context
.per_cm_clkstctrl
, OMAP3430_PER_MOD
,
525 omap2_cm_write_mod_reg(cm_context
.neon_cm_clkstctrl
, OMAP3430_NEON_MOD
,
527 omap2_cm_write_mod_reg(cm_context
.usbhost_cm_clkstctrl
,
528 OMAP3430ES2_USBHOST_MOD
, OMAP2_CM_CLKSTCTRL
);
529 omap2_cm_write_mod_reg(cm_context
.core_cm_autoidle1
, CORE_MOD
,
531 omap2_cm_write_mod_reg(cm_context
.core_cm_autoidle2
, CORE_MOD
,
533 omap2_cm_write_mod_reg(cm_context
.core_cm_autoidle3
, CORE_MOD
,
535 omap2_cm_write_mod_reg(cm_context
.wkup_cm_autoidle
, WKUP_MOD
,
537 omap2_cm_write_mod_reg(cm_context
.dss_cm_autoidle
, OMAP3430_DSS_MOD
,
539 omap2_cm_write_mod_reg(cm_context
.cam_cm_autoidle
, OMAP3430_CAM_MOD
,
541 omap2_cm_write_mod_reg(cm_context
.per_cm_autoidle
, OMAP3430_PER_MOD
,
543 omap2_cm_write_mod_reg(cm_context
.usbhost_cm_autoidle
,
544 OMAP3430ES2_USBHOST_MOD
, CM_AUTOIDLE
);
545 omap2_cm_write_mod_reg(cm_context
.sgx_cm_sleepdep
, OMAP3430ES2_SGX_MOD
,
546 OMAP3430_CM_SLEEPDEP
);
547 omap2_cm_write_mod_reg(cm_context
.dss_cm_sleepdep
, OMAP3430_DSS_MOD
,
548 OMAP3430_CM_SLEEPDEP
);
549 omap2_cm_write_mod_reg(cm_context
.cam_cm_sleepdep
, OMAP3430_CAM_MOD
,
550 OMAP3430_CM_SLEEPDEP
);
551 omap2_cm_write_mod_reg(cm_context
.per_cm_sleepdep
, OMAP3430_PER_MOD
,
552 OMAP3430_CM_SLEEPDEP
);
553 omap2_cm_write_mod_reg(cm_context
.usbhost_cm_sleepdep
,
554 OMAP3430ES2_USBHOST_MOD
, OMAP3430_CM_SLEEPDEP
);
555 omap2_cm_write_mod_reg(cm_context
.cm_clkout_ctrl
, OMAP3430_CCR_MOD
,
556 OMAP3_CM_CLKOUT_CTRL_OFFSET
);