arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17
  18 #include "soc.h"
  19 #include "iomap.h"
  20 #include "common.h"
  21 #include "cm-regbits-34xx.h"
  22 #include "prm-regbits-34xx.h"
  23 #include "prm3xxx.h"
  24 #include "cm3xxx.h"
  25 #include "sdrc.h"
  26 #include "pm.h"
  27 #include "control.h"
  28
  29 /* Used by omap3_ctrl_save_padconf() */
  30 #define START_PADCONF_SAVE              0x2
  31 #define PADCONF_SAVE_DONE               0x1
  32
  33 static void __iomem *omap2_ctrl_base;
  34 static void __iomem *omap4_ctrl_pad_base;
  35
  36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  37 struct omap3_scratchpad {
  38         u32 boot_config_ptr;
  39         u32 public_restore_ptr;
  40         u32 secure_ram_restore_ptr;
  41         u32 sdrc_module_semaphore;
  42         u32 prcm_block_offset;
  43         u32 sdrc_block_offset;
  44 };
  45
  46 struct omap3_scratchpad_prcm_block {
  47         u32 prm_clksrc_ctrl;
  48         u32 prm_clksel;
  49         u32 cm_clksel_core;
  50         u32 cm_clksel_wkup;
  51         u32 cm_clken_pll;
  52         u32 cm_autoidle_pll;
  53         u32 cm_clksel1_pll;
  54         u32 cm_clksel2_pll;
  55         u32 cm_clksel3_pll;
  56         u32 cm_clken_pll_mpu;
  57         u32 cm_autoidle_pll_mpu;
  58         u32 cm_clksel1_pll_mpu;
  59         u32 cm_clksel2_pll_mpu;
  60         u32 prcm_block_size;
  61 };
  62
  63 struct omap3_scratchpad_sdrc_block {
  64         u16 sysconfig;
  65         u16 cs_cfg;
  66         u16 sharing;
  67         u16 err_type;
  68         u32 dll_a_ctrl;
  69         u32 dll_b_ctrl;
  70         u32 power;
  71         u32 cs_0;
  72         u32 mcfg_0;
  73         u16 mr_0;
  74         u16 emr_1_0;
  75         u16 emr_2_0;
  76         u16 emr_3_0;
  77         u32 actim_ctrla_0;
  78         u32 actim_ctrlb_0;
  79         u32 rfr_ctrl_0;
  80         u32 cs_1;
  81         u32 mcfg_1;
  82         u16 mr_1;
  83         u16 emr_1_1;
  84         u16 emr_2_1;
  85         u16 emr_3_1;
  86         u32 actim_ctrla_1;
  87         u32 actim_ctrlb_1;
  88         u32 rfr_ctrl_1;
  89         u16 dcdl_1_ctrl;
  90         u16 dcdl_2_ctrl;
  91         u32 flags;
  92         u32 block_size;
  93 };
  94
  95 void *omap3_secure_ram_storage;
  96
  97 /*
  98  * This is used to store ARM registers in SDRAM before attempting
  99  * an MPU OFF. The save and restore happens from the SRAM sleep code.
 100  * The address is stored in scratchpad, so that it can be used
 101  * during the restore path.
 102  */
 103 u32 omap3_arm_context[128];
 104
 105 struct omap3_control_regs {
 106         u32 sysconfig;
 107         u32 devconf0;
 108         u32 mem_dftrw0;
 109         u32 mem_dftrw1;
 110         u32 msuspendmux_0;
 111         u32 msuspendmux_1;
 112         u32 msuspendmux_2;
 113         u32 msuspendmux_3;
 114         u32 msuspendmux_4;
 115         u32 msuspendmux_5;
 116         u32 sec_ctrl;
 117         u32 devconf1;
 118         u32 csirxfe;
 119         u32 iva2_bootaddr;
 120         u32 iva2_bootmod;
 121         u32 debobs_0;
 122         u32 debobs_1;
 123         u32 debobs_2;
 124         u32 debobs_3;
 125         u32 debobs_4;
 126         u32 debobs_5;
 127         u32 debobs_6;
 128         u32 debobs_7;
 129         u32 debobs_8;
 130         u32 prog_io0;
 131         u32 prog_io1;
 132         u32 dss_dpll_spreading;
 133         u32 core_dpll_spreading;
 134         u32 per_dpll_spreading;
 135         u32 usbhost_dpll_spreading;
 136         u32 pbias_lite;
 137         u32 temp_sensor;
 138         u32 sramldo4;
 139         u32 sramldo5;
 140         u32 csi;
 141         u32 padconf_sys_nirq;
 142 };
 143
 144 static struct omap3_control_regs control_context;
 145 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 146
 147 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 148 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 149
 150 void __init omap2_set_globals_control(void __iomem *ctrl,
 151                                       void __iomem *ctrl_pad)
 152 {
 153         omap2_ctrl_base = ctrl;
 154         omap4_ctrl_pad_base = ctrl_pad;
 155 }
 156
 157 void __iomem *omap_ctrl_base_get(void)
 158 {
 159         return omap2_ctrl_base;
 160 }
 161
 162 u8 omap_ctrl_readb(u16 offset)
 163 {
 164         return __raw_readb(OMAP_CTRL_REGADDR(offset));
 165 }
 166
 167 u16 omap_ctrl_readw(u16 offset)
 168 {
 169         return __raw_readw(OMAP_CTRL_REGADDR(offset));
 170 }
 171
 172 u32 omap_ctrl_readl(u16 offset)
 173 {
 174         return __raw_readl(OMAP_CTRL_REGADDR(offset));
 175 }
 176
 177 void omap_ctrl_writeb(u8 val, u16 offset)
 178 {
 179         __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
 180 }
 181
 182 void omap_ctrl_writew(u16 val, u16 offset)
 183 {
 184         __raw_writew(val, OMAP_CTRL_REGADDR(offset));
 185 }
 186
 187 void omap_ctrl_writel(u32 val, u16 offset)
 188 {
 189         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 190 }
 191
 192 /*
 193  * On OMAP4 control pad are not addressable from control
 194  * core base. So the common omap_ctrl_read/write APIs breaks
 195  * Hence export separate APIs to manage the omap4 pad control
 196  * registers. This APIs will work only for OMAP4
 197  */
 198
 199 u32 omap4_ctrl_pad_readl(u16 offset)
 200 {
 201         return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
 202 }
 203
 204 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 205 {
 206         __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
 207 }
 208
 209 #ifdef CONFIG_ARCH_OMAP3
 210
 211 /**
 212  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 213  * @bootmode: 8-bit value to pass to some boot code
 214  *
 215  * Set the bootmode in the scratchpad RAM.  This is used after the
 216  * system restarts.  Not sure what actually uses this - it may be the
 217  * bootloader, rather than the boot ROM - contrary to the preserved
 218  * comment below.  No return value.
 219  */
 220 void omap3_ctrl_write_boot_mode(u8 bootmode)
 221 {
 222         u32 l;
 223
 224         l = ('B' << 24) | ('M' << 16) | bootmode;
 225
 226         /*
 227          * Reserve the first word in scratchpad for communicating
 228          * with the boot ROM. A pointer to a data structure
 229          * describing the boot process can be stored there,
 230          * cf. OMAP34xx TRM, Initialization / Software Booting
 231          * Configuration.
 232          *
 233          * XXX This should use some omap_ctrl_writel()-type function
 234          */
 235         __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 236 }
 237
 238 #endif
 239
 240 /**
 241  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
 242  * @bootaddr: physical address of the boot loader
 243  *
 244  * Set boot address for the boot loader of a supported processor
 245  * when a power ON sequence occurs.
 246  */
 247 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
 248 {
 249         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
 250                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
 251                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 252                      soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 253                      0;
 254
 255         if (!offset) {
 256                 pr_err("%s: unsupported omap type\n", __func__);
 257                 return;
 258         }
 259
 260         omap_ctrl_writel(bootaddr, offset);
 261 }
 262
 263 /**
 264  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
 265  * @bootmode: 8-bit value to pass to some boot code
 266  *
 267  * Sets boot mode for the boot loader of a supported processor
 268  * when a power ON sequence occurs.
 269  */
 270 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
 271 {
 272         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
 273                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
 274                      0;
 275
 276         if (!offset) {
 277                 pr_err("%s: unsupported omap type\n", __func__);
 278                 return;
 279         }
 280
 281         omap_ctrl_writel(bootmode, offset);
 282 }
 283
 284 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 285 /*
 286  * Clears the scratchpad contents in case of cold boot-
 287  * called during bootup
 288  */
 289 void omap3_clear_scratchpad_contents(void)
 290 {
 291         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 292         void __iomem *v_addr;
 293         u32 offset = 0;
 294         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 295         if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
 296             OMAP3430_GLOBAL_COLD_RST_MASK) {
 297                 for ( ; offset <= max_offset; offset += 0x4)
 298                         __raw_writel(0x0, (v_addr + offset));
 299                 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
 300                                            OMAP3430_GR_MOD,
 301                                            OMAP3_PRM_RSTST_OFFSET);
 302         }
 303 }
 304
 305 /* Populate the scratchpad structure with restore structure */
 306 void omap3_save_scratchpad_contents(void)
 307 {
 308         void  __iomem *scratchpad_address;
 309         u32 arm_context_addr;
 310         struct omap3_scratchpad scratchpad_contents;
 311         struct omap3_scratchpad_prcm_block prcm_block_contents;
 312         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 313
 314         /*
 315          * Populate the Scratchpad contents
 316          *
 317          * The "get_*restore_pointer" functions are used to provide a
 318          * physical restore address where the ROM code jumps while waking
 319          * up from MPU OFF/OSWR state.
 320          * The restore pointer is stored into the scratchpad.
 321          */
 322         scratchpad_contents.boot_config_ptr = 0x0;
 323         if (cpu_is_omap3630())
 324                 scratchpad_contents.public_restore_ptr =
 325                         virt_to_phys(omap3_restore_3630);
 326         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 327                                         omap_rev() != OMAP3430_REV_ES3_1)
 328                 scratchpad_contents.public_restore_ptr =
 329                         virt_to_phys(omap3_restore);
 330         else
 331                 scratchpad_contents.public_restore_ptr =
 332                         virt_to_phys(omap3_restore_es3);
 333
 334         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 335                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 336         else
 337                 scratchpad_contents.secure_ram_restore_ptr =
 338                         (u32) __pa(omap3_secure_ram_storage);
 339         scratchpad_contents.sdrc_module_semaphore = 0x0;
 340         scratchpad_contents.prcm_block_offset = 0x2C;
 341         scratchpad_contents.sdrc_block_offset = 0x64;
 342
 343         /* Populate the PRCM block contents */
 344         prcm_block_contents.prm_clksrc_ctrl =
 345                 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 346                                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 347         prcm_block_contents.prm_clksel =
 348                 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
 349                                        OMAP3_PRM_CLKSEL_OFFSET);
 350         prcm_block_contents.cm_clksel_core =
 351                         omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
 352         prcm_block_contents.cm_clksel_wkup =
 353                         omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
 354         prcm_block_contents.cm_clken_pll =
 355                         omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 356         /*
 357          * As per erratum i671, ROM code does not respect the PER DPLL
 358          * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
 359          * Then,  in anycase, clear these bits to avoid extra latencies.
 360          */
 361         prcm_block_contents.cm_autoidle_pll =
 362                         omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
 363                         ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
 364         prcm_block_contents.cm_clksel1_pll =
 365                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 366         prcm_block_contents.cm_clksel2_pll =
 367                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
 368         prcm_block_contents.cm_clksel3_pll =
 369                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
 370         prcm_block_contents.cm_clken_pll_mpu =
 371                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
 372         prcm_block_contents.cm_autoidle_pll_mpu =
 373                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 374         prcm_block_contents.cm_clksel1_pll_mpu =
 375                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
 376         prcm_block_contents.cm_clksel2_pll_mpu =
 377                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
 378         prcm_block_contents.prcm_block_size = 0x0;
 379
 380         /* Populate the SDRC block contents */
 381         sdrc_block_contents.sysconfig =
 382                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 383         sdrc_block_contents.cs_cfg =
 384                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 385         sdrc_block_contents.sharing =
 386                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 387         sdrc_block_contents.err_type =
 388                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 389         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 390         sdrc_block_contents.dll_b_ctrl = 0x0;
 391         /*
 392          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 393          * be programed to issue automatic self refresh on timeout
 394          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 395          */
 396         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 397                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 398                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 399                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 400                                 SDRC_POWER_CLKCTRL_MASK)) |
 401                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 402                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 403         else
 404                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 405
 406         sdrc_block_contents.cs_0 = 0x0;
 407         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 408         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 409         sdrc_block_contents.emr_1_0 = 0x0;
 410         sdrc_block_contents.emr_2_0 = 0x0;
 411         sdrc_block_contents.emr_3_0 = 0x0;
 412         sdrc_block_contents.actim_ctrla_0 =
 413                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 414         sdrc_block_contents.actim_ctrlb_0 =
 415                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 416         sdrc_block_contents.rfr_ctrl_0 =
 417                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 418         sdrc_block_contents.cs_1 = 0x0;
 419         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 420         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 421         sdrc_block_contents.emr_1_1 = 0x0;
 422         sdrc_block_contents.emr_2_1 = 0x0;
 423         sdrc_block_contents.emr_3_1 = 0x0;
 424         sdrc_block_contents.actim_ctrla_1 =
 425                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 426         sdrc_block_contents.actim_ctrlb_1 =
 427                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 428         sdrc_block_contents.rfr_ctrl_1 =
 429                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 430         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 431         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 432         sdrc_block_contents.flags = 0x0;
 433         sdrc_block_contents.block_size = 0x0;
 434
 435         arm_context_addr = virt_to_phys(omap3_arm_context);
 436
 437         /* Copy all the contents to the scratchpad location */
 438         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 439         memcpy_toio(scratchpad_address, &scratchpad_contents,
 440                  sizeof(scratchpad_contents));
 441         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 442         memcpy_toio(scratchpad_address +
 443                 scratchpad_contents.prcm_block_offset,
 444                 &prcm_block_contents, sizeof(prcm_block_contents));
 445         memcpy_toio(scratchpad_address +
 446                 scratchpad_contents.sdrc_block_offset,
 447                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 448         /*
 449          * Copies the address of the location in SDRAM where ARM
 450          * registers get saved during a MPU OFF transition.
 451          */
 452         memcpy_toio(scratchpad_address +
 453                 scratchpad_contents.sdrc_block_offset +
 454                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 455 }
 456
 457 void omap3_control_save_context(void)
 458 {
 459         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 460         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 461         control_context.mem_dftrw0 =
 462                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 463         control_context.mem_dftrw1 =
 464                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 465         control_context.msuspendmux_0 =
 466                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 467         control_context.msuspendmux_1 =
 468                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 469         control_context.msuspendmux_2 =
 470                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 471         control_context.msuspendmux_3 =
 472                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 473         control_context.msuspendmux_4 =
 474                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 475         control_context.msuspendmux_5 =
 476                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 477         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 478         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 479         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 480         control_context.iva2_bootaddr =
 481                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 482         control_context.iva2_bootmod =
 483                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 484         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 485         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 486         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 487         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 488         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 489         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 490         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 491         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 492         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 493         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 494         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 495         control_context.dss_dpll_spreading =
 496                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 497         control_context.core_dpll_spreading =
 498                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 499         control_context.per_dpll_spreading =
 500                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 501         control_context.usbhost_dpll_spreading =
 502                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 503         control_context.pbias_lite =
 504                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 505         control_context.temp_sensor =
 506                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 507         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 508         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 509         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 510         control_context.padconf_sys_nirq =
 511                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 512         return;
 513 }
 514
 515 void omap3_control_restore_context(void)
 516 {
 517         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 518         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 519         omap_ctrl_writel(control_context.mem_dftrw0,
 520                                         OMAP343X_CONTROL_MEM_DFTRW0);
 521         omap_ctrl_writel(control_context.mem_dftrw1,
 522                                         OMAP343X_CONTROL_MEM_DFTRW1);
 523         omap_ctrl_writel(control_context.msuspendmux_0,
 524                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 525         omap_ctrl_writel(control_context.msuspendmux_1,
 526                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 527         omap_ctrl_writel(control_context.msuspendmux_2,
 528                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 529         omap_ctrl_writel(control_context.msuspendmux_3,
 530                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 531         omap_ctrl_writel(control_context.msuspendmux_4,
 532                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 533         omap_ctrl_writel(control_context.msuspendmux_5,
 534                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 535         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 536         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 537         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 538         omap_ctrl_writel(control_context.iva2_bootaddr,
 539                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 540         omap_ctrl_writel(control_context.iva2_bootmod,
 541                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 542         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 543         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 544         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 545         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 546         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 547         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 548         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 549         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 550         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 551         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 552         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 553         omap_ctrl_writel(control_context.dss_dpll_spreading,
 554                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 555         omap_ctrl_writel(control_context.core_dpll_spreading,
 556                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 557         omap_ctrl_writel(control_context.per_dpll_spreading,
 558                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 559         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 560                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 561         omap_ctrl_writel(control_context.pbias_lite,
 562                                         OMAP343X_CONTROL_PBIAS_LITE);
 563         omap_ctrl_writel(control_context.temp_sensor,
 564                                         OMAP343X_CONTROL_TEMP_SENSOR);
 565         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 566         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 567         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 568         omap_ctrl_writel(control_context.padconf_sys_nirq,
 569                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 570         return;
 571 }
 572
 573 void omap3630_ctrl_disable_rta(void)
 574 {
 575         if (!cpu_is_omap3630())
 576                 return;
 577         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
 578 }
 579
 580 /**
 581  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
 582  *
 583  * Tell the SCM to start saving the padconf registers, then wait for
 584  * the process to complete.  Returns 0 unconditionally, although it
 585  * should also eventually be able to return -ETIMEDOUT, if the save
 586  * does not complete.
 587  *
 588  * XXX This function is missing a timeout.  What should it be?
 589  */
 590 int omap3_ctrl_save_padconf(void)
 591 {
 592         u32 cpo;
 593
 594         /* Save the padconf registers */
 595         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 596         cpo |= START_PADCONF_SAVE;
 597         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
 598
 599         /* wait for the save to complete */
 600         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 601                  & PADCONF_SAVE_DONE))
 602                 udelay(1);
 603
 604         return 0;
 605 }
 606
 607 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */