arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27
  28 #include <plat/prcm.h>
  29 #include <plat/irqs.h>
  30 #include <plat/powerdomain.h>
  31 #include <plat/clockdomain.h>
  32 #include <plat/control.h>
  33 #include <plat/serial.h>
  34
  35 #include "pm.h"
  36
  37 #ifdef CONFIG_CPU_IDLE
  38
  39 #define OMAP3_MAX_STATES 7
  40 #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
  41 #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
  42 #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
  43 #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
  44 #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
  45 #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
  46 #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
  47
  48 struct omap3_processor_cx {
  49         u8 valid;
  50         u8 type;
  51         u32 sleep_latency;
  52         u32 wakeup_latency;
  53         u32 mpu_state;
  54         u32 core_state;
  55         u32 threshold;
  56         u32 flags;
  57 };
  58
  59 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
  60 struct omap3_processor_cx current_cx_state;
  61 struct powerdomain *mpu_pd, *core_pd;
  62
  63 static int omap3_idle_bm_check(void)
  64 {
  65         if (!omap3_can_sleep())
  66                 return 1;
  67         return 0;
  68 }
  69
  70 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  71                                 struct clockdomain *clkdm)
  72 {
  73         omap2_clkdm_allow_idle(clkdm);
  74         return 0;
  75 }
  76
  77 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  78                                 struct clockdomain *clkdm)
  79 {
  80         omap2_clkdm_deny_idle(clkdm);
  81         return 0;
  82 }
  83
  84 /**
  85  * omap3_enter_idle - Programs OMAP3 to enter the specified state
  86  * @dev: cpuidle device
  87  * @state: The target state to be programmed
  88  *
  89  * Called from the CPUidle framework to program the device to the
  90  * specified target state selected by the governor.
  91  */
  92 static int omap3_enter_idle(struct cpuidle_device *dev,
  93                         struct cpuidle_state *state)
  94 {
  95         struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
  96         struct timespec ts_preidle, ts_postidle, ts_idle;
  97         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
  98
  99         current_cx_state = *cx;
 100
 101         /* Used to keep track of the total time in idle */
 102         getnstimeofday(&ts_preidle);
 103
 104         local_irq_disable();
 105         local_fiq_disable();
 106
 107         if (!enable_off_mode) {
 108                 if (mpu_state < PWRDM_POWER_RET)
 109                         mpu_state = PWRDM_POWER_RET;
 110                 if (core_state < PWRDM_POWER_RET)
 111                         core_state = PWRDM_POWER_RET;
 112         }
 113
 114         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 115         pwrdm_set_next_pwrst(core_pd, core_state);
 116
 117         if (omap_irq_pending() || need_resched())
 118                 goto return_sleep_time;
 119
 120         if (cx->type == OMAP3_STATE_C1) {
 121                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 122                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 123         }
 124
 125         /* Execute ARM wfi */
 126         omap_sram_idle();
 127
 128         if (cx->type == OMAP3_STATE_C1) {
 129                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 130                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 131         }
 132
 133 return_sleep_time:
 134         getnstimeofday(&ts_postidle);
 135         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 136
 137         local_irq_enable();
 138         local_fiq_enable();
 139
 140         return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
 141 }
 142
 143 /**
 144  * omap3_enter_idle_bm - Checks for any bus activity
 145  * @dev: cpuidle device
 146  * @state: The target state to be programmed
 147  *
 148  * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 149  * function checks for any pending activity and then programs the
 150  * device to the specified or a safer state.
 151  */
 152 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 153                                struct cpuidle_state *state)
 154 {
 155         struct cpuidle_state *new_state = state;
 156
 157         if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
 158                 BUG_ON(!dev->safe_state);
 159                 new_state = dev->safe_state;
 160         }
 161
 162         dev->last_state = new_state;
 163         return omap3_enter_idle(dev, new_state);
 164 }
 165
 166 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 167
 168 /* omap3_init_power_states - Initialises the OMAP3 specific C states.
 169  *
 170  * Below is the desciption of each C state.
 171  *      C1 . MPU WFI + Core active
 172  *      C2 . MPU WFI + Core inactive
 173  *      C3 . MPU CSWR + Core inactive
 174  *      C4 . MPU OFF + Core inactive
 175  *      C5 . MPU CSWR + Core CSWR
 176  *      C6 . MPU OFF + Core CSWR
 177  *      C7 . MPU OFF + Core OFF
 178  */
 179 void omap_init_power_states(void)
 180 {
 181         /* C1 . MPU WFI + Core active */
 182         omap3_power_states[OMAP3_STATE_C1].valid = 1;
 183         omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
 184         omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
 185         omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
 186         omap3_power_states[OMAP3_STATE_C1].threshold = 5;
 187         omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
 188         omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
 189         omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
 190
 191         /* C2 . MPU WFI + Core inactive */
 192         omap3_power_states[OMAP3_STATE_C2].valid = 1;
 193         omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
 194         omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
 195         omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
 196         omap3_power_states[OMAP3_STATE_C2].threshold = 30;
 197         omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
 198         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
 199         omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
 200
 201         /* C3 . MPU CSWR + Core inactive */
 202         omap3_power_states[OMAP3_STATE_C3].valid = 1;
 203         omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
 204         omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
 205         omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
 206         omap3_power_states[OMAP3_STATE_C3].threshold = 300;
 207         omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
 208         omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
 209         omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
 210                                 CPUIDLE_FLAG_CHECK_BM;
 211
 212         /* C4 . MPU OFF + Core inactive */
 213         omap3_power_states[OMAP3_STATE_C4].valid = 1;
 214         omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
 215         omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
 216         omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
 217         omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
 218         omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
 219         omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
 220         omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
 221                                 CPUIDLE_FLAG_CHECK_BM;
 222
 223         /* C5 . MPU CSWR + Core CSWR*/
 224         omap3_power_states[OMAP3_STATE_C5].valid = 1;
 225         omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
 226         omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
 227         omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
 228         omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
 229         omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
 230         omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
 231         omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
 232                                 CPUIDLE_FLAG_CHECK_BM;
 233
 234         /* C6 . MPU OFF + Core CSWR */
 235         omap3_power_states[OMAP3_STATE_C6].valid = 1;
 236         omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
 237         omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
 238         omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
 239         omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
 240         omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
 241         omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
 242         omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
 243                                 CPUIDLE_FLAG_CHECK_BM;
 244
 245         /* C7 . MPU OFF + Core OFF */
 246         omap3_power_states[OMAP3_STATE_C7].valid = 1;
 247         omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
 248         omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
 249         omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
 250         omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
 251         omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
 252         omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
 253         omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
 254                                 CPUIDLE_FLAG_CHECK_BM;
 255 }
 256
 257 struct cpuidle_driver omap3_idle_driver = {
 258         .name =         "omap3_idle",
 259         .owner =        THIS_MODULE,
 260 };
 261
 262 /**
 263  * omap3_idle_init - Init routine for OMAP3 idle
 264  *
 265  * Registers the OMAP3 specific cpuidle driver with the cpuidle
 266  * framework with the valid set of states.
 267  */
 268 int __init omap3_idle_init(void)
 269 {
 270         int i, count = 0;
 271         struct omap3_processor_cx *cx;
 272         struct cpuidle_state *state;
 273         struct cpuidle_device *dev;
 274
 275         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 276         core_pd = pwrdm_lookup("core_pwrdm");
 277
 278         omap_init_power_states();
 279         cpuidle_register_driver(&omap3_idle_driver);
 280
 281         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 282
 283         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
 284                 cx = &omap3_power_states[i];
 285                 state = &dev->states[count];
 286
 287                 if (!cx->valid)
 288                         continue;
 289                 cpuidle_set_statedata(state, cx);
 290                 state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
 291                 state->target_residency = cx->threshold;
 292                 state->flags = cx->flags;
 293                 state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
 294                         omap3_enter_idle_bm : omap3_enter_idle;
 295                 if (cx->type == OMAP3_STATE_C1)
 296                         dev->safe_state = state;
 297                 sprintf(state->name, "C%d", count+1);
 298                 count++;
 299         }
 300
 301         if (!count)
 302                 return -EINVAL;
 303         dev->state_count = count;
 304
 305         if (cpuidle_register_device(dev)) {
 306                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 307                        __func__);
 308                 return -EIO;
 309         }
 310
 311         return 0;
 312 }
 313 #else
 314 int __init omap3_idle_init(void)
 315 {
 316         return 0;
 317 }
 318 #endif /* CONFIG_CPU_IDLE */