2 * linux/arch/arm/mach-omap2/devices.c
4 * OMAP2 platform device setup/initialization
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
17 #include <linux/clk.h>
19 #include <mach/hardware.h>
20 #include <asm/mach-types.h>
21 #include <asm/mach/map.h>
23 #include <plat/control.h>
25 #include <plat/board.h>
27 #include <mach/gpio.h>
32 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
34 static struct resource cam_resources
[] = {
36 .start
= OMAP24XX_CAMERA_BASE
,
37 .end
= OMAP24XX_CAMERA_BASE
+ 0xfff,
38 .flags
= IORESOURCE_MEM
,
41 .start
= INT_24XX_CAM_IRQ
,
42 .flags
= IORESOURCE_IRQ
,
46 static struct platform_device omap_cam_device
= {
47 .name
= "omap24xxcam",
49 .num_resources
= ARRAY_SIZE(cam_resources
),
50 .resource
= cam_resources
,
53 static inline void omap_init_camera(void)
55 platform_device_register(&omap_cam_device
);
58 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
60 static struct resource omap3isp_resources
[] = {
62 .start
= OMAP3430_ISP_BASE
,
63 .end
= OMAP3430_ISP_END
,
64 .flags
= IORESOURCE_MEM
,
67 .start
= OMAP3430_ISP_CBUFF_BASE
,
68 .end
= OMAP3430_ISP_CBUFF_END
,
69 .flags
= IORESOURCE_MEM
,
72 .start
= OMAP3430_ISP_CCP2_BASE
,
73 .end
= OMAP3430_ISP_CCP2_END
,
74 .flags
= IORESOURCE_MEM
,
77 .start
= OMAP3430_ISP_CCDC_BASE
,
78 .end
= OMAP3430_ISP_CCDC_END
,
79 .flags
= IORESOURCE_MEM
,
82 .start
= OMAP3430_ISP_HIST_BASE
,
83 .end
= OMAP3430_ISP_HIST_END
,
84 .flags
= IORESOURCE_MEM
,
87 .start
= OMAP3430_ISP_H3A_BASE
,
88 .end
= OMAP3430_ISP_H3A_END
,
89 .flags
= IORESOURCE_MEM
,
92 .start
= OMAP3430_ISP_PREV_BASE
,
93 .end
= OMAP3430_ISP_PREV_END
,
94 .flags
= IORESOURCE_MEM
,
97 .start
= OMAP3430_ISP_RESZ_BASE
,
98 .end
= OMAP3430_ISP_RESZ_END
,
99 .flags
= IORESOURCE_MEM
,
102 .start
= OMAP3430_ISP_SBL_BASE
,
103 .end
= OMAP3430_ISP_SBL_END
,
104 .flags
= IORESOURCE_MEM
,
107 .start
= OMAP3430_ISP_CSI2A_BASE
,
108 .end
= OMAP3430_ISP_CSI2A_END
,
109 .flags
= IORESOURCE_MEM
,
112 .start
= OMAP3430_ISP_CSI2PHY_BASE
,
113 .end
= OMAP3430_ISP_CSI2PHY_END
,
114 .flags
= IORESOURCE_MEM
,
117 .start
= INT_34XX_CAM_IRQ
,
118 .flags
= IORESOURCE_IRQ
,
122 static struct platform_device omap3isp_device
= {
125 .num_resources
= ARRAY_SIZE(omap3isp_resources
),
126 .resource
= omap3isp_resources
,
129 static inline void omap_init_camera(void)
131 platform_device_register(&omap3isp_device
);
134 static inline void omap_init_camera(void)
139 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
141 #define MBOX_REG_SIZE 0x120
143 #ifdef CONFIG_ARCH_OMAP2
144 static struct resource omap2_mbox_resources
[] = {
146 .start
= OMAP24XX_MAILBOX_BASE
,
147 .end
= OMAP24XX_MAILBOX_BASE
+ MBOX_REG_SIZE
- 1,
148 .flags
= IORESOURCE_MEM
,
151 .start
= INT_24XX_MAIL_U0_MPU
,
152 .flags
= IORESOURCE_IRQ
,
155 .start
= INT_24XX_MAIL_U3_MPU
,
156 .flags
= IORESOURCE_IRQ
,
159 static int omap2_mbox_resources_sz
= ARRAY_SIZE(omap2_mbox_resources
);
161 #define omap2_mbox_resources NULL
162 #define omap2_mbox_resources_sz 0
165 #ifdef CONFIG_ARCH_OMAP3
166 static struct resource omap3_mbox_resources
[] = {
168 .start
= OMAP34XX_MAILBOX_BASE
,
169 .end
= OMAP34XX_MAILBOX_BASE
+ MBOX_REG_SIZE
- 1,
170 .flags
= IORESOURCE_MEM
,
173 .start
= INT_24XX_MAIL_U0_MPU
,
174 .flags
= IORESOURCE_IRQ
,
177 static int omap3_mbox_resources_sz
= ARRAY_SIZE(omap3_mbox_resources
);
179 #define omap3_mbox_resources NULL
180 #define omap3_mbox_resources_sz 0
183 #ifdef CONFIG_ARCH_OMAP4
185 #define OMAP4_MBOX_REG_SIZE 0x130
186 static struct resource omap4_mbox_resources
[] = {
188 .start
= OMAP44XX_MAILBOX_BASE
,
189 .end
= OMAP44XX_MAILBOX_BASE
+
190 OMAP4_MBOX_REG_SIZE
- 1,
191 .flags
= IORESOURCE_MEM
,
194 .start
= OMAP44XX_IRQ_MAIL_U0
,
195 .flags
= IORESOURCE_IRQ
,
198 static int omap4_mbox_resources_sz
= ARRAY_SIZE(omap4_mbox_resources
);
200 #define omap4_mbox_resources NULL
201 #define omap4_mbox_resources_sz 0
204 static struct platform_device mbox_device
= {
205 .name
= "omap2-mailbox",
209 static inline void omap_init_mbox(void)
211 if (cpu_is_omap24xx()) {
212 mbox_device
.resource
= omap2_mbox_resources
;
213 mbox_device
.num_resources
= omap2_mbox_resources_sz
;
214 } else if (cpu_is_omap34xx()) {
215 mbox_device
.resource
= omap3_mbox_resources
;
216 mbox_device
.num_resources
= omap3_mbox_resources_sz
;
217 } else if (cpu_is_omap44xx()) {
218 mbox_device
.resource
= omap4_mbox_resources
;
219 mbox_device
.num_resources
= omap4_mbox_resources_sz
;
221 pr_err("%s: platform not supported\n", __func__
);
224 platform_device_register(&mbox_device
);
227 static inline void omap_init_mbox(void) { }
228 #endif /* CONFIG_OMAP_MBOX_FWK */
230 #if defined(CONFIG_OMAP_STI)
232 #if defined(CONFIG_ARCH_OMAP2)
234 #define OMAP2_STI_BASE 0x48068000
235 #define OMAP2_STI_CHANNEL_BASE 0x54000000
236 #define OMAP2_STI_IRQ 4
238 static struct resource sti_resources
[] = {
240 .start
= OMAP2_STI_BASE
,
241 .end
= OMAP2_STI_BASE
+ 0x7ff,
242 .flags
= IORESOURCE_MEM
,
245 .start
= OMAP2_STI_CHANNEL_BASE
,
246 .end
= OMAP2_STI_CHANNEL_BASE
+ SZ_64K
- 1,
247 .flags
= IORESOURCE_MEM
,
250 .start
= OMAP2_STI_IRQ
,
251 .flags
= IORESOURCE_IRQ
,
254 #elif defined(CONFIG_ARCH_OMAP3)
256 #define OMAP3_SDTI_BASE 0x54500000
257 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
259 static struct resource sti_resources
[] = {
261 .start
= OMAP3_SDTI_BASE
,
262 .end
= OMAP3_SDTI_BASE
+ 0xFFF,
263 .flags
= IORESOURCE_MEM
,
266 .start
= OMAP3_SDTI_CHANNEL_BASE
,
267 .end
= OMAP3_SDTI_CHANNEL_BASE
+ SZ_1M
- 1,
268 .flags
= IORESOURCE_MEM
,
274 static struct platform_device sti_device
= {
277 .num_resources
= ARRAY_SIZE(sti_resources
),
278 .resource
= sti_resources
,
281 static inline void omap_init_sti(void)
283 platform_device_register(&sti_device
);
286 static inline void omap_init_sti(void) {}
289 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
291 #include <plat/mcspi.h>
293 #define OMAP2_MCSPI1_BASE 0x48098000
294 #define OMAP2_MCSPI2_BASE 0x4809a000
295 #define OMAP2_MCSPI3_BASE 0x480b8000
296 #define OMAP2_MCSPI4_BASE 0x480ba000
298 #define OMAP4_MCSPI1_BASE 0x48098100
299 #define OMAP4_MCSPI2_BASE 0x4809a100
300 #define OMAP4_MCSPI3_BASE 0x480b8100
301 #define OMAP4_MCSPI4_BASE 0x480ba100
303 static struct omap2_mcspi_platform_config omap2_mcspi1_config
= {
307 static struct resource omap2_mcspi1_resources
[] = {
309 .start
= OMAP2_MCSPI1_BASE
,
310 .end
= OMAP2_MCSPI1_BASE
+ 0xff,
311 .flags
= IORESOURCE_MEM
,
315 static struct platform_device omap2_mcspi1
= {
316 .name
= "omap2_mcspi",
318 .num_resources
= ARRAY_SIZE(omap2_mcspi1_resources
),
319 .resource
= omap2_mcspi1_resources
,
321 .platform_data
= &omap2_mcspi1_config
,
325 static struct omap2_mcspi_platform_config omap2_mcspi2_config
= {
329 static struct resource omap2_mcspi2_resources
[] = {
331 .start
= OMAP2_MCSPI2_BASE
,
332 .end
= OMAP2_MCSPI2_BASE
+ 0xff,
333 .flags
= IORESOURCE_MEM
,
337 static struct platform_device omap2_mcspi2
= {
338 .name
= "omap2_mcspi",
340 .num_resources
= ARRAY_SIZE(omap2_mcspi2_resources
),
341 .resource
= omap2_mcspi2_resources
,
343 .platform_data
= &omap2_mcspi2_config
,
347 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
348 defined(CONFIG_ARCH_OMAP4)
349 static struct omap2_mcspi_platform_config omap2_mcspi3_config
= {
353 static struct resource omap2_mcspi3_resources
[] = {
355 .start
= OMAP2_MCSPI3_BASE
,
356 .end
= OMAP2_MCSPI3_BASE
+ 0xff,
357 .flags
= IORESOURCE_MEM
,
361 static struct platform_device omap2_mcspi3
= {
362 .name
= "omap2_mcspi",
364 .num_resources
= ARRAY_SIZE(omap2_mcspi3_resources
),
365 .resource
= omap2_mcspi3_resources
,
367 .platform_data
= &omap2_mcspi3_config
,
372 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
373 static struct omap2_mcspi_platform_config omap2_mcspi4_config
= {
377 static struct resource omap2_mcspi4_resources
[] = {
379 .start
= OMAP2_MCSPI4_BASE
,
380 .end
= OMAP2_MCSPI4_BASE
+ 0xff,
381 .flags
= IORESOURCE_MEM
,
385 static struct platform_device omap2_mcspi4
= {
386 .name
= "omap2_mcspi",
388 .num_resources
= ARRAY_SIZE(omap2_mcspi4_resources
),
389 .resource
= omap2_mcspi4_resources
,
391 .platform_data
= &omap2_mcspi4_config
,
396 #ifdef CONFIG_ARCH_OMAP4
397 static inline void omap4_mcspi_fixup(void)
399 omap2_mcspi1_resources
[0].start
= OMAP4_MCSPI1_BASE
;
400 omap2_mcspi1_resources
[0].end
= OMAP4_MCSPI1_BASE
+ 0xff;
401 omap2_mcspi2_resources
[0].start
= OMAP4_MCSPI2_BASE
;
402 omap2_mcspi2_resources
[0].end
= OMAP4_MCSPI2_BASE
+ 0xff;
403 omap2_mcspi3_resources
[0].start
= OMAP4_MCSPI3_BASE
;
404 omap2_mcspi3_resources
[0].end
= OMAP4_MCSPI3_BASE
+ 0xff;
405 omap2_mcspi4_resources
[0].start
= OMAP4_MCSPI4_BASE
;
406 omap2_mcspi4_resources
[0].end
= OMAP4_MCSPI4_BASE
+ 0xff;
409 static inline void omap4_mcspi_fixup(void)
414 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
415 defined(CONFIG_ARCH_OMAP4)
416 static inline void omap2_mcspi3_init(void)
418 platform_device_register(&omap2_mcspi3
);
421 static inline void omap2_mcspi3_init(void)
426 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
427 static inline void omap2_mcspi4_init(void)
429 platform_device_register(&omap2_mcspi4
);
432 static inline void omap2_mcspi4_init(void)
437 static void omap_init_mcspi(void)
439 if (cpu_is_omap44xx())
442 platform_device_register(&omap2_mcspi1
);
443 platform_device_register(&omap2_mcspi2
);
445 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
448 if (cpu_is_omap343x() || cpu_is_omap44xx())
453 static inline void omap_init_mcspi(void) {}
456 #ifdef CONFIG_OMAP_SHA1_MD5
457 static struct resource sha1_md5_resources
[] = {
459 .start
= OMAP24XX_SEC_SHA1MD5_BASE
,
460 .end
= OMAP24XX_SEC_SHA1MD5_BASE
+ 0x64,
461 .flags
= IORESOURCE_MEM
,
464 .start
= INT_24XX_SHA1MD5
,
465 .flags
= IORESOURCE_IRQ
,
469 static struct platform_device sha1_md5_device
= {
470 .name
= "OMAP SHA1/MD5",
472 .num_resources
= ARRAY_SIZE(sha1_md5_resources
),
473 .resource
= sha1_md5_resources
,
476 static void omap_init_sha1_md5(void)
478 platform_device_register(&sha1_md5_device
);
481 static inline void omap_init_sha1_md5(void) { }
484 /*-------------------------------------------------------------------------*/
486 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
488 #define MMCHS_SYSCONFIG 0x0010
489 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
490 #define MMCHS_SYSSTATUS 0x0014
491 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
493 static struct platform_device dummy_pdev
= {
495 .bus
= &platform_bus_type
,
500 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
502 * Ensure that each MMC controller is fully reset. Controllers
503 * left in an unknown state (by bootloader) may prevent retention
504 * or OFF-mode. This is especially important in cases where the
505 * MMC driver is not enabled, _or_ built as a module.
507 * In order for reset to work, interface, functional and debounce
508 * clocks must be enabled. The debounce clock comes from func_32k_clk
509 * and is not under SW control, so we only enable i- and f-clocks.
511 static void __init
omap_hsmmc_reset(void)
513 u32 i
, nr_controllers
;
515 if (cpu_is_omap242x())
518 nr_controllers
= cpu_is_omap44xx() ? OMAP44XX_NR_MMC
:
519 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC
: OMAP24XX_NR_MMC
);
521 for (i
= 0; i
< nr_controllers
; i
++) {
523 struct clk
*iclk
, *fclk
;
524 struct device
*dev
= &dummy_pdev
.dev
;
528 base
= OMAP2_MMC1_BASE
;
531 base
= OMAP2_MMC2_BASE
;
534 base
= OMAP3_MMC3_BASE
;
537 if (!cpu_is_omap44xx())
539 base
= OMAP4_MMC4_BASE
;
542 if (!cpu_is_omap44xx())
544 base
= OMAP4_MMC5_BASE
;
548 if (cpu_is_omap44xx())
549 base
+= OMAP4_MMC_REG_OFFSET
;
552 dev_set_name(&dummy_pdev
.dev
, "mmci-omap-hs.%d", i
);
553 iclk
= clk_get(dev
, "ick");
554 if (iclk
&& clk_enable(iclk
))
557 fclk
= clk_get(dev
, "fck");
558 if (fclk
&& clk_enable(fclk
))
561 if (!iclk
|| !fclk
) {
563 "%s: Unable to enable clocks for MMC%d, "
564 "cannot reset.\n", __func__
, i
);
568 omap_writel(MMCHS_SYSCONFIG_SWRESET
, base
+ MMCHS_SYSCONFIG
);
569 v
= omap_readl(base
+ MMCHS_SYSSTATUS
);
570 while (!(omap_readl(base
+ MMCHS_SYSSTATUS
) &
571 MMCHS_SYSSTATUS_RESETDONE
))
585 static inline void omap_hsmmc_reset(void) {}
588 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
589 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
591 static inline void omap2_mmc_mux(struct omap_mmc_platform_data
*mmc_controller
,
594 if (cpu_is_omap2420() && controller_nr
== 0) {
595 omap_cfg_reg(H18_24XX_MMC_CMD
);
596 omap_cfg_reg(H15_24XX_MMC_CLKI
);
597 omap_cfg_reg(G19_24XX_MMC_CLKO
);
598 omap_cfg_reg(F20_24XX_MMC_DAT0
);
599 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0
);
600 omap_cfg_reg(G18_24XX_MMC_CMD_DIR
);
601 if (mmc_controller
->slots
[0].wires
== 4) {
602 omap_cfg_reg(H14_24XX_MMC_DAT1
);
603 omap_cfg_reg(E19_24XX_MMC_DAT2
);
604 omap_cfg_reg(D19_24XX_MMC_DAT3
);
605 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1
);
606 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2
);
607 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3
);
611 * Use internal loop-back in MMC/SDIO Module Input Clock
614 if (mmc_controller
->slots
[0].internal_clock
) {
615 u32 v
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
);
617 omap_ctrl_writel(v
, OMAP2_CONTROL_DEVCONF0
);
621 if (cpu_is_omap34xx()) {
622 if (controller_nr
== 0) {
623 omap_mux_init_signal("sdmmc1_clk",
624 OMAP_PIN_INPUT_PULLUP
);
625 omap_mux_init_signal("sdmmc1_cmd",
626 OMAP_PIN_INPUT_PULLUP
);
627 omap_mux_init_signal("sdmmc1_dat0",
628 OMAP_PIN_INPUT_PULLUP
);
629 if (mmc_controller
->slots
[0].wires
== 4 ||
630 mmc_controller
->slots
[0].wires
== 8) {
631 omap_mux_init_signal("sdmmc1_dat1",
632 OMAP_PIN_INPUT_PULLUP
);
633 omap_mux_init_signal("sdmmc1_dat2",
634 OMAP_PIN_INPUT_PULLUP
);
635 omap_mux_init_signal("sdmmc1_dat3",
636 OMAP_PIN_INPUT_PULLUP
);
638 if (mmc_controller
->slots
[0].wires
== 8) {
639 omap_mux_init_signal("sdmmc1_dat4",
640 OMAP_PIN_INPUT_PULLUP
);
641 omap_mux_init_signal("sdmmc1_dat5",
642 OMAP_PIN_INPUT_PULLUP
);
643 omap_mux_init_signal("sdmmc1_dat6",
644 OMAP_PIN_INPUT_PULLUP
);
645 omap_mux_init_signal("sdmmc1_dat7",
646 OMAP_PIN_INPUT_PULLUP
);
649 if (controller_nr
== 1) {
651 omap_mux_init_signal("sdmmc2_clk",
652 OMAP_PIN_INPUT_PULLUP
);
653 omap_mux_init_signal("sdmmc2_cmd",
654 OMAP_PIN_INPUT_PULLUP
);
655 omap_mux_init_signal("sdmmc2_dat0",
656 OMAP_PIN_INPUT_PULLUP
);
659 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
660 * in the board-*.c files
662 if (mmc_controller
->slots
[0].wires
== 4 ||
663 mmc_controller
->slots
[0].wires
== 8) {
664 omap_mux_init_signal("sdmmc2_dat1",
665 OMAP_PIN_INPUT_PULLUP
);
666 omap_mux_init_signal("sdmmc2_dat2",
667 OMAP_PIN_INPUT_PULLUP
);
668 omap_mux_init_signal("sdmmc2_dat3",
669 OMAP_PIN_INPUT_PULLUP
);
671 if (mmc_controller
->slots
[0].wires
== 8) {
672 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
673 OMAP_PIN_INPUT_PULLUP
);
674 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
675 OMAP_PIN_INPUT_PULLUP
);
676 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
677 OMAP_PIN_INPUT_PULLUP
);
678 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
679 OMAP_PIN_INPUT_PULLUP
);
684 * For MMC3 the pins need to be muxed in the board-*.c files
689 void __init
omap2_init_mmc(struct omap_mmc_platform_data
**mmc_data
,
695 for (i
= 0; i
< nr_controllers
; i
++) {
696 unsigned long base
, size
;
697 unsigned int irq
= 0;
702 omap2_mmc_mux(mmc_data
[i
], i
);
706 base
= OMAP2_MMC1_BASE
;
707 irq
= INT_24XX_MMC_IRQ
;
710 base
= OMAP2_MMC2_BASE
;
711 irq
= INT_24XX_MMC2_IRQ
;
714 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
716 base
= OMAP3_MMC3_BASE
;
717 irq
= INT_34XX_MMC3_IRQ
;
720 if (!cpu_is_omap44xx())
722 base
= OMAP4_MMC4_BASE
+ OMAP4_MMC_REG_OFFSET
;
723 irq
= OMAP44XX_IRQ_MMC4
;
726 if (!cpu_is_omap44xx())
728 base
= OMAP4_MMC5_BASE
+ OMAP4_MMC_REG_OFFSET
;
729 irq
= OMAP44XX_IRQ_MMC4
;
735 if (cpu_is_omap2420()) {
736 size
= OMAP2420_MMC_SIZE
;
738 } else if (cpu_is_omap44xx()) {
740 base
+= OMAP4_MMC_REG_OFFSET
;
741 irq
+= OMAP44XX_IRQ_GIC_START
;
743 size
= OMAP4_HSMMC_SIZE
;
744 name
= "mmci-omap-hs";
746 size
= OMAP3_HSMMC_SIZE
;
747 name
= "mmci-omap-hs";
749 omap_mmc_add(name
, i
, base
, size
, irq
, mmc_data
[i
]);
755 /*-------------------------------------------------------------------------*/
757 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
758 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
759 #define OMAP_HDQ_BASE 0x480B2000
761 static struct resource omap_hdq_resources
[] = {
763 .start
= OMAP_HDQ_BASE
,
764 .end
= OMAP_HDQ_BASE
+ 0x1C,
765 .flags
= IORESOURCE_MEM
,
768 .start
= INT_24XX_HDQ_IRQ
,
769 .flags
= IORESOURCE_IRQ
,
772 static struct platform_device omap_hdq_dev
= {
776 .platform_data
= NULL
,
778 .num_resources
= ARRAY_SIZE(omap_hdq_resources
),
779 .resource
= omap_hdq_resources
,
781 static inline void omap_hdq_init(void)
783 (void) platform_device_register(&omap_hdq_dev
);
786 static inline void omap_hdq_init(void) {}
789 /*-------------------------------------------------------------------------*/
791 static int __init
omap2_init_devices(void)
793 /* please keep these calls, and their implementations above,
794 * in alphabetical order so they're easier to sort through.
802 omap_init_sha1_md5();
806 arch_initcall(omap2_init_devices
);