2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
28 #include <asm/mach-types.h>
29 #include <plat/gpmc.h>
32 #include <plat/sdrc.h>
34 #include <mach/hardware.h>
38 /* GPMC register offsets */
39 #define GPMC_REVISION 0x00
40 #define GPMC_SYSCONFIG 0x10
41 #define GPMC_SYSSTATUS 0x14
42 #define GPMC_IRQSTATUS 0x18
43 #define GPMC_IRQENABLE 0x1c
44 #define GPMC_TIMEOUT_CONTROL 0x40
45 #define GPMC_ERR_ADDRESS 0x44
46 #define GPMC_ERR_TYPE 0x48
47 #define GPMC_CONFIG 0x50
48 #define GPMC_STATUS 0x54
49 #define GPMC_PREFETCH_CONFIG1 0x1e0
50 #define GPMC_PREFETCH_CONFIG2 0x1e4
51 #define GPMC_PREFETCH_CONTROL 0x1ec
52 #define GPMC_PREFETCH_STATUS 0x1f0
53 #define GPMC_ECC_CONFIG 0x1f4
54 #define GPMC_ECC_CONTROL 0x1f8
55 #define GPMC_ECC_SIZE_CONFIG 0x1fc
56 #define GPMC_ECC1_RESULT 0x200
57 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
59 /* GPMC ECC control settings */
60 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
61 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
62 #define GPMC_ECC_CTRL_ECCREG1 0x001
63 #define GPMC_ECC_CTRL_ECCREG2 0x002
64 #define GPMC_ECC_CTRL_ECCREG3 0x003
65 #define GPMC_ECC_CTRL_ECCREG4 0x004
66 #define GPMC_ECC_CTRL_ECCREG5 0x005
67 #define GPMC_ECC_CTRL_ECCREG6 0x006
68 #define GPMC_ECC_CTRL_ECCREG7 0x007
69 #define GPMC_ECC_CTRL_ECCREG8 0x008
70 #define GPMC_ECC_CTRL_ECCREG9 0x009
72 #define GPMC_CS0_OFFSET 0x60
73 #define GPMC_CS_SIZE 0x30
75 #define GPMC_MEM_START 0x00000000
76 #define GPMC_MEM_END 0x3FFFFFFF
77 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
79 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
80 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
82 #define CS_NUM_SHIFT 24
83 #define ENABLE_PREFETCH (0x1 << 7)
84 #define DMA_MPU_MODE 2
86 /* XXX: Only NAND irq has been considered,currently these are the only ones used
90 struct gpmc_client_irq
{
95 /* Structure to save gpmc cs context */
96 struct gpmc_cs_config
{
108 * Structure to save/restore gpmc context
109 * to support core off on OMAP3
111 struct omap3_gpmc_regs
{
116 u32 prefetch_config1
;
117 u32 prefetch_config2
;
118 u32 prefetch_control
;
119 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
122 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
123 static struct irq_chip gpmc_irq_chip
;
124 static unsigned gpmc_irq_start
;
126 static struct resource gpmc_mem_root
;
127 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
128 static DEFINE_SPINLOCK(gpmc_mem_lock
);
129 static unsigned int gpmc_cs_map
; /* flag for cs which are initialized */
130 static int gpmc_ecc_used
= -EINVAL
; /* cs using ecc engine */
132 static void __iomem
*gpmc_base
;
134 static struct clk
*gpmc_l3_clk
;
136 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
138 static void gpmc_write_reg(int idx
, u32 val
)
140 __raw_writel(val
, gpmc_base
+ idx
);
143 static u32
gpmc_read_reg(int idx
)
145 return __raw_readl(gpmc_base
+ idx
);
148 static void gpmc_cs_write_byte(int cs
, int idx
, u8 val
)
150 void __iomem
*reg_addr
;
152 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
153 __raw_writeb(val
, reg_addr
);
156 static u8
gpmc_cs_read_byte(int cs
, int idx
)
158 void __iomem
*reg_addr
;
160 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
161 return __raw_readb(reg_addr
);
164 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
166 void __iomem
*reg_addr
;
168 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
169 __raw_writel(val
, reg_addr
);
172 u32
gpmc_cs_read_reg(int cs
, int idx
)
174 void __iomem
*reg_addr
;
176 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
177 return __raw_readl(reg_addr
);
180 /* TODO: Add support for gpmc_fck to clock framework and use it */
181 unsigned long gpmc_get_fclk_period(void)
183 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
186 printk(KERN_WARNING
"gpmc_l3_clk not enabled\n");
191 rate
= 1000000000 / rate
; /* In picoseconds */
196 unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
198 unsigned long tick_ps
;
200 /* Calculate in picosecs to yield more exact results */
201 tick_ps
= gpmc_get_fclk_period();
203 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
206 unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
208 unsigned long tick_ps
;
210 /* Calculate in picosecs to yield more exact results */
211 tick_ps
= gpmc_get_fclk_period();
213 return (time_ps
+ tick_ps
- 1) / tick_ps
;
216 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
218 return ticks
* gpmc_get_fclk_period() / 1000;
221 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns
)
223 unsigned long ticks
= gpmc_ns_to_ticks(time_ns
);
225 return ticks
* gpmc_get_fclk_period() / 1000;
229 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
230 int time
, const char *name
)
232 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
237 int ticks
, mask
, nr_bits
;
242 ticks
= gpmc_ns_to_ticks(time
);
243 nr_bits
= end_bit
- st_bit
+ 1;
244 if (ticks
>= 1 << nr_bits
) {
246 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
247 cs
, name
, time
, ticks
, 1 << nr_bits
);
252 mask
= (1 << nr_bits
) - 1;
253 l
= gpmc_cs_read_reg(cs
, reg
);
256 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
257 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
258 (l
>> st_bit
) & mask
, time
);
260 l
&= ~(mask
<< st_bit
);
261 l
|= ticks
<< st_bit
;
262 gpmc_cs_write_reg(cs
, reg
, l
);
268 #define GPMC_SET_ONE(reg, st, end, field) \
269 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
270 t->field, #field) < 0) \
273 #define GPMC_SET_ONE(reg, st, end, field) \
274 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
278 int gpmc_cs_calc_divider(int cs
, unsigned int sync_clk
)
283 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
284 div
= l
/ gpmc_get_fclk_period();
293 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
298 div
= gpmc_cs_calc_divider(cs
, t
->sync_clk
);
302 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
303 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
304 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
306 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
307 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
308 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
310 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
311 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
312 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
313 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
315 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
316 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
317 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
319 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
321 if (cpu_is_omap34xx()) {
322 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
323 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
326 /* caller is expected to have initialized CONFIG1 to cover
327 * at least sync vs async
329 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
330 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
332 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
333 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
337 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
343 static void gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
348 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
349 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
351 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
353 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
354 l
|= GPMC_CONFIG7_CSVALID
;
355 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
358 static void gpmc_cs_disable_mem(int cs
)
362 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
363 l
&= ~GPMC_CONFIG7_CSVALID
;
364 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
367 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
372 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
373 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
374 mask
= (l
>> 8) & 0x0f;
375 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
378 static int gpmc_cs_mem_enabled(int cs
)
382 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
383 return l
& GPMC_CONFIG7_CSVALID
;
386 int gpmc_cs_set_reserved(int cs
, int reserved
)
388 if (cs
> GPMC_CS_NUM
)
391 gpmc_cs_map
&= ~(1 << cs
);
392 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
397 int gpmc_cs_reserved(int cs
)
399 if (cs
> GPMC_CS_NUM
)
402 return gpmc_cs_map
& (1 << cs
);
405 static unsigned long gpmc_mem_align(unsigned long size
)
409 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
410 order
= GPMC_CHUNK_SHIFT
- 1;
419 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
421 struct resource
*res
= &gpmc_cs_mem
[cs
];
424 size
= gpmc_mem_align(size
);
425 spin_lock(&gpmc_mem_lock
);
427 res
->end
= base
+ size
- 1;
428 r
= request_resource(&gpmc_mem_root
, res
);
429 spin_unlock(&gpmc_mem_lock
);
434 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
436 struct resource
*res
= &gpmc_cs_mem
[cs
];
439 if (cs
> GPMC_CS_NUM
)
442 size
= gpmc_mem_align(size
);
443 if (size
> (1 << GPMC_SECTION_SHIFT
))
446 spin_lock(&gpmc_mem_lock
);
447 if (gpmc_cs_reserved(cs
)) {
451 if (gpmc_cs_mem_enabled(cs
))
452 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
454 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
459 gpmc_cs_enable_mem(cs
, res
->start
, resource_size(res
));
461 gpmc_cs_set_reserved(cs
, 1);
463 spin_unlock(&gpmc_mem_lock
);
466 EXPORT_SYMBOL(gpmc_cs_request
);
468 void gpmc_cs_free(int cs
)
470 spin_lock(&gpmc_mem_lock
);
471 if (cs
>= GPMC_CS_NUM
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
472 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
474 spin_unlock(&gpmc_mem_lock
);
477 gpmc_cs_disable_mem(cs
);
478 release_resource(&gpmc_cs_mem
[cs
]);
479 gpmc_cs_set_reserved(cs
, 0);
480 spin_unlock(&gpmc_mem_lock
);
482 EXPORT_SYMBOL(gpmc_cs_free
);
485 * gpmc_read_status - read access request to get the different gpmc status
489 int gpmc_read_status(int cmd
)
491 int status
= -EINVAL
;
495 case GPMC_GET_IRQ_STATUS
:
496 status
= gpmc_read_reg(GPMC_IRQSTATUS
);
499 case GPMC_PREFETCH_FIFO_CNT
:
500 regval
= gpmc_read_reg(GPMC_PREFETCH_STATUS
);
501 status
= GPMC_PREFETCH_STATUS_FIFO_CNT(regval
);
504 case GPMC_PREFETCH_COUNT
:
505 regval
= gpmc_read_reg(GPMC_PREFETCH_STATUS
);
506 status
= GPMC_PREFETCH_STATUS_COUNT(regval
);
509 case GPMC_STATUS_BUFFER
:
510 regval
= gpmc_read_reg(GPMC_STATUS
);
511 /* 1 : buffer is available to write */
512 status
= regval
& GPMC_STATUS_BUFF_EMPTY
;
516 printk(KERN_ERR
"gpmc_read_status: Not supported\n");
520 EXPORT_SYMBOL(gpmc_read_status
);
523 * gpmc_cs_configure - write request to configure gpmc
524 * @cs: chip select number
526 * @wval: value to write
527 * @return status of the operation
529 int gpmc_cs_configure(int cs
, int cmd
, int wval
)
535 case GPMC_ENABLE_IRQ
:
536 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
539 case GPMC_SET_IRQ_STATUS
:
540 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
544 regval
= gpmc_read_reg(GPMC_CONFIG
);
546 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
548 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
549 gpmc_write_reg(GPMC_CONFIG
, regval
);
552 case GPMC_CONFIG_RDY_BSY
:
553 regval
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
555 regval
|= WR_RD_PIN_MONITORING
;
557 regval
&= ~WR_RD_PIN_MONITORING
;
558 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, regval
);
561 case GPMC_CONFIG_DEV_SIZE
:
562 regval
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
564 /* clear 2 target bits */
565 regval
&= ~GPMC_CONFIG1_DEVICESIZE(3);
567 /* set the proper value */
568 regval
|= GPMC_CONFIG1_DEVICESIZE(wval
);
570 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, regval
);
573 case GPMC_CONFIG_DEV_TYPE
:
574 regval
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
575 regval
|= GPMC_CONFIG1_DEVICETYPE(wval
);
576 if (wval
== GPMC_DEVICETYPE_NOR
)
577 regval
|= GPMC_CONFIG1_MUXADDDATA
;
578 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, regval
);
582 printk(KERN_ERR
"gpmc_configure_cs: Not supported\n");
588 EXPORT_SYMBOL(gpmc_cs_configure
);
591 * gpmc_nand_read - nand specific read access request
592 * @cs: chip select number
595 int gpmc_nand_read(int cs
, int cmd
)
601 rval
= gpmc_cs_read_byte(cs
, GPMC_CS_NAND_DATA
);
605 printk(KERN_ERR
"gpmc_read_nand_ctrl: Not supported\n");
609 EXPORT_SYMBOL(gpmc_nand_read
);
612 * gpmc_nand_write - nand specific write request
613 * @cs: chip select number
615 * @wval: value to write
617 int gpmc_nand_write(int cs
, int cmd
, int wval
)
622 case GPMC_NAND_COMMAND
:
623 gpmc_cs_write_byte(cs
, GPMC_CS_NAND_COMMAND
, wval
);
626 case GPMC_NAND_ADDRESS
:
627 gpmc_cs_write_byte(cs
, GPMC_CS_NAND_ADDRESS
, wval
);
631 gpmc_cs_write_byte(cs
, GPMC_CS_NAND_DATA
, wval
);
634 printk(KERN_ERR
"gpmc_write_nand_ctrl: Not supported\n");
639 EXPORT_SYMBOL(gpmc_nand_write
);
644 * gpmc_prefetch_enable - configures and starts prefetch transfer
645 * @cs: cs (chip select) number
646 * @fifo_th: fifo threshold to be used for read/ write
647 * @dma_mode: dma mode enable (1) or disable (0)
648 * @u32_count: number of bytes to be transferred
649 * @is_write: prefetch read(0) or write post(1) mode
651 int gpmc_prefetch_enable(int cs
, int fifo_th
, int dma_mode
,
652 unsigned int u32_count
, int is_write
)
655 if (fifo_th
> PREFETCH_FIFOTHRESHOLD_MAX
) {
656 pr_err("gpmc: fifo threshold is not supported\n");
658 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL
))) {
659 /* Set the amount of bytes to be prefetched */
660 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, u32_count
);
662 /* Set dma/mpu mode, the prefetch read / post write and
663 * enable the engine. Set which cs is has requested for.
665 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, ((cs
<< CS_NUM_SHIFT
) |
666 PREFETCH_FIFOTHRESHOLD(fifo_th
) |
668 (dma_mode
<< DMA_MPU_MODE
) |
671 /* Start the prefetch engine */
672 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, 0x1);
679 EXPORT_SYMBOL(gpmc_prefetch_enable
);
682 * gpmc_prefetch_reset - disables and stops the prefetch engine
684 int gpmc_prefetch_reset(int cs
)
688 /* check if the same module/cs is trying to reset */
689 config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
690 if (((config1
>> CS_NUM_SHIFT
) & 0x7) != cs
)
693 /* Stop the PFPW engine */
694 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, 0x0);
696 /* Reset/disable the PFPW engine */
697 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, 0x0);
701 EXPORT_SYMBOL(gpmc_prefetch_reset
);
703 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
705 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
706 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
707 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
708 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
709 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
710 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
711 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
712 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
713 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
714 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
715 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
716 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
717 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
718 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
719 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
720 reg
->gpmc_bch_result0
= gpmc_base
+ GPMC_ECC_BCH_RESULT_0
;
723 int gpmc_get_client_irq(unsigned irq_config
)
727 if (hweight32(irq_config
) > 1)
730 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
731 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
732 return gpmc_client_irq
[i
].irq
;
737 static int gpmc_irq_endis(unsigned irq
, bool endis
)
742 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
743 if (irq
== gpmc_client_irq
[i
].irq
) {
744 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
746 regval
|= gpmc_client_irq
[i
].bitmask
;
748 regval
&= ~gpmc_client_irq
[i
].bitmask
;
749 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
756 static void gpmc_irq_disable(struct irq_data
*p
)
758 gpmc_irq_endis(p
->irq
, false);
761 static void gpmc_irq_enable(struct irq_data
*p
)
763 gpmc_irq_endis(p
->irq
, true);
766 static void gpmc_irq_noop(struct irq_data
*data
) { }
768 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
770 static int gpmc_setup_irq(int gpmc_irq
)
778 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
779 if (IS_ERR_VALUE(gpmc_irq_start
)) {
780 pr_err("irq_alloc_descs failed\n");
781 return gpmc_irq_start
;
784 gpmc_irq_chip
.name
= "gpmc";
785 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
786 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
787 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
788 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
789 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
790 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
791 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
793 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
794 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
796 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
797 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
798 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
799 &gpmc_irq_chip
, handle_simple_irq
);
800 set_irq_flags(gpmc_client_irq
[i
].irq
,
801 IRQF_VALID
| IRQF_NOAUTOEN
);
804 /* Disable interrupts */
805 gpmc_write_reg(GPMC_IRQENABLE
, 0);
807 /* clear interrupts */
808 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
809 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
811 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
814 static void __init
gpmc_mem_init(void)
817 unsigned long boot_rom_space
= 0;
819 /* never allocate the first page, to facilitate bug detection;
820 * even if we didn't boot from ROM.
822 boot_rom_space
= BOOT_ROM_SPACE
;
823 /* In apollon the CS0 is mapped as 0x0000 0000 */
824 if (machine_is_omap_apollon())
826 gpmc_mem_root
.start
= GPMC_MEM_START
+ boot_rom_space
;
827 gpmc_mem_root
.end
= GPMC_MEM_END
;
829 /* Reserve all regions that has been set up by bootloader */
830 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
833 if (!gpmc_cs_mem_enabled(cs
))
835 gpmc_cs_get_memconf(cs
, &base
, &size
);
836 if (gpmc_cs_insert_mem(cs
, base
, size
) < 0)
841 static int __init
gpmc_init(void)
848 if (cpu_is_omap24xx()) {
850 if (cpu_is_omap2420())
851 l
= OMAP2420_GPMC_BASE
;
853 l
= OMAP34XX_GPMC_BASE
;
854 gpmc_irq
= 20 + OMAP_INTC_START
;
855 } else if (cpu_is_omap34xx()) {
857 l
= OMAP34XX_GPMC_BASE
;
858 gpmc_irq
= 20 + OMAP_INTC_START
;
859 } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
860 /* Base address and irq number are same for OMAP4/5 */
862 l
= OMAP44XX_GPMC_BASE
;
863 gpmc_irq
= 20 + OMAP44XX_IRQ_GIC_START
;
869 gpmc_l3_clk
= clk_get(NULL
, ck
);
870 if (IS_ERR(gpmc_l3_clk
)) {
871 printk(KERN_ERR
"Could not get GPMC clock %s\n", ck
);
875 gpmc_base
= ioremap(l
, SZ_4K
);
877 clk_put(gpmc_l3_clk
);
878 printk(KERN_ERR
"Could not get GPMC register memory\n");
882 clk_enable(gpmc_l3_clk
);
884 l
= gpmc_read_reg(GPMC_REVISION
);
885 printk(KERN_INFO
"GPMC revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
886 /* Set smart idle mode and automatic L3 clock gating */
887 l
= gpmc_read_reg(GPMC_SYSCONFIG
);
889 l
|= (0x02 << 3) | (1 << 0);
890 gpmc_write_reg(GPMC_SYSCONFIG
, l
);
893 ret
= gpmc_setup_irq(gpmc_irq
);
895 pr_err("gpmc: irq-%d could not claim: err %d\n",
899 postcore_initcall(gpmc_init
);
901 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
906 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
911 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
912 if (regval
& gpmc_client_irq
[i
].bitmask
)
913 generic_handle_irq(gpmc_client_irq
[i
].irq
);
915 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
920 #ifdef CONFIG_ARCH_OMAP3
921 static struct omap3_gpmc_regs gpmc_context
;
923 void omap3_gpmc_save_context(void)
927 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
928 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
929 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
930 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
931 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
932 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
933 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
934 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
935 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
936 if (gpmc_context
.cs_context
[i
].is_valid
) {
937 gpmc_context
.cs_context
[i
].config1
=
938 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
939 gpmc_context
.cs_context
[i
].config2
=
940 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
941 gpmc_context
.cs_context
[i
].config3
=
942 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
943 gpmc_context
.cs_context
[i
].config4
=
944 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
945 gpmc_context
.cs_context
[i
].config5
=
946 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
947 gpmc_context
.cs_context
[i
].config6
=
948 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
949 gpmc_context
.cs_context
[i
].config7
=
950 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
955 void omap3_gpmc_restore_context(void)
959 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
960 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
961 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
962 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
963 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
964 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
965 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
966 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
967 if (gpmc_context
.cs_context
[i
].is_valid
) {
968 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
969 gpmc_context
.cs_context
[i
].config1
);
970 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
971 gpmc_context
.cs_context
[i
].config2
);
972 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
973 gpmc_context
.cs_context
[i
].config3
);
974 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
975 gpmc_context
.cs_context
[i
].config4
);
976 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
977 gpmc_context
.cs_context
[i
].config5
);
978 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
979 gpmc_context
.cs_context
[i
].config6
);
980 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
981 gpmc_context
.cs_context
[i
].config7
);
985 #endif /* CONFIG_ARCH_OMAP3 */
988 * gpmc_enable_hwecc - enable hardware ecc functionality
989 * @cs: chip select number
990 * @mode: read/write mode
991 * @dev_width: device bus width(1 for x16, 0 for x8)
992 * @ecc_size: bytes for which ECC will be generated
994 int gpmc_enable_hwecc(int cs
, int mode
, int dev_width
, int ecc_size
)
998 /* check if ecc module is in used */
999 if (gpmc_ecc_used
!= -EINVAL
)
1004 /* clear ecc and enable bits */
1005 gpmc_write_reg(GPMC_ECC_CONTROL
,
1006 GPMC_ECC_CTRL_ECCCLEAR
|
1007 GPMC_ECC_CTRL_ECCREG1
);
1009 /* program ecc and result sizes */
1010 val
= ((((ecc_size
>> 1) - 1) << 22) | (0x0000000F));
1011 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG
, val
);
1015 case GPMC_ECC_WRITE
:
1016 gpmc_write_reg(GPMC_ECC_CONTROL
,
1017 GPMC_ECC_CTRL_ECCCLEAR
|
1018 GPMC_ECC_CTRL_ECCREG1
);
1020 case GPMC_ECC_READSYN
:
1021 gpmc_write_reg(GPMC_ECC_CONTROL
,
1022 GPMC_ECC_CTRL_ECCCLEAR
|
1023 GPMC_ECC_CTRL_ECCDISABLE
);
1026 printk(KERN_INFO
"Error: Unrecognized Mode[%d]!\n", mode
);
1030 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
1031 val
= (dev_width
<< 7) | (cs
<< 1) | (0x1);
1032 gpmc_write_reg(GPMC_ECC_CONFIG
, val
);
1035 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc
);
1038 * gpmc_calculate_ecc - generate non-inverted ecc bytes
1039 * @cs: chip select number
1040 * @dat: data pointer over which ecc is computed
1041 * @ecc_code: ecc code buffer
1043 * Using non-inverted ECC is considered ugly since writing a blank
1044 * page (padding) will clear the ECC bytes. This is not a problem as long
1045 * no one is trying to write data on the seemingly unused page. Reading
1046 * an erased page will produce an ECC mismatch between generated and read
1047 * ECC bytes that has to be dealt with separately.
1049 int gpmc_calculate_ecc(int cs
, const u_char
*dat
, u_char
*ecc_code
)
1051 unsigned int val
= 0x0;
1053 if (gpmc_ecc_used
!= cs
)
1056 /* read ecc result */
1057 val
= gpmc_read_reg(GPMC_ECC1_RESULT
);
1058 *ecc_code
++ = val
; /* P128e, ..., P1e */
1059 *ecc_code
++ = val
>> 16; /* P128o, ..., P1o */
1060 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
1061 *ecc_code
++ = ((val
>> 8) & 0x0f) | ((val
>> 20) & 0xf0);
1063 gpmc_ecc_used
= -EINVAL
;
1066 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc
);
1068 #ifdef CONFIG_ARCH_OMAP3
1071 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
1072 * @cs: chip select number
1073 * @nsectors: how many 512-byte sectors to process
1074 * @nerrors: how many errors to correct per sector (4 or 8)
1076 * This function must be executed before any call to gpmc_enable_hwecc_bch.
1078 int gpmc_init_hwecc_bch(int cs
, int nsectors
, int nerrors
)
1080 /* check if ecc module is in use */
1081 if (gpmc_ecc_used
!= -EINVAL
)
1084 /* support only OMAP3 class */
1085 if (!cpu_is_omap34xx()) {
1086 printk(KERN_ERR
"BCH ecc is not supported on this CPU\n");
1091 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
1092 * Other chips may be added if confirmed to work.
1094 if ((nerrors
== 4) &&
1095 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
1096 printk(KERN_ERR
"BCH 4-bit mode is not supported on this CPU\n");
1102 printk(KERN_ERR
"BCH cannot process %d sectors (max is 8)\n",
1109 EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch
);
1112 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
1113 * @cs: chip select number
1114 * @mode: read/write mode
1115 * @dev_width: device bus width(1 for x16, 0 for x8)
1116 * @nsectors: how many 512-byte sectors to process
1117 * @nerrors: how many errors to correct per sector (4 or 8)
1119 int gpmc_enable_hwecc_bch(int cs
, int mode
, int dev_width
, int nsectors
,
1124 /* check if ecc module is in use */
1125 if (gpmc_ecc_used
!= -EINVAL
)
1130 /* clear ecc and enable bits */
1131 gpmc_write_reg(GPMC_ECC_CONTROL
, 0x1);
1134 * When using BCH, sector size is hardcoded to 512 bytes.
1135 * Here we are using wrapping mode 6 both for reading and writing, with:
1136 * size0 = 0 (no additional protected byte in spare area)
1137 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1139 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG
, (32 << 22) | (0 << 12));
1141 /* BCH configuration */
1142 val
= ((1 << 16) | /* enable BCH */
1143 (((nerrors
== 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1144 (0x06 << 8) | /* wrap mode = 6 */
1145 (dev_width
<< 7) | /* bus width */
1146 (((nsectors
-1) & 0x7) << 4) | /* number of sectors */
1147 (cs
<< 1) | /* ECC CS */
1148 (0x1)); /* enable ECC */
1150 gpmc_write_reg(GPMC_ECC_CONFIG
, val
);
1151 gpmc_write_reg(GPMC_ECC_CONTROL
, 0x101);
1154 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch
);
1157 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1158 * @cs: chip select number
1159 * @dat: The pointer to data on which ecc is computed
1160 * @ecc: The ecc output buffer
1162 int gpmc_calculate_ecc_bch4(int cs
, const u_char
*dat
, u_char
*ecc
)
1165 unsigned long nsectors
, reg
, val1
, val2
;
1167 if (gpmc_ecc_used
!= cs
)
1170 nsectors
= ((gpmc_read_reg(GPMC_ECC_CONFIG
) >> 4) & 0x7) + 1;
1172 for (i
= 0; i
< nsectors
; i
++) {
1174 reg
= GPMC_ECC_BCH_RESULT_0
+ 16*i
;
1176 /* Read hw-computed remainder */
1177 val1
= gpmc_read_reg(reg
+ 0);
1178 val2
= gpmc_read_reg(reg
+ 4);
1181 * Add constant polynomial to remainder, in order to get an ecc
1182 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1183 * left-justify the resulting polynomial.
1185 *ecc
++ = 0x28 ^ ((val2
>> 12) & 0xFF);
1186 *ecc
++ = 0x13 ^ ((val2
>> 4) & 0xFF);
1187 *ecc
++ = 0xcc ^ (((val2
& 0xF) << 4)|((val1
>> 28) & 0xF));
1188 *ecc
++ = 0x39 ^ ((val1
>> 20) & 0xFF);
1189 *ecc
++ = 0x96 ^ ((val1
>> 12) & 0xFF);
1190 *ecc
++ = 0xac ^ ((val1
>> 4) & 0xFF);
1191 *ecc
++ = 0x7f ^ ((val1
& 0xF) << 4);
1194 gpmc_ecc_used
= -EINVAL
;
1197 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4
);
1200 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1201 * @cs: chip select number
1202 * @dat: The pointer to data on which ecc is computed
1203 * @ecc: The ecc output buffer
1205 int gpmc_calculate_ecc_bch8(int cs
, const u_char
*dat
, u_char
*ecc
)
1208 unsigned long nsectors
, reg
, val1
, val2
, val3
, val4
;
1210 if (gpmc_ecc_used
!= cs
)
1213 nsectors
= ((gpmc_read_reg(GPMC_ECC_CONFIG
) >> 4) & 0x7) + 1;
1215 for (i
= 0; i
< nsectors
; i
++) {
1217 reg
= GPMC_ECC_BCH_RESULT_0
+ 16*i
;
1219 /* Read hw-computed remainder */
1220 val1
= gpmc_read_reg(reg
+ 0);
1221 val2
= gpmc_read_reg(reg
+ 4);
1222 val3
= gpmc_read_reg(reg
+ 8);
1223 val4
= gpmc_read_reg(reg
+ 12);
1226 * Add constant polynomial to remainder, in order to get an ecc
1227 * sequence of 0xFFs for a buffer filled with 0xFFs.
1229 *ecc
++ = 0xef ^ (val4
& 0xFF);
1230 *ecc
++ = 0x51 ^ ((val3
>> 24) & 0xFF);
1231 *ecc
++ = 0x2e ^ ((val3
>> 16) & 0xFF);
1232 *ecc
++ = 0x09 ^ ((val3
>> 8) & 0xFF);
1233 *ecc
++ = 0xed ^ (val3
& 0xFF);
1234 *ecc
++ = 0x93 ^ ((val2
>> 24) & 0xFF);
1235 *ecc
++ = 0x9a ^ ((val2
>> 16) & 0xFF);
1236 *ecc
++ = 0xc2 ^ ((val2
>> 8) & 0xFF);
1237 *ecc
++ = 0x97 ^ (val2
& 0xFF);
1238 *ecc
++ = 0x79 ^ ((val1
>> 24) & 0xFF);
1239 *ecc
++ = 0xe5 ^ ((val1
>> 16) & 0xFF);
1240 *ecc
++ = 0x24 ^ ((val1
>> 8) & 0xFF);
1241 *ecc
++ = 0xb5 ^ (val1
& 0xFF);
1244 gpmc_ecc_used
= -EINVAL
;
1247 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8
);
1249 #endif /* CONFIG_ARCH_OMAP3 */