2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_address.h>
30 #include <linux/of_mtd.h>
31 #include <linux/of_device.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
37 #include <asm/mach-types.h>
41 #include "omap_device.h"
43 #include "gpmc-nand.h"
44 #include "gpmc-onenand.h"
46 #define DEVICE_NAME "omap-gpmc"
48 /* GPMC register offsets */
49 #define GPMC_REVISION 0x00
50 #define GPMC_SYSCONFIG 0x10
51 #define GPMC_SYSSTATUS 0x14
52 #define GPMC_IRQSTATUS 0x18
53 #define GPMC_IRQENABLE 0x1c
54 #define GPMC_TIMEOUT_CONTROL 0x40
55 #define GPMC_ERR_ADDRESS 0x44
56 #define GPMC_ERR_TYPE 0x48
57 #define GPMC_CONFIG 0x50
58 #define GPMC_STATUS 0x54
59 #define GPMC_PREFETCH_CONFIG1 0x1e0
60 #define GPMC_PREFETCH_CONFIG2 0x1e4
61 #define GPMC_PREFETCH_CONTROL 0x1ec
62 #define GPMC_PREFETCH_STATUS 0x1f0
63 #define GPMC_ECC_CONFIG 0x1f4
64 #define GPMC_ECC_CONTROL 0x1f8
65 #define GPMC_ECC_SIZE_CONFIG 0x1fc
66 #define GPMC_ECC1_RESULT 0x200
67 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
69 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
70 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
72 /* GPMC ECC control settings */
73 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
74 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
75 #define GPMC_ECC_CTRL_ECCREG1 0x001
76 #define GPMC_ECC_CTRL_ECCREG2 0x002
77 #define GPMC_ECC_CTRL_ECCREG3 0x003
78 #define GPMC_ECC_CTRL_ECCREG4 0x004
79 #define GPMC_ECC_CTRL_ECCREG5 0x005
80 #define GPMC_ECC_CTRL_ECCREG6 0x006
81 #define GPMC_ECC_CTRL_ECCREG7 0x007
82 #define GPMC_ECC_CTRL_ECCREG8 0x008
83 #define GPMC_ECC_CTRL_ECCREG9 0x009
85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
88 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
92 #define GPMC_CS0_OFFSET 0x60
93 #define GPMC_CS_SIZE 0x30
94 #define GPMC_BCH_SIZE 0x10
96 #define GPMC_MEM_END 0x3FFFFFFF
98 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
101 #define CS_NUM_SHIFT 24
102 #define ENABLE_PREFETCH (0x1 << 7)
103 #define DMA_MPU_MODE 2
105 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
106 #define GPMC_REVISION_MINOR(l) (l & 0xf)
108 #define GPMC_HAS_WR_ACCESS 0x1
109 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
110 #define GPMC_HAS_MUX_AAD 0x4
112 #define GPMC_NR_WAITPINS 4
114 /* XXX: Only NAND irq has been considered,currently these are the only ones used
116 #define GPMC_NR_IRQ 2
118 struct gpmc_client_irq
{
123 /* Structure to save gpmc cs context */
124 struct gpmc_cs_config
{
136 * Structure to save/restore gpmc context
137 * to support core off on OMAP3
139 struct omap3_gpmc_regs
{
144 u32 prefetch_config1
;
145 u32 prefetch_config2
;
146 u32 prefetch_control
;
147 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
150 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
151 static struct irq_chip gpmc_irq_chip
;
152 static int gpmc_irq_start
;
154 static struct resource gpmc_mem_root
;
155 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
156 static DEFINE_SPINLOCK(gpmc_mem_lock
);
157 /* Define chip-selects as reserved by default until probe completes */
158 static unsigned int gpmc_cs_map
= ((1 << GPMC_CS_NUM
) - 1);
159 static unsigned int gpmc_cs_num
= GPMC_CS_NUM
;
160 static unsigned int gpmc_nr_waitpins
;
161 static struct device
*gpmc_dev
;
163 static resource_size_t phys_base
, mem_size
;
164 static unsigned gpmc_capability
;
165 static void __iomem
*gpmc_base
;
167 static struct clk
*gpmc_l3_clk
;
169 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
171 static void gpmc_write_reg(int idx
, u32 val
)
173 __raw_writel(val
, gpmc_base
+ idx
);
176 static u32
gpmc_read_reg(int idx
)
178 return __raw_readl(gpmc_base
+ idx
);
181 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
183 void __iomem
*reg_addr
;
185 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
186 __raw_writel(val
, reg_addr
);
189 static u32
gpmc_cs_read_reg(int cs
, int idx
)
191 void __iomem
*reg_addr
;
193 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
194 return __raw_readl(reg_addr
);
197 /* TODO: Add support for gpmc_fck to clock framework and use it */
198 static unsigned long gpmc_get_fclk_period(void)
200 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
203 printk(KERN_WARNING
"gpmc_l3_clk not enabled\n");
208 rate
= 1000000000 / rate
; /* In picoseconds */
213 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
215 unsigned long tick_ps
;
217 /* Calculate in picosecs to yield more exact results */
218 tick_ps
= gpmc_get_fclk_period();
220 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
223 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
225 unsigned long tick_ps
;
227 /* Calculate in picosecs to yield more exact results */
228 tick_ps
= gpmc_get_fclk_period();
230 return (time_ps
+ tick_ps
- 1) / tick_ps
;
233 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
235 return ticks
* gpmc_get_fclk_period() / 1000;
238 static unsigned int gpmc_ticks_to_ps(unsigned int ticks
)
240 return ticks
* gpmc_get_fclk_period();
243 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps
)
245 unsigned long ticks
= gpmc_ps_to_ticks(time_ps
);
247 return ticks
* gpmc_get_fclk_period();
250 static inline void gpmc_cs_modify_reg(int cs
, int reg
, u32 mask
, bool value
)
254 l
= gpmc_cs_read_reg(cs
, reg
);
259 gpmc_cs_write_reg(cs
, reg
, l
);
262 static void gpmc_cs_bool_timings(int cs
, const struct gpmc_bool_timings
*p
)
264 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG1
,
265 GPMC_CONFIG1_TIME_PARA_GRAN
,
266 p
->time_para_granularity
);
267 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG2
,
268 GPMC_CONFIG2_CSEXTRADELAY
, p
->cs_extra_delay
);
269 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG3
,
270 GPMC_CONFIG3_ADVEXTRADELAY
, p
->adv_extra_delay
);
271 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
272 GPMC_CONFIG4_OEEXTRADELAY
, p
->oe_extra_delay
);
273 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
274 GPMC_CONFIG4_OEEXTRADELAY
, p
->we_extra_delay
);
275 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
276 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
,
277 p
->cycle2cyclesamecsen
);
278 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
279 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
,
280 p
->cycle2cyclediffcsen
);
284 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
285 int time
, const char *name
)
287 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
292 int ticks
, mask
, nr_bits
;
297 ticks
= gpmc_ns_to_ticks(time
);
298 nr_bits
= end_bit
- st_bit
+ 1;
299 if (ticks
>= 1 << nr_bits
) {
301 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
302 cs
, name
, time
, ticks
, 1 << nr_bits
);
307 mask
= (1 << nr_bits
) - 1;
308 l
= gpmc_cs_read_reg(cs
, reg
);
311 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
312 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
313 (l
>> st_bit
) & mask
, time
);
315 l
&= ~(mask
<< st_bit
);
316 l
|= ticks
<< st_bit
;
317 gpmc_cs_write_reg(cs
, reg
, l
);
323 #define GPMC_SET_ONE(reg, st, end, field) \
324 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
325 t->field, #field) < 0) \
328 #define GPMC_SET_ONE(reg, st, end, field) \
329 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
333 int gpmc_calc_divider(unsigned int sync_clk
)
338 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
339 div
= l
/ gpmc_get_fclk_period();
348 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
353 div
= gpmc_calc_divider(t
->sync_clk
);
357 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
358 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
359 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
361 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
362 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
363 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
365 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
370 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
371 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
374 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
376 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 0, 3, bus_turnaround
);
377 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 8, 11, cycle2cycle_delay
);
379 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 18, 19, wait_monitoring
);
380 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 25, 26, clk_activation
);
382 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
384 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
387 /* caller is expected to have initialized CONFIG1 to cover
388 * at least sync vs async
390 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
391 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
393 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
394 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
398 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
401 gpmc_cs_bool_timings(cs
, &t
->bool_timings
);
406 static int gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
412 * Ensure that base address is aligned on a
413 * boundary equal to or greater than size.
415 if (base
& (size
- 1))
418 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
419 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
421 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
423 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
424 l
|= GPMC_CONFIG7_CSVALID
;
425 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
430 static void gpmc_cs_disable_mem(int cs
)
434 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
435 l
&= ~GPMC_CONFIG7_CSVALID
;
436 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
439 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
444 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
445 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
446 mask
= (l
>> 8) & 0x0f;
447 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
450 static int gpmc_cs_mem_enabled(int cs
)
454 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
455 return l
& GPMC_CONFIG7_CSVALID
;
458 static void gpmc_cs_set_reserved(int cs
, int reserved
)
460 gpmc_cs_map
&= ~(1 << cs
);
461 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
464 static bool gpmc_cs_reserved(int cs
)
466 return gpmc_cs_map
& (1 << cs
);
469 static unsigned long gpmc_mem_align(unsigned long size
)
473 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
474 order
= GPMC_CHUNK_SHIFT
- 1;
483 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
485 struct resource
*res
= &gpmc_cs_mem
[cs
];
488 size
= gpmc_mem_align(size
);
489 spin_lock(&gpmc_mem_lock
);
491 res
->end
= base
+ size
- 1;
492 r
= request_resource(&gpmc_mem_root
, res
);
493 spin_unlock(&gpmc_mem_lock
);
498 static int gpmc_cs_delete_mem(int cs
)
500 struct resource
*res
= &gpmc_cs_mem
[cs
];
503 spin_lock(&gpmc_mem_lock
);
504 r
= release_resource(res
);
507 spin_unlock(&gpmc_mem_lock
);
513 * gpmc_cs_remap - remaps a chip-select physical base address
514 * @cs: chip-select to remap
515 * @base: physical base address to re-map chip-select to
517 * Re-maps a chip-select to a new physical base address specified by
518 * "base". Returns 0 on success and appropriate negative error code
521 static int gpmc_cs_remap(int cs
, u32 base
)
526 if (cs
> gpmc_cs_num
) {
527 pr_err("%s: requested chip-select is disabled\n", __func__
);
532 * Make sure we ignore any device offsets from the GPMC partition
533 * allocated for the chip select and that the new base confirms
534 * to the GPMC 16MB minimum granularity.
536 base
&= ~(SZ_16M
- 1);
538 gpmc_cs_get_memconf(cs
, &old_base
, &size
);
539 if (base
== old_base
)
541 gpmc_cs_disable_mem(cs
);
542 ret
= gpmc_cs_delete_mem(cs
);
545 ret
= gpmc_cs_insert_mem(cs
, base
, size
);
548 ret
= gpmc_cs_enable_mem(cs
, base
, size
);
555 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
557 struct resource
*res
= &gpmc_cs_mem
[cs
];
560 if (cs
> gpmc_cs_num
) {
561 pr_err("%s: requested chip-select is disabled\n", __func__
);
564 size
= gpmc_mem_align(size
);
565 if (size
> (1 << GPMC_SECTION_SHIFT
))
568 spin_lock(&gpmc_mem_lock
);
569 if (gpmc_cs_reserved(cs
)) {
573 if (gpmc_cs_mem_enabled(cs
))
574 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
576 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
581 r
= gpmc_cs_enable_mem(cs
, res
->start
, resource_size(res
));
583 release_resource(res
);
588 gpmc_cs_set_reserved(cs
, 1);
590 spin_unlock(&gpmc_mem_lock
);
593 EXPORT_SYMBOL(gpmc_cs_request
);
595 void gpmc_cs_free(int cs
)
597 struct resource
*res
= &gpmc_cs_mem
[cs
];
599 spin_lock(&gpmc_mem_lock
);
600 if (cs
>= gpmc_cs_num
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
601 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
603 spin_unlock(&gpmc_mem_lock
);
606 gpmc_cs_disable_mem(cs
);
608 release_resource(res
);
609 gpmc_cs_set_reserved(cs
, 0);
610 spin_unlock(&gpmc_mem_lock
);
612 EXPORT_SYMBOL(gpmc_cs_free
);
615 * gpmc_configure - write request to configure gpmc
617 * @wval: value to write
618 * @return status of the operation
620 int gpmc_configure(int cmd
, int wval
)
625 case GPMC_ENABLE_IRQ
:
626 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
629 case GPMC_SET_IRQ_STATUS
:
630 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
634 regval
= gpmc_read_reg(GPMC_CONFIG
);
636 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
638 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
639 gpmc_write_reg(GPMC_CONFIG
, regval
);
643 pr_err("%s: command not supported\n", __func__
);
649 EXPORT_SYMBOL(gpmc_configure
);
651 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
655 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
656 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
657 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
658 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
659 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
660 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
661 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
662 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
663 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
664 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
665 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
666 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
667 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
668 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
669 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
671 for (i
= 0; i
< GPMC_BCH_NUM_REMAINDER
; i
++) {
672 reg
->gpmc_bch_result0
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_0
+
674 reg
->gpmc_bch_result1
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_1
+
676 reg
->gpmc_bch_result2
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_2
+
678 reg
->gpmc_bch_result3
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_3
+
683 int gpmc_get_client_irq(unsigned irq_config
)
687 if (hweight32(irq_config
) > 1)
690 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
691 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
692 return gpmc_client_irq
[i
].irq
;
697 static int gpmc_irq_endis(unsigned irq
, bool endis
)
702 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
703 if (irq
== gpmc_client_irq
[i
].irq
) {
704 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
706 regval
|= gpmc_client_irq
[i
].bitmask
;
708 regval
&= ~gpmc_client_irq
[i
].bitmask
;
709 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
716 static void gpmc_irq_disable(struct irq_data
*p
)
718 gpmc_irq_endis(p
->irq
, false);
721 static void gpmc_irq_enable(struct irq_data
*p
)
723 gpmc_irq_endis(p
->irq
, true);
726 static void gpmc_irq_noop(struct irq_data
*data
) { }
728 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
730 static int gpmc_setup_irq(void)
738 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
739 if (gpmc_irq_start
< 0) {
740 pr_err("irq_alloc_descs failed\n");
741 return gpmc_irq_start
;
744 gpmc_irq_chip
.name
= "gpmc";
745 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
746 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
747 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
748 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
749 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
750 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
751 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
753 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
754 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
756 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
757 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
758 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
759 &gpmc_irq_chip
, handle_simple_irq
);
760 set_irq_flags(gpmc_client_irq
[i
].irq
,
761 IRQF_VALID
| IRQF_NOAUTOEN
);
764 /* Disable interrupts */
765 gpmc_write_reg(GPMC_IRQENABLE
, 0);
767 /* clear interrupts */
768 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
769 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
771 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
774 static int gpmc_free_irq(void)
779 free_irq(gpmc_irq
, NULL
);
781 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
782 irq_set_handler(gpmc_client_irq
[i
].irq
, NULL
);
783 irq_set_chip(gpmc_client_irq
[i
].irq
, &no_irq_chip
);
784 irq_modify_status(gpmc_client_irq
[i
].irq
, 0, 0);
787 irq_free_descs(gpmc_irq_start
, GPMC_NR_IRQ
);
792 static void gpmc_mem_exit(void)
796 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
797 if (!gpmc_cs_mem_enabled(cs
))
799 gpmc_cs_delete_mem(cs
);
804 static void gpmc_mem_init(void)
809 * The first 1MB of GPMC address space is typically mapped to
810 * the internal ROM. Never allocate the first page, to
811 * facilitate bug detection; even if we didn't boot from ROM.
813 gpmc_mem_root
.start
= SZ_1M
;
814 gpmc_mem_root
.end
= GPMC_MEM_END
;
816 /* Reserve all regions that has been set up by bootloader */
817 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
820 if (!gpmc_cs_mem_enabled(cs
))
822 gpmc_cs_get_memconf(cs
, &base
, &size
);
823 if (gpmc_cs_insert_mem(cs
, base
, size
)) {
824 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
825 __func__
, cs
, base
, base
+ size
);
826 gpmc_cs_disable_mem(cs
);
831 static u32
gpmc_round_ps_to_sync_clk(u32 time_ps
, u32 sync_clk
)
836 div
= gpmc_calc_divider(sync_clk
);
837 temp
= gpmc_ps_to_ticks(time_ps
);
838 temp
= (temp
+ div
- 1) / div
;
839 return gpmc_ticks_to_ps(temp
* div
);
842 /* XXX: can the cycles be avoided ? */
843 static int gpmc_calc_sync_read_timings(struct gpmc_timings
*gpmc_t
,
844 struct gpmc_device_timings
*dev_t
,
850 temp
= dev_t
->t_avdp_r
;
851 /* XXX: mux check required ? */
853 /* XXX: t_avdp not to be required for sync, only added for tusb
854 * this indirectly necessitates requirement of t_avdp_r and
855 * t_avdp_w instead of having a single t_avdp
857 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
858 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
860 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
863 temp
= dev_t
->t_oeasu
; /* XXX: remove this ? */
865 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_ach
);
866 temp
= max_t(u32
, temp
, gpmc_t
->adv_rd_off
+
867 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_oe
));
869 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
872 /* XXX: any scope for improvement ?, by combining oe_on
873 * and clk_activation, need to check whether
874 * access = clk_activation + round to sync clk ?
876 temp
= max_t(u32
, dev_t
->t_iaa
, dev_t
->cyc_iaa
* gpmc_t
->sync_clk
);
877 temp
+= gpmc_t
->clk_activation
;
879 temp
= max_t(u32
, temp
, gpmc_t
->oe_on
+
880 gpmc_ticks_to_ps(dev_t
->cyc_oe
));
881 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
883 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
884 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
887 temp
= max_t(u32
, dev_t
->t_cez_r
, dev_t
->t_oez
);
888 temp
= gpmc_round_ps_to_sync_clk(temp
, gpmc_t
->sync_clk
) +
890 /* XXX: barter t_ce_rdyz with t_cez_r ? */
891 if (dev_t
->t_ce_rdyz
)
892 temp
= max_t(u32
, temp
, gpmc_t
->cs_rd_off
+ dev_t
->t_ce_rdyz
);
893 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
898 static int gpmc_calc_sync_write_timings(struct gpmc_timings
*gpmc_t
,
899 struct gpmc_device_timings
*dev_t
,
905 temp
= dev_t
->t_avdp_w
;
907 temp
= max_t(u32
, temp
,
908 gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
909 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
911 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
913 /* wr_data_mux_bus */
914 temp
= max_t(u32
, dev_t
->t_weasu
,
915 gpmc_t
->clk_activation
+ dev_t
->t_rdyo
);
916 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
917 * and in that case remember to handle we_on properly
920 temp
= max_t(u32
, temp
,
921 gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
922 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
923 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
925 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
928 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
929 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
931 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
934 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
935 gpmc_t
->wr_access
= gpmc_t
->access
;
938 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
939 temp
= max_t(u32
, temp
,
940 gpmc_t
->wr_access
+ gpmc_ticks_to_ps(1));
941 temp
= max_t(u32
, temp
,
942 gpmc_t
->we_on
+ gpmc_ticks_to_ps(dev_t
->cyc_wpl
));
943 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
945 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
949 temp
= gpmc_round_ps_to_sync_clk(dev_t
->t_cez_w
, gpmc_t
->sync_clk
);
950 temp
+= gpmc_t
->wr_access
;
951 /* XXX: barter t_ce_rdyz with t_cez_w ? */
952 if (dev_t
->t_ce_rdyz
)
953 temp
= max_t(u32
, temp
,
954 gpmc_t
->cs_wr_off
+ dev_t
->t_ce_rdyz
);
955 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
960 static int gpmc_calc_async_read_timings(struct gpmc_timings
*gpmc_t
,
961 struct gpmc_device_timings
*dev_t
,
967 temp
= dev_t
->t_avdp_r
;
969 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
970 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
973 temp
= dev_t
->t_oeasu
;
975 temp
= max_t(u32
, temp
,
976 gpmc_t
->adv_rd_off
+ dev_t
->t_aavdh
);
977 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
980 temp
= max_t(u32
, dev_t
->t_iaa
, /* XXX: remove t_iaa in async ? */
981 gpmc_t
->oe_on
+ dev_t
->t_oe
);
982 temp
= max_t(u32
, temp
,
983 gpmc_t
->cs_on
+ dev_t
->t_ce
);
984 temp
= max_t(u32
, temp
,
985 gpmc_t
->adv_on
+ dev_t
->t_aa
);
986 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
988 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
989 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
992 temp
= max_t(u32
, dev_t
->t_rd_cycle
,
993 gpmc_t
->cs_rd_off
+ dev_t
->t_cez_r
);
994 temp
= max_t(u32
, temp
, gpmc_t
->oe_off
+ dev_t
->t_oez
);
995 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
1000 static int gpmc_calc_async_write_timings(struct gpmc_timings
*gpmc_t
,
1001 struct gpmc_device_timings
*dev_t
,
1007 temp
= dev_t
->t_avdp_w
;
1009 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1010 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
1012 /* wr_data_mux_bus */
1013 temp
= dev_t
->t_weasu
;
1015 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1016 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1017 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1019 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1022 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1023 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1025 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1028 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1029 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1031 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1035 temp
= max_t(u32
, dev_t
->t_wr_cycle
,
1036 gpmc_t
->cs_wr_off
+ dev_t
->t_cez_w
);
1037 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1042 static int gpmc_calc_sync_common_timings(struct gpmc_timings
*gpmc_t
,
1043 struct gpmc_device_timings
*dev_t
)
1047 gpmc_t
->sync_clk
= gpmc_calc_divider(dev_t
->clk
) *
1048 gpmc_get_fclk_period();
1050 gpmc_t
->page_burst_access
= gpmc_round_ps_to_sync_clk(
1054 temp
= max_t(u32
, dev_t
->t_ces
, dev_t
->t_avds
);
1055 gpmc_t
->clk_activation
= gpmc_round_ps_to_ticks(temp
);
1057 if (gpmc_calc_divider(gpmc_t
->sync_clk
) != 1)
1060 if (dev_t
->ce_xdelay
)
1061 gpmc_t
->bool_timings
.cs_extra_delay
= true;
1062 if (dev_t
->avd_xdelay
)
1063 gpmc_t
->bool_timings
.adv_extra_delay
= true;
1064 if (dev_t
->oe_xdelay
)
1065 gpmc_t
->bool_timings
.oe_extra_delay
= true;
1066 if (dev_t
->we_xdelay
)
1067 gpmc_t
->bool_timings
.we_extra_delay
= true;
1072 static int gpmc_calc_common_timings(struct gpmc_timings
*gpmc_t
,
1073 struct gpmc_device_timings
*dev_t
,
1079 gpmc_t
->cs_on
= gpmc_round_ps_to_ticks(dev_t
->t_ceasu
);
1082 temp
= dev_t
->t_avdasu
;
1083 if (dev_t
->t_ce_avd
)
1084 temp
= max_t(u32
, temp
,
1085 gpmc_t
->cs_on
+ dev_t
->t_ce_avd
);
1086 gpmc_t
->adv_on
= gpmc_round_ps_to_ticks(temp
);
1089 gpmc_calc_sync_common_timings(gpmc_t
, dev_t
);
1094 /* TODO: remove this function once all peripherals are confirmed to
1095 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1096 * has to be modified to handle timings in ps instead of ns
1098 static void gpmc_convert_ps_to_ns(struct gpmc_timings
*t
)
1101 t
->cs_rd_off
/= 1000;
1102 t
->cs_wr_off
/= 1000;
1104 t
->adv_rd_off
/= 1000;
1105 t
->adv_wr_off
/= 1000;
1110 t
->page_burst_access
/= 1000;
1112 t
->rd_cycle
/= 1000;
1113 t
->wr_cycle
/= 1000;
1114 t
->bus_turnaround
/= 1000;
1115 t
->cycle2cycle_delay
/= 1000;
1116 t
->wait_monitoring
/= 1000;
1117 t
->clk_activation
/= 1000;
1118 t
->wr_access
/= 1000;
1119 t
->wr_data_mux_bus
/= 1000;
1122 int gpmc_calc_timings(struct gpmc_timings
*gpmc_t
,
1123 struct gpmc_settings
*gpmc_s
,
1124 struct gpmc_device_timings
*dev_t
)
1126 bool mux
= false, sync
= false;
1129 mux
= gpmc_s
->mux_add_data
? true : false;
1130 sync
= (gpmc_s
->sync_read
|| gpmc_s
->sync_write
);
1133 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1135 gpmc_calc_common_timings(gpmc_t
, dev_t
, sync
);
1137 if (gpmc_s
&& gpmc_s
->sync_read
)
1138 gpmc_calc_sync_read_timings(gpmc_t
, dev_t
, mux
);
1140 gpmc_calc_async_read_timings(gpmc_t
, dev_t
, mux
);
1142 if (gpmc_s
&& gpmc_s
->sync_write
)
1143 gpmc_calc_sync_write_timings(gpmc_t
, dev_t
, mux
);
1145 gpmc_calc_async_write_timings(gpmc_t
, dev_t
, mux
);
1147 /* TODO: remove, see function definition */
1148 gpmc_convert_ps_to_ns(gpmc_t
);
1154 * gpmc_cs_program_settings - programs non-timing related settings
1155 * @cs: GPMC chip-select to program
1156 * @p: pointer to GPMC settings structure
1158 * Programs non-timing related settings for a GPMC chip-select, such as
1159 * bus-width, burst configuration, etc. Function should be called once
1160 * for each chip-select that is being used and must be called before
1161 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1162 * register will be initialised to zero by this function. Returns 0 on
1163 * success and appropriate negative error code on failure.
1165 int gpmc_cs_program_settings(int cs
, struct gpmc_settings
*p
)
1169 if ((!p
->device_width
) || (p
->device_width
> GPMC_DEVWIDTH_16BIT
)) {
1170 pr_err("%s: invalid width %d!", __func__
, p
->device_width
);
1174 /* Address-data multiplexing not supported for NAND devices */
1175 if (p
->device_nand
&& p
->mux_add_data
) {
1176 pr_err("%s: invalid configuration!\n", __func__
);
1180 if ((p
->mux_add_data
> GPMC_MUX_AD
) ||
1181 ((p
->mux_add_data
== GPMC_MUX_AAD
) &&
1182 !(gpmc_capability
& GPMC_HAS_MUX_AAD
))) {
1183 pr_err("%s: invalid multiplex configuration!\n", __func__
);
1187 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1188 if (p
->burst_read
|| p
->burst_write
) {
1189 switch (p
->burst_len
) {
1195 pr_err("%s: invalid page/burst-length (%d)\n",
1196 __func__
, p
->burst_len
);
1201 if ((p
->wait_on_read
|| p
->wait_on_write
) &&
1202 (p
->wait_pin
> gpmc_nr_waitpins
)) {
1203 pr_err("%s: invalid wait-pin (%d)\n", __func__
, p
->wait_pin
);
1207 config1
= GPMC_CONFIG1_DEVICESIZE((p
->device_width
- 1));
1210 config1
|= GPMC_CONFIG1_READTYPE_SYNC
;
1212 config1
|= GPMC_CONFIG1_WRITETYPE_SYNC
;
1213 if (p
->wait_on_read
)
1214 config1
|= GPMC_CONFIG1_WAIT_READ_MON
;
1215 if (p
->wait_on_write
)
1216 config1
|= GPMC_CONFIG1_WAIT_WRITE_MON
;
1217 if (p
->wait_on_read
|| p
->wait_on_write
)
1218 config1
|= GPMC_CONFIG1_WAIT_PIN_SEL(p
->wait_pin
);
1220 config1
|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND
);
1221 if (p
->mux_add_data
)
1222 config1
|= GPMC_CONFIG1_MUXTYPE(p
->mux_add_data
);
1224 config1
|= GPMC_CONFIG1_READMULTIPLE_SUPP
;
1226 config1
|= GPMC_CONFIG1_WRITEMULTIPLE_SUPP
;
1227 if (p
->burst_read
|| p
->burst_write
) {
1228 config1
|= GPMC_CONFIG1_PAGE_LEN(p
->burst_len
>> 3);
1229 config1
|= p
->burst_wrap
? GPMC_CONFIG1_WRAPBURST_SUPP
: 0;
1232 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, config1
);
1238 static struct of_device_id gpmc_dt_ids
[] = {
1239 { .compatible
= "ti,omap2420-gpmc" },
1240 { .compatible
= "ti,omap2430-gpmc" },
1241 { .compatible
= "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1242 { .compatible
= "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1243 { .compatible
= "ti,am3352-gpmc" }, /* am335x devices */
1246 MODULE_DEVICE_TABLE(of
, gpmc_dt_ids
);
1249 * gpmc_read_settings_dt - read gpmc settings from device-tree
1250 * @np: pointer to device-tree node for a gpmc child device
1251 * @p: pointer to gpmc settings structure
1253 * Reads the GPMC settings for a GPMC child device from device-tree and
1254 * stores them in the GPMC settings structure passed. The GPMC settings
1255 * structure is initialised to zero by this function and so any
1256 * previously stored settings will be cleared.
1258 void gpmc_read_settings_dt(struct device_node
*np
, struct gpmc_settings
*p
)
1260 memset(p
, 0, sizeof(struct gpmc_settings
));
1262 p
->sync_read
= of_property_read_bool(np
, "gpmc,sync-read");
1263 p
->sync_write
= of_property_read_bool(np
, "gpmc,sync-write");
1264 of_property_read_u32(np
, "gpmc,device-width", &p
->device_width
);
1265 of_property_read_u32(np
, "gpmc,mux-add-data", &p
->mux_add_data
);
1267 if (!of_property_read_u32(np
, "gpmc,burst-length", &p
->burst_len
)) {
1268 p
->burst_wrap
= of_property_read_bool(np
, "gpmc,burst-wrap");
1269 p
->burst_read
= of_property_read_bool(np
, "gpmc,burst-read");
1270 p
->burst_write
= of_property_read_bool(np
, "gpmc,burst-write");
1271 if (!p
->burst_read
&& !p
->burst_write
)
1272 pr_warn("%s: page/burst-length set but not used!\n",
1276 if (!of_property_read_u32(np
, "gpmc,wait-pin", &p
->wait_pin
)) {
1277 p
->wait_on_read
= of_property_read_bool(np
,
1278 "gpmc,wait-on-read");
1279 p
->wait_on_write
= of_property_read_bool(np
,
1280 "gpmc,wait-on-write");
1281 if (!p
->wait_on_read
&& !p
->wait_on_write
)
1282 pr_warn("%s: read/write wait monitoring not enabled!\n",
1287 static void __maybe_unused
gpmc_read_timings_dt(struct device_node
*np
,
1288 struct gpmc_timings
*gpmc_t
)
1290 struct gpmc_bool_timings
*p
;
1295 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1297 /* minimum clock period for syncronous mode */
1298 of_property_read_u32(np
, "gpmc,sync-clk-ps", &gpmc_t
->sync_clk
);
1300 /* chip select timtings */
1301 of_property_read_u32(np
, "gpmc,cs-on-ns", &gpmc_t
->cs_on
);
1302 of_property_read_u32(np
, "gpmc,cs-rd-off-ns", &gpmc_t
->cs_rd_off
);
1303 of_property_read_u32(np
, "gpmc,cs-wr-off-ns", &gpmc_t
->cs_wr_off
);
1305 /* ADV signal timings */
1306 of_property_read_u32(np
, "gpmc,adv-on-ns", &gpmc_t
->adv_on
);
1307 of_property_read_u32(np
, "gpmc,adv-rd-off-ns", &gpmc_t
->adv_rd_off
);
1308 of_property_read_u32(np
, "gpmc,adv-wr-off-ns", &gpmc_t
->adv_wr_off
);
1310 /* WE signal timings */
1311 of_property_read_u32(np
, "gpmc,we-on-ns", &gpmc_t
->we_on
);
1312 of_property_read_u32(np
, "gpmc,we-off-ns", &gpmc_t
->we_off
);
1314 /* OE signal timings */
1315 of_property_read_u32(np
, "gpmc,oe-on-ns", &gpmc_t
->oe_on
);
1316 of_property_read_u32(np
, "gpmc,oe-off-ns", &gpmc_t
->oe_off
);
1318 /* access and cycle timings */
1319 of_property_read_u32(np
, "gpmc,page-burst-access-ns",
1320 &gpmc_t
->page_burst_access
);
1321 of_property_read_u32(np
, "gpmc,access-ns", &gpmc_t
->access
);
1322 of_property_read_u32(np
, "gpmc,rd-cycle-ns", &gpmc_t
->rd_cycle
);
1323 of_property_read_u32(np
, "gpmc,wr-cycle-ns", &gpmc_t
->wr_cycle
);
1324 of_property_read_u32(np
, "gpmc,bus-turnaround-ns",
1325 &gpmc_t
->bus_turnaround
);
1326 of_property_read_u32(np
, "gpmc,cycle2cycle-delay-ns",
1327 &gpmc_t
->cycle2cycle_delay
);
1328 of_property_read_u32(np
, "gpmc,wait-monitoring-ns",
1329 &gpmc_t
->wait_monitoring
);
1330 of_property_read_u32(np
, "gpmc,clk-activation-ns",
1331 &gpmc_t
->clk_activation
);
1333 /* only applicable to OMAP3+ */
1334 of_property_read_u32(np
, "gpmc,wr-access-ns", &gpmc_t
->wr_access
);
1335 of_property_read_u32(np
, "gpmc,wr-data-mux-bus-ns",
1336 &gpmc_t
->wr_data_mux_bus
);
1338 /* bool timing parameters */
1339 p
= &gpmc_t
->bool_timings
;
1341 p
->cycle2cyclediffcsen
=
1342 of_property_read_bool(np
, "gpmc,cycle2cycle-diffcsen");
1343 p
->cycle2cyclesamecsen
=
1344 of_property_read_bool(np
, "gpmc,cycle2cycle-samecsen");
1345 p
->we_extra_delay
= of_property_read_bool(np
, "gpmc,we-extra-delay");
1346 p
->oe_extra_delay
= of_property_read_bool(np
, "gpmc,oe-extra-delay");
1347 p
->adv_extra_delay
= of_property_read_bool(np
, "gpmc,adv-extra-delay");
1348 p
->cs_extra_delay
= of_property_read_bool(np
, "gpmc,cs-extra-delay");
1349 p
->time_para_granularity
=
1350 of_property_read_bool(np
, "gpmc,time-para-granularity");
1353 #if IS_ENABLED(CONFIG_MTD_NAND)
1355 static const char * const nand_xfer_types
[] = {
1356 [NAND_OMAP_PREFETCH_POLLED
] = "prefetch-polled",
1357 [NAND_OMAP_POLLED
] = "polled",
1358 [NAND_OMAP_PREFETCH_DMA
] = "prefetch-dma",
1359 [NAND_OMAP_PREFETCH_IRQ
] = "prefetch-irq",
1362 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1363 struct device_node
*child
)
1367 struct gpmc_timings gpmc_t
;
1368 struct omap_nand_platform_data
*gpmc_nand_data
;
1370 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1371 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1376 gpmc_nand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_nand_data
),
1378 if (!gpmc_nand_data
)
1381 gpmc_nand_data
->cs
= val
;
1382 gpmc_nand_data
->of_node
= child
;
1384 /* Detect availability of ELM module */
1385 gpmc_nand_data
->elm_of_node
= of_parse_phandle(child
, "ti,elm-id", 0);
1386 if (gpmc_nand_data
->elm_of_node
== NULL
)
1387 gpmc_nand_data
->elm_of_node
=
1388 of_parse_phandle(child
, "elm_id", 0);
1389 if (gpmc_nand_data
->elm_of_node
== NULL
)
1390 pr_warn("%s: ti,elm-id property not found\n", __func__
);
1392 /* select ecc-scheme for NAND */
1393 if (of_property_read_string(child
, "ti,nand-ecc-opt", &s
)) {
1394 pr_err("%s: ti,nand-ecc-opt not found\n", __func__
);
1397 if (!strcmp(s
, "ham1") || !strcmp(s
, "sw") ||
1398 !strcmp(s
, "hw") || !strcmp(s
, "hw-romcode"))
1399 gpmc_nand_data
->ecc_opt
=
1400 OMAP_ECC_HAM1_CODE_HW
;
1401 else if (!strcmp(s
, "bch4"))
1402 if (gpmc_nand_data
->elm_of_node
)
1403 gpmc_nand_data
->ecc_opt
=
1404 OMAP_ECC_BCH4_CODE_HW
;
1406 gpmc_nand_data
->ecc_opt
=
1407 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
;
1408 else if (!strcmp(s
, "bch8"))
1409 if (gpmc_nand_data
->elm_of_node
)
1410 gpmc_nand_data
->ecc_opt
=
1411 OMAP_ECC_BCH8_CODE_HW
;
1413 gpmc_nand_data
->ecc_opt
=
1414 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
;
1416 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__
);
1418 /* select data transfer mode for NAND controller */
1419 if (!of_property_read_string(child
, "ti,nand-xfer-type", &s
))
1420 for (val
= 0; val
< ARRAY_SIZE(nand_xfer_types
); val
++)
1421 if (!strcasecmp(s
, nand_xfer_types
[val
])) {
1422 gpmc_nand_data
->xfer_type
= val
;
1426 val
= of_get_nand_bus_width(child
);
1428 gpmc_nand_data
->devsize
= NAND_BUSWIDTH_16
;
1430 gpmc_read_timings_dt(child
, &gpmc_t
);
1431 gpmc_nand_init(gpmc_nand_data
, &gpmc_t
);
1436 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1437 struct device_node
*child
)
1443 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1444 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1445 struct device_node
*child
)
1448 struct omap_onenand_platform_data
*gpmc_onenand_data
;
1450 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1451 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1456 gpmc_onenand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_onenand_data
),
1458 if (!gpmc_onenand_data
)
1461 gpmc_onenand_data
->cs
= val
;
1462 gpmc_onenand_data
->of_node
= child
;
1463 gpmc_onenand_data
->dma_channel
= -1;
1465 if (!of_property_read_u32(child
, "dma-channel", &val
))
1466 gpmc_onenand_data
->dma_channel
= val
;
1468 gpmc_onenand_init(gpmc_onenand_data
);
1473 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1474 struct device_node
*child
)
1481 * gpmc_probe_generic_child - configures the gpmc for a child device
1482 * @pdev: pointer to gpmc platform device
1483 * @child: pointer to device-tree node for child device
1485 * Allocates and configures a GPMC chip-select for a child device.
1486 * Returns 0 on success and appropriate negative error code on failure.
1488 static int gpmc_probe_generic_child(struct platform_device
*pdev
,
1489 struct device_node
*child
)
1491 struct gpmc_settings gpmc_s
;
1492 struct gpmc_timings gpmc_t
;
1493 struct resource res
;
1497 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1498 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1503 if (of_address_to_resource(child
, 0, &res
) < 0) {
1504 dev_err(&pdev
->dev
, "%s has malformed 'reg' property\n",
1509 ret
= gpmc_cs_request(cs
, resource_size(&res
), &base
);
1511 dev_err(&pdev
->dev
, "cannot request GPMC CS %d\n", cs
);
1516 * For some GPMC devices we still need to rely on the bootloader
1517 * timings because the devices can be connected via FPGA. So far
1518 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
1519 * REVISIT: Add timing support from slls644g.pdf and from the
1522 if (of_device_is_compatible(child
, "ns16550a") ||
1523 of_device_is_compatible(child
, "smsc,lan91c94") ||
1524 of_device_is_compatible(child
, "smsc,lan91c111")) {
1525 dev_warn(&pdev
->dev
,
1526 "%s using bootloader timings on CS%d\n",
1532 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1533 * location in the gpmc address space. When booting with
1534 * device-tree we want the NOR flash to be mapped to the
1535 * location specified in the device-tree blob. So remap the
1536 * CS to this location. Once DT migration is complete should
1537 * just make gpmc_cs_request() map a specific address.
1539 ret
= gpmc_cs_remap(cs
, res
.start
);
1541 dev_err(&pdev
->dev
, "cannot remap GPMC CS %d to %pa\n",
1546 gpmc_read_settings_dt(child
, &gpmc_s
);
1548 ret
= of_property_read_u32(child
, "bank-width", &gpmc_s
.device_width
);
1552 ret
= gpmc_cs_program_settings(cs
, &gpmc_s
);
1556 gpmc_read_timings_dt(child
, &gpmc_t
);
1557 gpmc_cs_set_timings(cs
, &gpmc_t
);
1560 if (of_platform_device_create(child
, NULL
, &pdev
->dev
))
1563 dev_err(&pdev
->dev
, "failed to create gpmc child %s\n", child
->name
);
1572 static int gpmc_probe_dt(struct platform_device
*pdev
)
1575 struct device_node
*child
;
1576 const struct of_device_id
*of_id
=
1577 of_match_device(gpmc_dt_ids
, &pdev
->dev
);
1582 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-cs",
1585 pr_err("%s: number of chip-selects not defined\n", __func__
);
1587 } else if (gpmc_cs_num
< 1) {
1588 pr_err("%s: all chip-selects are disabled\n", __func__
);
1590 } else if (gpmc_cs_num
> GPMC_CS_NUM
) {
1591 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1592 __func__
, GPMC_CS_NUM
);
1596 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-waitpins",
1599 pr_err("%s: number of wait pins not found!\n", __func__
);
1603 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
1608 if (of_node_cmp(child
->name
, "nand") == 0)
1609 ret
= gpmc_probe_nand_child(pdev
, child
);
1610 else if (of_node_cmp(child
->name
, "onenand") == 0)
1611 ret
= gpmc_probe_onenand_child(pdev
, child
);
1612 else if (of_node_cmp(child
->name
, "ethernet") == 0 ||
1613 of_node_cmp(child
->name
, "nor") == 0 ||
1614 of_node_cmp(child
->name
, "uart") == 0)
1615 ret
= gpmc_probe_generic_child(pdev
, child
);
1617 if (WARN(ret
< 0, "%s: probing gpmc child %s failed\n",
1618 __func__
, child
->full_name
))
1625 static int gpmc_probe_dt(struct platform_device
*pdev
)
1631 static int gpmc_probe(struct platform_device
*pdev
)
1635 struct resource
*res
;
1637 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1641 phys_base
= res
->start
;
1642 mem_size
= resource_size(res
);
1644 gpmc_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1645 if (IS_ERR(gpmc_base
))
1646 return PTR_ERR(gpmc_base
);
1648 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1650 dev_warn(&pdev
->dev
, "Failed to get resource: irq\n");
1652 gpmc_irq
= res
->start
;
1654 gpmc_l3_clk
= clk_get(&pdev
->dev
, "fck");
1655 if (IS_ERR(gpmc_l3_clk
)) {
1656 dev_err(&pdev
->dev
, "error: clk_get\n");
1658 return PTR_ERR(gpmc_l3_clk
);
1661 pm_runtime_enable(&pdev
->dev
);
1662 pm_runtime_get_sync(&pdev
->dev
);
1664 gpmc_dev
= &pdev
->dev
;
1666 l
= gpmc_read_reg(GPMC_REVISION
);
1669 * FIXME: Once device-tree migration is complete the below flags
1670 * should be populated based upon the device-tree compatible
1671 * string. For now just use the IP revision. OMAP3+ devices have
1672 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1673 * devices support the addr-addr-data multiplex protocol.
1675 * GPMC IP revisions:
1678 * - OMAP44xx/54xx/AM335x = 6.0
1680 if (GPMC_REVISION_MAJOR(l
) > 0x4)
1681 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
1682 if (GPMC_REVISION_MAJOR(l
) > 0x5)
1683 gpmc_capability
|= GPMC_HAS_MUX_AAD
;
1684 dev_info(gpmc_dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
1685 GPMC_REVISION_MINOR(l
));
1689 if (gpmc_setup_irq() < 0)
1690 dev_warn(gpmc_dev
, "gpmc_setup_irq failed\n");
1692 /* Now the GPMC is initialised, unreserve the chip-selects */
1695 if (!pdev
->dev
.of_node
) {
1696 gpmc_cs_num
= GPMC_CS_NUM
;
1697 gpmc_nr_waitpins
= GPMC_NR_WAITPINS
;
1700 rc
= gpmc_probe_dt(pdev
);
1702 pm_runtime_put_sync(&pdev
->dev
);
1703 clk_put(gpmc_l3_clk
);
1704 dev_err(gpmc_dev
, "failed to probe DT parameters\n");
1711 static int gpmc_remove(struct platform_device
*pdev
)
1715 pm_runtime_put_sync(&pdev
->dev
);
1716 pm_runtime_disable(&pdev
->dev
);
1721 #ifdef CONFIG_PM_SLEEP
1722 static int gpmc_suspend(struct device
*dev
)
1724 omap3_gpmc_save_context();
1725 pm_runtime_put_sync(dev
);
1729 static int gpmc_resume(struct device
*dev
)
1731 pm_runtime_get_sync(dev
);
1732 omap3_gpmc_restore_context();
1737 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops
, gpmc_suspend
, gpmc_resume
);
1739 static struct platform_driver gpmc_driver
= {
1740 .probe
= gpmc_probe
,
1741 .remove
= gpmc_remove
,
1743 .name
= DEVICE_NAME
,
1744 .owner
= THIS_MODULE
,
1745 .of_match_table
= of_match_ptr(gpmc_dt_ids
),
1750 static __init
int gpmc_init(void)
1752 return platform_driver_register(&gpmc_driver
);
1755 static __exit
void gpmc_exit(void)
1757 platform_driver_unregister(&gpmc_driver
);
1761 omap_postcore_initcall(gpmc_init
);
1762 module_exit(gpmc_exit
);
1764 static int __init
omap_gpmc_init(void)
1766 struct omap_hwmod
*oh
;
1767 struct platform_device
*pdev
;
1768 char *oh_name
= "gpmc";
1771 * if the board boots up with a populated DT, do not
1772 * manually add the device from this initcall
1774 if (of_have_populated_dt())
1777 oh
= omap_hwmod_lookup(oh_name
);
1779 pr_err("Could not look up %s\n", oh_name
);
1783 pdev
= omap_device_build(DEVICE_NAME
, -1, oh
, NULL
, 0);
1784 WARN(IS_ERR(pdev
), "could not build omap_device for %s\n", oh_name
);
1786 return PTR_RET(pdev
);
1788 omap_postcore_initcall(omap_gpmc_init
);
1790 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
1795 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1800 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
1801 if (regval
& gpmc_client_irq
[i
].bitmask
)
1802 generic_handle_irq(gpmc_client_irq
[i
].irq
);
1804 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1809 static struct omap3_gpmc_regs gpmc_context
;
1811 void omap3_gpmc_save_context(void)
1815 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
1816 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
1817 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
1818 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
1819 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
1820 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
1821 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
1822 for (i
= 0; i
< gpmc_cs_num
; i
++) {
1823 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
1824 if (gpmc_context
.cs_context
[i
].is_valid
) {
1825 gpmc_context
.cs_context
[i
].config1
=
1826 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
1827 gpmc_context
.cs_context
[i
].config2
=
1828 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
1829 gpmc_context
.cs_context
[i
].config3
=
1830 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
1831 gpmc_context
.cs_context
[i
].config4
=
1832 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
1833 gpmc_context
.cs_context
[i
].config5
=
1834 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
1835 gpmc_context
.cs_context
[i
].config6
=
1836 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
1837 gpmc_context
.cs_context
[i
].config7
=
1838 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
1843 void omap3_gpmc_restore_context(void)
1847 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
1848 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
1849 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
1850 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
1851 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
1852 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
1853 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
1854 for (i
= 0; i
< gpmc_cs_num
; i
++) {
1855 if (gpmc_context
.cs_context
[i
].is_valid
) {
1856 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
1857 gpmc_context
.cs_context
[i
].config1
);
1858 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
1859 gpmc_context
.cs_context
[i
].config2
);
1860 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
1861 gpmc_context
.cs_context
[i
].config3
);
1862 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
1863 gpmc_context
.cs_context
[i
].config4
);
1864 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
1865 gpmc_context
.cs_context
[i
].config5
);
1866 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
1867 gpmc_context
.cs_context
[i
].config6
);
1868 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
1869 gpmc_context
.cs_context
[i
].config7
);